1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 * 6 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_device.h> 21 #include <linux/of_irq.h> 22 #include <linux/regmap.h> 23 24 #include "../pinctrl/core.h" 25 #include "../pinctrl/pinctrl-rockchip.h" 26 27 #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */ 28 #define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */ 29 30 static const struct rockchip_gpio_regs gpio_regs_v1 = { 31 .port_dr = 0x00, 32 .port_ddr = 0x04, 33 .int_en = 0x30, 34 .int_mask = 0x34, 35 .int_type = 0x38, 36 .int_polarity = 0x3c, 37 .int_status = 0x40, 38 .int_rawstatus = 0x44, 39 .debounce = 0x48, 40 .port_eoi = 0x4c, 41 .ext_port = 0x50, 42 }; 43 44 static const struct rockchip_gpio_regs gpio_regs_v2 = { 45 .port_dr = 0x00, 46 .port_ddr = 0x08, 47 .int_en = 0x10, 48 .int_mask = 0x18, 49 .int_type = 0x20, 50 .int_polarity = 0x28, 51 .int_bothedge = 0x30, 52 .int_status = 0x50, 53 .int_rawstatus = 0x58, 54 .debounce = 0x38, 55 .dbclk_div_en = 0x40, 56 .dbclk_div_con = 0x48, 57 .port_eoi = 0x60, 58 .ext_port = 0x70, 59 .version_id = 0x78, 60 }; 61 62 static inline void gpio_writel_v2(u32 val, void __iomem *reg) 63 { 64 writel((val & 0xffff) | 0xffff0000, reg); 65 writel((val >> 16) | 0xffff0000, reg + 0x4); 66 } 67 68 static inline u32 gpio_readl_v2(void __iomem *reg) 69 { 70 return readl(reg + 0x4) << 16 | readl(reg); 71 } 72 73 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, 74 u32 value, unsigned int offset) 75 { 76 void __iomem *reg = bank->reg_base + offset; 77 78 if (bank->gpio_type == GPIO_TYPE_V2) 79 gpio_writel_v2(value, reg); 80 else 81 writel(value, reg); 82 } 83 84 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, 85 unsigned int offset) 86 { 87 void __iomem *reg = bank->reg_base + offset; 88 u32 value; 89 90 if (bank->gpio_type == GPIO_TYPE_V2) 91 value = gpio_readl_v2(reg); 92 else 93 value = readl(reg); 94 95 return value; 96 } 97 98 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, 99 u32 bit, u32 value, 100 unsigned int offset) 101 { 102 void __iomem *reg = bank->reg_base + offset; 103 u32 data; 104 105 if (bank->gpio_type == GPIO_TYPE_V2) { 106 if (value) 107 data = BIT(bit % 16) | BIT(bit % 16 + 16); 108 else 109 data = BIT(bit % 16 + 16); 110 writel(data, bit >= 16 ? reg + 0x4 : reg); 111 } else { 112 data = readl(reg); 113 data &= ~BIT(bit); 114 if (value) 115 data |= BIT(bit); 116 writel(data, reg); 117 } 118 } 119 120 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, 121 u32 bit, unsigned int offset) 122 { 123 void __iomem *reg = bank->reg_base + offset; 124 u32 data; 125 126 if (bank->gpio_type == GPIO_TYPE_V2) { 127 data = readl(bit >= 16 ? reg + 0x4 : reg); 128 data >>= bit % 16; 129 } else { 130 data = readl(reg); 131 data >>= bit; 132 } 133 134 return data & (0x1); 135 } 136 137 static int rockchip_gpio_get_direction(struct gpio_chip *chip, 138 unsigned int offset) 139 { 140 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 141 u32 data; 142 143 data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr); 144 if (data) 145 return GPIO_LINE_DIRECTION_OUT; 146 147 return GPIO_LINE_DIRECTION_IN; 148 } 149 150 static int rockchip_gpio_set_direction(struct gpio_chip *chip, 151 unsigned int offset, bool input) 152 { 153 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 154 unsigned long flags; 155 u32 data = input ? 0 : 1; 156 157 raw_spin_lock_irqsave(&bank->slock, flags); 158 rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr); 159 raw_spin_unlock_irqrestore(&bank->slock, flags); 160 161 return 0; 162 } 163 164 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset, 165 int value) 166 { 167 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 168 unsigned long flags; 169 170 raw_spin_lock_irqsave(&bank->slock, flags); 171 rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr); 172 raw_spin_unlock_irqrestore(&bank->slock, flags); 173 } 174 175 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset) 176 { 177 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 178 u32 data; 179 180 data = readl(bank->reg_base + bank->gpio_regs->ext_port); 181 data >>= offset; 182 data &= 1; 183 184 return data; 185 } 186 187 static int rockchip_gpio_set_debounce(struct gpio_chip *gc, 188 unsigned int offset, 189 unsigned int debounce) 190 { 191 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 192 const struct rockchip_gpio_regs *reg = bank->gpio_regs; 193 unsigned long flags, div_reg, freq, max_debounce; 194 bool div_debounce_support; 195 unsigned int cur_div_reg; 196 u64 div; 197 198 if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) { 199 div_debounce_support = true; 200 freq = clk_get_rate(bank->db_clk); 201 max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq; 202 if (debounce > max_debounce) 203 return -EINVAL; 204 205 div = debounce * freq; 206 div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1; 207 } else { 208 div_debounce_support = false; 209 } 210 211 raw_spin_lock_irqsave(&bank->slock, flags); 212 213 /* Only the v1 needs to configure div_en and div_con for dbclk */ 214 if (debounce) { 215 if (div_debounce_support) { 216 /* Configure the max debounce from consumers */ 217 cur_div_reg = readl(bank->reg_base + 218 reg->dbclk_div_con); 219 if (cur_div_reg < div_reg) 220 writel(div_reg, bank->reg_base + 221 reg->dbclk_div_con); 222 rockchip_gpio_writel_bit(bank, offset, 1, 223 reg->dbclk_div_en); 224 } 225 226 rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce); 227 } else { 228 if (div_debounce_support) 229 rockchip_gpio_writel_bit(bank, offset, 0, 230 reg->dbclk_div_en); 231 232 rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce); 233 } 234 235 raw_spin_unlock_irqrestore(&bank->slock, flags); 236 237 /* Enable or disable dbclk at last */ 238 if (div_debounce_support) { 239 if (debounce) 240 clk_prepare_enable(bank->db_clk); 241 else 242 clk_disable_unprepare(bank->db_clk); 243 } 244 245 return 0; 246 } 247 248 static int rockchip_gpio_direction_input(struct gpio_chip *gc, 249 unsigned int offset) 250 { 251 return rockchip_gpio_set_direction(gc, offset, true); 252 } 253 254 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 255 unsigned int offset, int value) 256 { 257 rockchip_gpio_set(gc, offset, value); 258 259 return rockchip_gpio_set_direction(gc, offset, false); 260 } 261 262 /* 263 * gpiolib set_config callback function. The setting of the pin 264 * mux function as 'gpio output' will be handled by the pinctrl subsystem 265 * interface. 266 */ 267 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 268 unsigned long config) 269 { 270 enum pin_config_param param = pinconf_to_config_param(config); 271 272 switch (param) { 273 case PIN_CONFIG_INPUT_DEBOUNCE: 274 rockchip_gpio_set_debounce(gc, offset, true); 275 /* 276 * Rockchip's gpio could only support up to one period 277 * of the debounce clock(pclk), which is far away from 278 * satisftying the requirement, as pclk is usually near 279 * 100MHz shared by all peripherals. So the fact is it 280 * has crippled debounce capability could only be useful 281 * to prevent any spurious glitches from waking up the system 282 * if the gpio is conguired as wakeup interrupt source. Let's 283 * still return -ENOTSUPP as before, to make sure the caller 284 * of gpiod_set_debounce won't change its behaviour. 285 */ 286 return -ENOTSUPP; 287 default: 288 return -ENOTSUPP; 289 } 290 } 291 292 /* 293 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 294 * and a virtual IRQ, if not already present. 295 */ 296 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) 297 { 298 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 299 unsigned int virq; 300 301 if (!bank->domain) 302 return -ENXIO; 303 304 virq = irq_create_mapping(bank->domain, offset); 305 306 return (virq) ? : -ENXIO; 307 } 308 309 static const struct gpio_chip rockchip_gpiolib_chip = { 310 .request = gpiochip_generic_request, 311 .free = gpiochip_generic_free, 312 .set = rockchip_gpio_set, 313 .get = rockchip_gpio_get, 314 .get_direction = rockchip_gpio_get_direction, 315 .direction_input = rockchip_gpio_direction_input, 316 .direction_output = rockchip_gpio_direction_output, 317 .set_config = rockchip_gpio_set_config, 318 .to_irq = rockchip_gpio_to_irq, 319 .owner = THIS_MODULE, 320 }; 321 322 static void rockchip_irq_demux(struct irq_desc *desc) 323 { 324 struct irq_chip *chip = irq_desc_get_chip(desc); 325 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 326 u32 pend; 327 328 dev_dbg(bank->dev, "got irq for bank %s\n", bank->name); 329 330 chained_irq_enter(chip, desc); 331 332 pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status); 333 334 while (pend) { 335 unsigned int irq, virq; 336 337 irq = __ffs(pend); 338 pend &= ~BIT(irq); 339 virq = irq_find_mapping(bank->domain, irq); 340 341 if (!virq) { 342 dev_err(bank->dev, "unmapped irq %d\n", irq); 343 continue; 344 } 345 346 dev_dbg(bank->dev, "handling irq %d\n", irq); 347 348 /* 349 * Triggering IRQ on both rising and falling edge 350 * needs manual intervention. 351 */ 352 if (bank->toggle_edge_mode & BIT(irq)) { 353 u32 data, data_old, polarity; 354 unsigned long flags; 355 356 data = readl_relaxed(bank->reg_base + 357 bank->gpio_regs->ext_port); 358 do { 359 raw_spin_lock_irqsave(&bank->slock, flags); 360 361 polarity = readl_relaxed(bank->reg_base + 362 bank->gpio_regs->int_polarity); 363 if (data & BIT(irq)) 364 polarity &= ~BIT(irq); 365 else 366 polarity |= BIT(irq); 367 writel(polarity, 368 bank->reg_base + 369 bank->gpio_regs->int_polarity); 370 371 raw_spin_unlock_irqrestore(&bank->slock, flags); 372 373 data_old = data; 374 data = readl_relaxed(bank->reg_base + 375 bank->gpio_regs->ext_port); 376 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 377 } 378 379 generic_handle_irq(virq); 380 } 381 382 chained_irq_exit(chip, desc); 383 } 384 385 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 386 { 387 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 388 struct rockchip_pin_bank *bank = gc->private; 389 u32 mask = BIT(d->hwirq); 390 u32 polarity; 391 u32 level; 392 u32 data; 393 unsigned long flags; 394 int ret = 0; 395 396 raw_spin_lock_irqsave(&bank->slock, flags); 397 398 rockchip_gpio_writel_bit(bank, d->hwirq, 0, 399 bank->gpio_regs->port_ddr); 400 401 raw_spin_unlock_irqrestore(&bank->slock, flags); 402 403 if (type & IRQ_TYPE_EDGE_BOTH) 404 irq_set_handler_locked(d, handle_edge_irq); 405 else 406 irq_set_handler_locked(d, handle_level_irq); 407 408 raw_spin_lock_irqsave(&bank->slock, flags); 409 410 level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type); 411 polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity); 412 413 switch (type) { 414 case IRQ_TYPE_EDGE_BOTH: 415 if (bank->gpio_type == GPIO_TYPE_V2) { 416 bank->toggle_edge_mode &= ~mask; 417 rockchip_gpio_writel_bit(bank, d->hwirq, 1, 418 bank->gpio_regs->int_bothedge); 419 goto out; 420 } else { 421 bank->toggle_edge_mode |= mask; 422 level |= mask; 423 424 /* 425 * Determine gpio state. If 1 next interrupt should be 426 * falling otherwise rising. 427 */ 428 data = readl(bank->reg_base + bank->gpio_regs->ext_port); 429 if (data & mask) 430 polarity &= ~mask; 431 else 432 polarity |= mask; 433 } 434 break; 435 case IRQ_TYPE_EDGE_RISING: 436 bank->toggle_edge_mode &= ~mask; 437 level |= mask; 438 polarity |= mask; 439 break; 440 case IRQ_TYPE_EDGE_FALLING: 441 bank->toggle_edge_mode &= ~mask; 442 level |= mask; 443 polarity &= ~mask; 444 break; 445 case IRQ_TYPE_LEVEL_HIGH: 446 bank->toggle_edge_mode &= ~mask; 447 level &= ~mask; 448 polarity |= mask; 449 break; 450 case IRQ_TYPE_LEVEL_LOW: 451 bank->toggle_edge_mode &= ~mask; 452 level &= ~mask; 453 polarity &= ~mask; 454 break; 455 default: 456 ret = -EINVAL; 457 goto out; 458 } 459 460 rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type); 461 rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity); 462 out: 463 raw_spin_unlock_irqrestore(&bank->slock, flags); 464 465 return ret; 466 } 467 468 static int rockchip_irq_reqres(struct irq_data *d) 469 { 470 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 471 struct rockchip_pin_bank *bank = gc->private; 472 473 return gpiochip_reqres_irq(&bank->gpio_chip, d->hwirq); 474 } 475 476 static void rockchip_irq_relres(struct irq_data *d) 477 { 478 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 479 struct rockchip_pin_bank *bank = gc->private; 480 481 gpiochip_relres_irq(&bank->gpio_chip, d->hwirq); 482 } 483 484 static void rockchip_irq_suspend(struct irq_data *d) 485 { 486 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 487 struct rockchip_pin_bank *bank = gc->private; 488 489 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask); 490 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask); 491 } 492 493 static void rockchip_irq_resume(struct irq_data *d) 494 { 495 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 496 struct rockchip_pin_bank *bank = gc->private; 497 498 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask); 499 } 500 501 static void rockchip_irq_enable(struct irq_data *d) 502 { 503 irq_gc_mask_clr_bit(d); 504 } 505 506 static void rockchip_irq_disable(struct irq_data *d) 507 { 508 irq_gc_mask_set_bit(d); 509 } 510 511 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) 512 { 513 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 514 struct irq_chip_generic *gc; 515 int ret; 516 517 bank->domain = irq_domain_add_linear(bank->of_node, 32, 518 &irq_generic_chip_ops, NULL); 519 if (!bank->domain) { 520 dev_warn(bank->dev, "could not init irq domain for bank %s\n", 521 bank->name); 522 return -EINVAL; 523 } 524 525 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 526 "rockchip_gpio_irq", 527 handle_level_irq, 528 clr, 0, 0); 529 if (ret) { 530 dev_err(bank->dev, "could not alloc generic chips for bank %s\n", 531 bank->name); 532 irq_domain_remove(bank->domain); 533 return -EINVAL; 534 } 535 536 gc = irq_get_domain_generic_chip(bank->domain, 0); 537 if (bank->gpio_type == GPIO_TYPE_V2) { 538 gc->reg_writel = gpio_writel_v2; 539 gc->reg_readl = gpio_readl_v2; 540 } 541 542 gc->reg_base = bank->reg_base; 543 gc->private = bank; 544 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask; 545 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi; 546 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 547 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 548 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 549 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; 550 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; 551 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 552 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 553 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 554 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 555 gc->chip_types[0].chip.irq_request_resources = rockchip_irq_reqres; 556 gc->chip_types[0].chip.irq_release_resources = rockchip_irq_relres; 557 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 558 559 /* 560 * Linux assumes that all interrupts start out disabled/masked. 561 * Our driver only uses the concept of masked and always keeps 562 * things enabled, so for us that's all masked and all enabled. 563 */ 564 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask); 565 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi); 566 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en); 567 gc->mask_cache = 0xffffffff; 568 569 irq_set_chained_handler_and_data(bank->irq, 570 rockchip_irq_demux, bank); 571 572 return 0; 573 } 574 575 static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank) 576 { 577 struct gpio_chip *gc; 578 int ret; 579 580 bank->gpio_chip = rockchip_gpiolib_chip; 581 582 gc = &bank->gpio_chip; 583 gc->base = bank->pin_base; 584 gc->ngpio = bank->nr_pins; 585 gc->label = bank->name; 586 gc->parent = bank->dev; 587 588 ret = gpiochip_add_data(gc, bank); 589 if (ret) { 590 dev_err(bank->dev, "failed to add gpiochip %s, %d\n", 591 gc->label, ret); 592 return ret; 593 } 594 595 /* 596 * For DeviceTree-supported systems, the gpio core checks the 597 * pinctrl's device node for the "gpio-ranges" property. 598 * If it is present, it takes care of adding the pin ranges 599 * for the driver. In this case the driver can skip ahead. 600 * 601 * In order to remain compatible with older, existing DeviceTree 602 * files which don't set the "gpio-ranges" property or systems that 603 * utilize ACPI the driver has to call gpiochip_add_pin_range(). 604 */ 605 if (!of_property_read_bool(bank->of_node, "gpio-ranges")) { 606 struct device_node *pctlnp = of_get_parent(bank->of_node); 607 struct pinctrl_dev *pctldev = NULL; 608 609 if (!pctlnp) 610 return -ENODATA; 611 612 pctldev = of_pinctrl_get(pctlnp); 613 if (!pctldev) 614 return -ENODEV; 615 616 ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0, 617 gc->base, gc->ngpio); 618 if (ret) { 619 dev_err(bank->dev, "Failed to add pin range\n"); 620 goto fail; 621 } 622 } 623 624 ret = rockchip_interrupts_register(bank); 625 if (ret) { 626 dev_err(bank->dev, "failed to register interrupt, %d\n", ret); 627 goto fail; 628 } 629 630 return 0; 631 632 fail: 633 gpiochip_remove(&bank->gpio_chip); 634 635 return ret; 636 } 637 638 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank) 639 { 640 struct resource res; 641 int id = 0; 642 643 if (of_address_to_resource(bank->of_node, 0, &res)) { 644 dev_err(bank->dev, "cannot find IO resource for bank\n"); 645 return -ENOENT; 646 } 647 648 bank->reg_base = devm_ioremap_resource(bank->dev, &res); 649 if (IS_ERR(bank->reg_base)) 650 return PTR_ERR(bank->reg_base); 651 652 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 653 if (!bank->irq) 654 return -EINVAL; 655 656 bank->clk = of_clk_get(bank->of_node, 0); 657 if (IS_ERR(bank->clk)) 658 return PTR_ERR(bank->clk); 659 660 clk_prepare_enable(bank->clk); 661 id = readl(bank->reg_base + gpio_regs_v2.version_id); 662 663 /* If not gpio v2, that is default to v1. */ 664 if (id == GPIO_TYPE_V2) { 665 bank->gpio_regs = &gpio_regs_v2; 666 bank->gpio_type = GPIO_TYPE_V2; 667 bank->db_clk = of_clk_get(bank->of_node, 1); 668 if (IS_ERR(bank->db_clk)) { 669 dev_err(bank->dev, "cannot find debounce clk\n"); 670 clk_disable_unprepare(bank->clk); 671 return -EINVAL; 672 } 673 } else { 674 bank->gpio_regs = &gpio_regs_v1; 675 bank->gpio_type = GPIO_TYPE_V1; 676 } 677 678 return 0; 679 } 680 681 static struct rockchip_pin_bank * 682 rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id) 683 { 684 struct rockchip_pinctrl *info; 685 struct rockchip_pin_bank *bank; 686 int i, found = 0; 687 688 info = pinctrl_dev_get_drvdata(pctldev); 689 bank = info->ctrl->pin_banks; 690 for (i = 0; i < info->ctrl->nr_banks; i++, bank++) { 691 if (bank->bank_num == id) { 692 found = 1; 693 break; 694 } 695 } 696 697 return found ? bank : NULL; 698 } 699 700 static int rockchip_gpio_probe(struct platform_device *pdev) 701 { 702 struct device *dev = &pdev->dev; 703 struct device_node *np = dev->of_node; 704 struct device_node *pctlnp = of_get_parent(np); 705 struct pinctrl_dev *pctldev = NULL; 706 struct rockchip_pin_bank *bank = NULL; 707 struct rockchip_pin_output_deferred *cfg; 708 static int gpio; 709 int id, ret; 710 711 if (!np || !pctlnp) 712 return -ENODEV; 713 714 pctldev = of_pinctrl_get(pctlnp); 715 if (!pctldev) 716 return -EPROBE_DEFER; 717 718 id = of_alias_get_id(np, "gpio"); 719 if (id < 0) 720 id = gpio++; 721 722 bank = rockchip_gpio_find_bank(pctldev, id); 723 if (!bank) 724 return -EINVAL; 725 726 bank->dev = dev; 727 bank->of_node = np; 728 729 raw_spin_lock_init(&bank->slock); 730 731 ret = rockchip_get_bank_data(bank); 732 if (ret) 733 return ret; 734 735 /* 736 * Prevent clashes with a deferred output setting 737 * being added right at this moment. 738 */ 739 mutex_lock(&bank->deferred_lock); 740 741 ret = rockchip_gpiolib_register(bank); 742 if (ret) { 743 clk_disable_unprepare(bank->clk); 744 mutex_unlock(&bank->deferred_lock); 745 return ret; 746 } 747 748 while (!list_empty(&bank->deferred_output)) { 749 cfg = list_first_entry(&bank->deferred_output, 750 struct rockchip_pin_output_deferred, head); 751 list_del(&cfg->head); 752 753 ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg); 754 if (ret) 755 dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin, cfg->arg); 756 757 kfree(cfg); 758 } 759 760 mutex_unlock(&bank->deferred_lock); 761 762 platform_set_drvdata(pdev, bank); 763 dev_info(dev, "probed %pOF\n", np); 764 765 return 0; 766 } 767 768 static int rockchip_gpio_remove(struct platform_device *pdev) 769 { 770 struct rockchip_pin_bank *bank = platform_get_drvdata(pdev); 771 772 clk_disable_unprepare(bank->clk); 773 gpiochip_remove(&bank->gpio_chip); 774 775 return 0; 776 } 777 778 static const struct of_device_id rockchip_gpio_match[] = { 779 { .compatible = "rockchip,gpio-bank", }, 780 { .compatible = "rockchip,rk3188-gpio-bank0" }, 781 { }, 782 }; 783 784 static struct platform_driver rockchip_gpio_driver = { 785 .probe = rockchip_gpio_probe, 786 .remove = rockchip_gpio_remove, 787 .driver = { 788 .name = "rockchip-gpio", 789 .of_match_table = rockchip_gpio_match, 790 }, 791 }; 792 793 static int __init rockchip_gpio_init(void) 794 { 795 return platform_driver_register(&rockchip_gpio_driver); 796 } 797 postcore_initcall(rockchip_gpio_init); 798 799 static void __exit rockchip_gpio_exit(void) 800 { 801 platform_driver_unregister(&rockchip_gpio_driver); 802 } 803 module_exit(rockchip_gpio_exit); 804 805 MODULE_DESCRIPTION("Rockchip gpio driver"); 806 MODULE_ALIAS("platform:rockchip-gpio"); 807 MODULE_LICENSE("GPL v2"); 808 MODULE_DEVICE_TABLE(of, rockchip_gpio_match); 809