1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 * 6 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_device.h> 21 #include <linux/of_irq.h> 22 #include <linux/pinctrl/pinconf-generic.h> 23 #include <linux/regmap.h> 24 25 #include "../pinctrl/core.h" 26 #include "../pinctrl/pinctrl-rockchip.h" 27 28 #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */ 29 #define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */ 30 #define GPIO_TYPE_V2_1 (0x0101157C) /* GPIO Version ID 0x0101157C */ 31 32 static const struct rockchip_gpio_regs gpio_regs_v1 = { 33 .port_dr = 0x00, 34 .port_ddr = 0x04, 35 .int_en = 0x30, 36 .int_mask = 0x34, 37 .int_type = 0x38, 38 .int_polarity = 0x3c, 39 .int_status = 0x40, 40 .int_rawstatus = 0x44, 41 .debounce = 0x48, 42 .port_eoi = 0x4c, 43 .ext_port = 0x50, 44 }; 45 46 static const struct rockchip_gpio_regs gpio_regs_v2 = { 47 .port_dr = 0x00, 48 .port_ddr = 0x08, 49 .int_en = 0x10, 50 .int_mask = 0x18, 51 .int_type = 0x20, 52 .int_polarity = 0x28, 53 .int_bothedge = 0x30, 54 .int_status = 0x50, 55 .int_rawstatus = 0x58, 56 .debounce = 0x38, 57 .dbclk_div_en = 0x40, 58 .dbclk_div_con = 0x48, 59 .port_eoi = 0x60, 60 .ext_port = 0x70, 61 .version_id = 0x78, 62 }; 63 64 static inline void gpio_writel_v2(u32 val, void __iomem *reg) 65 { 66 writel((val & 0xffff) | 0xffff0000, reg); 67 writel((val >> 16) | 0xffff0000, reg + 0x4); 68 } 69 70 static inline u32 gpio_readl_v2(void __iomem *reg) 71 { 72 return readl(reg + 0x4) << 16 | readl(reg); 73 } 74 75 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, 76 u32 value, unsigned int offset) 77 { 78 void __iomem *reg = bank->reg_base + offset; 79 80 if (bank->gpio_type == GPIO_TYPE_V2) 81 gpio_writel_v2(value, reg); 82 else 83 writel(value, reg); 84 } 85 86 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, 87 unsigned int offset) 88 { 89 void __iomem *reg = bank->reg_base + offset; 90 u32 value; 91 92 if (bank->gpio_type == GPIO_TYPE_V2) 93 value = gpio_readl_v2(reg); 94 else 95 value = readl(reg); 96 97 return value; 98 } 99 100 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, 101 u32 bit, u32 value, 102 unsigned int offset) 103 { 104 void __iomem *reg = bank->reg_base + offset; 105 u32 data; 106 107 if (bank->gpio_type == GPIO_TYPE_V2) { 108 if (value) 109 data = BIT(bit % 16) | BIT(bit % 16 + 16); 110 else 111 data = BIT(bit % 16 + 16); 112 writel(data, bit >= 16 ? reg + 0x4 : reg); 113 } else { 114 data = readl(reg); 115 data &= ~BIT(bit); 116 if (value) 117 data |= BIT(bit); 118 writel(data, reg); 119 } 120 } 121 122 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, 123 u32 bit, unsigned int offset) 124 { 125 void __iomem *reg = bank->reg_base + offset; 126 u32 data; 127 128 if (bank->gpio_type == GPIO_TYPE_V2) { 129 data = readl(bit >= 16 ? reg + 0x4 : reg); 130 data >>= bit % 16; 131 } else { 132 data = readl(reg); 133 data >>= bit; 134 } 135 136 return data & (0x1); 137 } 138 139 static int rockchip_gpio_get_direction(struct gpio_chip *chip, 140 unsigned int offset) 141 { 142 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 143 u32 data; 144 145 data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr); 146 if (data) 147 return GPIO_LINE_DIRECTION_OUT; 148 149 return GPIO_LINE_DIRECTION_IN; 150 } 151 152 static int rockchip_gpio_set_direction(struct gpio_chip *chip, 153 unsigned int offset, bool input) 154 { 155 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 156 unsigned long flags; 157 u32 data = input ? 0 : 1; 158 159 raw_spin_lock_irqsave(&bank->slock, flags); 160 rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr); 161 raw_spin_unlock_irqrestore(&bank->slock, flags); 162 163 return 0; 164 } 165 166 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset, 167 int value) 168 { 169 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 170 unsigned long flags; 171 172 raw_spin_lock_irqsave(&bank->slock, flags); 173 rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr); 174 raw_spin_unlock_irqrestore(&bank->slock, flags); 175 } 176 177 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset) 178 { 179 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 180 u32 data; 181 182 data = readl(bank->reg_base + bank->gpio_regs->ext_port); 183 data >>= offset; 184 data &= 1; 185 186 return data; 187 } 188 189 static int rockchip_gpio_set_debounce(struct gpio_chip *gc, 190 unsigned int offset, 191 unsigned int debounce) 192 { 193 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 194 const struct rockchip_gpio_regs *reg = bank->gpio_regs; 195 unsigned long flags, div_reg, freq, max_debounce; 196 bool div_debounce_support; 197 unsigned int cur_div_reg; 198 u64 div; 199 200 if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) { 201 div_debounce_support = true; 202 freq = clk_get_rate(bank->db_clk); 203 max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq; 204 if (debounce > max_debounce) 205 return -EINVAL; 206 207 div = debounce * freq; 208 div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1; 209 } else { 210 div_debounce_support = false; 211 } 212 213 raw_spin_lock_irqsave(&bank->slock, flags); 214 215 /* Only the v1 needs to configure div_en and div_con for dbclk */ 216 if (debounce) { 217 if (div_debounce_support) { 218 /* Configure the max debounce from consumers */ 219 cur_div_reg = readl(bank->reg_base + 220 reg->dbclk_div_con); 221 if (cur_div_reg < div_reg) 222 writel(div_reg, bank->reg_base + 223 reg->dbclk_div_con); 224 rockchip_gpio_writel_bit(bank, offset, 1, 225 reg->dbclk_div_en); 226 } 227 228 rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce); 229 } else { 230 if (div_debounce_support) 231 rockchip_gpio_writel_bit(bank, offset, 0, 232 reg->dbclk_div_en); 233 234 rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce); 235 } 236 237 raw_spin_unlock_irqrestore(&bank->slock, flags); 238 239 /* Enable or disable dbclk at last */ 240 if (div_debounce_support) { 241 if (debounce) 242 clk_prepare_enable(bank->db_clk); 243 else 244 clk_disable_unprepare(bank->db_clk); 245 } 246 247 return 0; 248 } 249 250 static int rockchip_gpio_direction_input(struct gpio_chip *gc, 251 unsigned int offset) 252 { 253 return rockchip_gpio_set_direction(gc, offset, true); 254 } 255 256 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 257 unsigned int offset, int value) 258 { 259 rockchip_gpio_set(gc, offset, value); 260 261 return rockchip_gpio_set_direction(gc, offset, false); 262 } 263 264 /* 265 * gpiolib set_config callback function. The setting of the pin 266 * mux function as 'gpio output' will be handled by the pinctrl subsystem 267 * interface. 268 */ 269 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 270 unsigned long config) 271 { 272 enum pin_config_param param = pinconf_to_config_param(config); 273 274 switch (param) { 275 case PIN_CONFIG_INPUT_DEBOUNCE: 276 rockchip_gpio_set_debounce(gc, offset, true); 277 /* 278 * Rockchip's gpio could only support up to one period 279 * of the debounce clock(pclk), which is far away from 280 * satisftying the requirement, as pclk is usually near 281 * 100MHz shared by all peripherals. So the fact is it 282 * has crippled debounce capability could only be useful 283 * to prevent any spurious glitches from waking up the system 284 * if the gpio is conguired as wakeup interrupt source. Let's 285 * still return -ENOTSUPP as before, to make sure the caller 286 * of gpiod_set_debounce won't change its behaviour. 287 */ 288 return -ENOTSUPP; 289 default: 290 return -ENOTSUPP; 291 } 292 } 293 294 /* 295 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 296 * and a virtual IRQ, if not already present. 297 */ 298 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) 299 { 300 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 301 unsigned int virq; 302 303 if (!bank->domain) 304 return -ENXIO; 305 306 virq = irq_create_mapping(bank->domain, offset); 307 308 return (virq) ? : -ENXIO; 309 } 310 311 static const struct gpio_chip rockchip_gpiolib_chip = { 312 .request = gpiochip_generic_request, 313 .free = gpiochip_generic_free, 314 .set = rockchip_gpio_set, 315 .get = rockchip_gpio_get, 316 .get_direction = rockchip_gpio_get_direction, 317 .direction_input = rockchip_gpio_direction_input, 318 .direction_output = rockchip_gpio_direction_output, 319 .set_config = rockchip_gpio_set_config, 320 .to_irq = rockchip_gpio_to_irq, 321 .owner = THIS_MODULE, 322 }; 323 324 static void rockchip_irq_demux(struct irq_desc *desc) 325 { 326 struct irq_chip *chip = irq_desc_get_chip(desc); 327 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 328 u32 pend; 329 330 dev_dbg(bank->dev, "got irq for bank %s\n", bank->name); 331 332 chained_irq_enter(chip, desc); 333 334 pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status); 335 336 while (pend) { 337 unsigned int irq, virq; 338 339 irq = __ffs(pend); 340 pend &= ~BIT(irq); 341 virq = irq_find_mapping(bank->domain, irq); 342 343 if (!virq) { 344 dev_err(bank->dev, "unmapped irq %d\n", irq); 345 continue; 346 } 347 348 dev_dbg(bank->dev, "handling irq %d\n", irq); 349 350 /* 351 * Triggering IRQ on both rising and falling edge 352 * needs manual intervention. 353 */ 354 if (bank->toggle_edge_mode & BIT(irq)) { 355 u32 data, data_old, polarity; 356 unsigned long flags; 357 358 data = readl_relaxed(bank->reg_base + 359 bank->gpio_regs->ext_port); 360 do { 361 raw_spin_lock_irqsave(&bank->slock, flags); 362 363 polarity = readl_relaxed(bank->reg_base + 364 bank->gpio_regs->int_polarity); 365 if (data & BIT(irq)) 366 polarity &= ~BIT(irq); 367 else 368 polarity |= BIT(irq); 369 writel(polarity, 370 bank->reg_base + 371 bank->gpio_regs->int_polarity); 372 373 raw_spin_unlock_irqrestore(&bank->slock, flags); 374 375 data_old = data; 376 data = readl_relaxed(bank->reg_base + 377 bank->gpio_regs->ext_port); 378 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 379 } 380 381 generic_handle_irq(virq); 382 } 383 384 chained_irq_exit(chip, desc); 385 } 386 387 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 388 { 389 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 390 struct rockchip_pin_bank *bank = gc->private; 391 u32 mask = BIT(d->hwirq); 392 u32 polarity; 393 u32 level; 394 u32 data; 395 unsigned long flags; 396 int ret = 0; 397 398 raw_spin_lock_irqsave(&bank->slock, flags); 399 400 rockchip_gpio_writel_bit(bank, d->hwirq, 0, 401 bank->gpio_regs->port_ddr); 402 403 raw_spin_unlock_irqrestore(&bank->slock, flags); 404 405 if (type & IRQ_TYPE_EDGE_BOTH) 406 irq_set_handler_locked(d, handle_edge_irq); 407 else 408 irq_set_handler_locked(d, handle_level_irq); 409 410 raw_spin_lock_irqsave(&bank->slock, flags); 411 412 level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type); 413 polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity); 414 415 if (type == IRQ_TYPE_EDGE_BOTH) { 416 if (bank->gpio_type == GPIO_TYPE_V2) { 417 rockchip_gpio_writel_bit(bank, d->hwirq, 1, 418 bank->gpio_regs->int_bothedge); 419 goto out; 420 } else { 421 bank->toggle_edge_mode |= mask; 422 level |= mask; 423 424 /* 425 * Determine gpio state. If 1 next interrupt should be 426 * falling otherwise rising. 427 */ 428 data = readl(bank->reg_base + bank->gpio_regs->ext_port); 429 if (data & mask) 430 polarity &= ~mask; 431 else 432 polarity |= mask; 433 } 434 } else { 435 if (bank->gpio_type == GPIO_TYPE_V2) { 436 rockchip_gpio_writel_bit(bank, d->hwirq, 0, 437 bank->gpio_regs->int_bothedge); 438 } else { 439 bank->toggle_edge_mode &= ~mask; 440 } 441 switch (type) { 442 case IRQ_TYPE_EDGE_RISING: 443 level |= mask; 444 polarity |= mask; 445 break; 446 case IRQ_TYPE_EDGE_FALLING: 447 level |= mask; 448 polarity &= ~mask; 449 break; 450 case IRQ_TYPE_LEVEL_HIGH: 451 level &= ~mask; 452 polarity |= mask; 453 break; 454 case IRQ_TYPE_LEVEL_LOW: 455 level &= ~mask; 456 polarity &= ~mask; 457 break; 458 default: 459 ret = -EINVAL; 460 goto out; 461 } 462 } 463 464 rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type); 465 rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity); 466 out: 467 raw_spin_unlock_irqrestore(&bank->slock, flags); 468 469 return ret; 470 } 471 472 static int rockchip_irq_reqres(struct irq_data *d) 473 { 474 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 475 struct rockchip_pin_bank *bank = gc->private; 476 477 return gpiochip_reqres_irq(&bank->gpio_chip, d->hwirq); 478 } 479 480 static void rockchip_irq_relres(struct irq_data *d) 481 { 482 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 483 struct rockchip_pin_bank *bank = gc->private; 484 485 gpiochip_relres_irq(&bank->gpio_chip, d->hwirq); 486 } 487 488 static void rockchip_irq_suspend(struct irq_data *d) 489 { 490 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 491 struct rockchip_pin_bank *bank = gc->private; 492 493 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask); 494 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask); 495 } 496 497 static void rockchip_irq_resume(struct irq_data *d) 498 { 499 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 500 struct rockchip_pin_bank *bank = gc->private; 501 502 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask); 503 } 504 505 static void rockchip_irq_enable(struct irq_data *d) 506 { 507 irq_gc_mask_clr_bit(d); 508 } 509 510 static void rockchip_irq_disable(struct irq_data *d) 511 { 512 irq_gc_mask_set_bit(d); 513 } 514 515 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) 516 { 517 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 518 struct irq_chip_generic *gc; 519 int ret; 520 521 bank->domain = irq_domain_add_linear(bank->of_node, 32, 522 &irq_generic_chip_ops, NULL); 523 if (!bank->domain) { 524 dev_warn(bank->dev, "could not init irq domain for bank %s\n", 525 bank->name); 526 return -EINVAL; 527 } 528 529 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 530 "rockchip_gpio_irq", 531 handle_level_irq, 532 clr, 0, 0); 533 if (ret) { 534 dev_err(bank->dev, "could not alloc generic chips for bank %s\n", 535 bank->name); 536 irq_domain_remove(bank->domain); 537 return -EINVAL; 538 } 539 540 gc = irq_get_domain_generic_chip(bank->domain, 0); 541 if (bank->gpio_type == GPIO_TYPE_V2) { 542 gc->reg_writel = gpio_writel_v2; 543 gc->reg_readl = gpio_readl_v2; 544 } 545 546 gc->reg_base = bank->reg_base; 547 gc->private = bank; 548 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask; 549 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi; 550 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 551 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 552 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 553 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; 554 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; 555 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 556 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 557 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 558 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 559 gc->chip_types[0].chip.irq_request_resources = rockchip_irq_reqres; 560 gc->chip_types[0].chip.irq_release_resources = rockchip_irq_relres; 561 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 562 563 /* 564 * Linux assumes that all interrupts start out disabled/masked. 565 * Our driver only uses the concept of masked and always keeps 566 * things enabled, so for us that's all masked and all enabled. 567 */ 568 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask); 569 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi); 570 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en); 571 gc->mask_cache = 0xffffffff; 572 573 irq_set_chained_handler_and_data(bank->irq, 574 rockchip_irq_demux, bank); 575 576 return 0; 577 } 578 579 static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank) 580 { 581 struct gpio_chip *gc; 582 int ret; 583 584 bank->gpio_chip = rockchip_gpiolib_chip; 585 586 gc = &bank->gpio_chip; 587 gc->base = bank->pin_base; 588 gc->ngpio = bank->nr_pins; 589 gc->label = bank->name; 590 gc->parent = bank->dev; 591 592 ret = gpiochip_add_data(gc, bank); 593 if (ret) { 594 dev_err(bank->dev, "failed to add gpiochip %s, %d\n", 595 gc->label, ret); 596 return ret; 597 } 598 599 /* 600 * For DeviceTree-supported systems, the gpio core checks the 601 * pinctrl's device node for the "gpio-ranges" property. 602 * If it is present, it takes care of adding the pin ranges 603 * for the driver. In this case the driver can skip ahead. 604 * 605 * In order to remain compatible with older, existing DeviceTree 606 * files which don't set the "gpio-ranges" property or systems that 607 * utilize ACPI the driver has to call gpiochip_add_pin_range(). 608 */ 609 if (!of_property_read_bool(bank->of_node, "gpio-ranges")) { 610 struct device_node *pctlnp = of_get_parent(bank->of_node); 611 struct pinctrl_dev *pctldev = NULL; 612 613 if (!pctlnp) 614 return -ENODATA; 615 616 pctldev = of_pinctrl_get(pctlnp); 617 if (!pctldev) 618 return -ENODEV; 619 620 ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0, 621 gc->base, gc->ngpio); 622 if (ret) { 623 dev_err(bank->dev, "Failed to add pin range\n"); 624 goto fail; 625 } 626 } 627 628 ret = rockchip_interrupts_register(bank); 629 if (ret) { 630 dev_err(bank->dev, "failed to register interrupt, %d\n", ret); 631 goto fail; 632 } 633 634 return 0; 635 636 fail: 637 gpiochip_remove(&bank->gpio_chip); 638 639 return ret; 640 } 641 642 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank) 643 { 644 struct resource res; 645 int id = 0; 646 647 if (of_address_to_resource(bank->of_node, 0, &res)) { 648 dev_err(bank->dev, "cannot find IO resource for bank\n"); 649 return -ENOENT; 650 } 651 652 bank->reg_base = devm_ioremap_resource(bank->dev, &res); 653 if (IS_ERR(bank->reg_base)) 654 return PTR_ERR(bank->reg_base); 655 656 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 657 if (!bank->irq) 658 return -EINVAL; 659 660 bank->clk = of_clk_get(bank->of_node, 0); 661 if (IS_ERR(bank->clk)) 662 return PTR_ERR(bank->clk); 663 664 clk_prepare_enable(bank->clk); 665 id = readl(bank->reg_base + gpio_regs_v2.version_id); 666 667 /* If not gpio v2, that is default to v1. */ 668 if (id == GPIO_TYPE_V2 || id == GPIO_TYPE_V2_1) { 669 bank->gpio_regs = &gpio_regs_v2; 670 bank->gpio_type = GPIO_TYPE_V2; 671 bank->db_clk = of_clk_get(bank->of_node, 1); 672 if (IS_ERR(bank->db_clk)) { 673 dev_err(bank->dev, "cannot find debounce clk\n"); 674 clk_disable_unprepare(bank->clk); 675 return -EINVAL; 676 } 677 } else { 678 bank->gpio_regs = &gpio_regs_v1; 679 bank->gpio_type = GPIO_TYPE_V1; 680 } 681 682 return 0; 683 } 684 685 static struct rockchip_pin_bank * 686 rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id) 687 { 688 struct rockchip_pinctrl *info; 689 struct rockchip_pin_bank *bank; 690 int i, found = 0; 691 692 info = pinctrl_dev_get_drvdata(pctldev); 693 bank = info->ctrl->pin_banks; 694 for (i = 0; i < info->ctrl->nr_banks; i++, bank++) { 695 if (bank->bank_num == id) { 696 found = 1; 697 break; 698 } 699 } 700 701 return found ? bank : NULL; 702 } 703 704 static int rockchip_gpio_probe(struct platform_device *pdev) 705 { 706 struct device *dev = &pdev->dev; 707 struct device_node *np = dev->of_node; 708 struct device_node *pctlnp = of_get_parent(np); 709 struct pinctrl_dev *pctldev = NULL; 710 struct rockchip_pin_bank *bank = NULL; 711 struct rockchip_pin_deferred *cfg; 712 static int gpio; 713 int id, ret; 714 715 if (!np || !pctlnp) 716 return -ENODEV; 717 718 pctldev = of_pinctrl_get(pctlnp); 719 if (!pctldev) 720 return -EPROBE_DEFER; 721 722 id = of_alias_get_id(np, "gpio"); 723 if (id < 0) 724 id = gpio++; 725 726 bank = rockchip_gpio_find_bank(pctldev, id); 727 if (!bank) 728 return -EINVAL; 729 730 bank->dev = dev; 731 bank->of_node = np; 732 733 raw_spin_lock_init(&bank->slock); 734 735 ret = rockchip_get_bank_data(bank); 736 if (ret) 737 return ret; 738 739 /* 740 * Prevent clashes with a deferred output setting 741 * being added right at this moment. 742 */ 743 mutex_lock(&bank->deferred_lock); 744 745 ret = rockchip_gpiolib_register(bank); 746 if (ret) { 747 clk_disable_unprepare(bank->clk); 748 mutex_unlock(&bank->deferred_lock); 749 return ret; 750 } 751 752 while (!list_empty(&bank->deferred_pins)) { 753 cfg = list_first_entry(&bank->deferred_pins, 754 struct rockchip_pin_deferred, head); 755 list_del(&cfg->head); 756 757 switch (cfg->param) { 758 case PIN_CONFIG_OUTPUT: 759 ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg); 760 if (ret) 761 dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin, 762 cfg->arg); 763 break; 764 case PIN_CONFIG_INPUT_ENABLE: 765 ret = rockchip_gpio_direction_input(&bank->gpio_chip, cfg->pin); 766 if (ret) 767 dev_warn(dev, "setting input pin %u failed\n", cfg->pin); 768 break; 769 default: 770 dev_warn(dev, "unknown deferred config param %d\n", cfg->param); 771 break; 772 } 773 kfree(cfg); 774 } 775 776 mutex_unlock(&bank->deferred_lock); 777 778 platform_set_drvdata(pdev, bank); 779 dev_info(dev, "probed %pOF\n", np); 780 781 return 0; 782 } 783 784 static int rockchip_gpio_remove(struct platform_device *pdev) 785 { 786 struct rockchip_pin_bank *bank = platform_get_drvdata(pdev); 787 788 clk_disable_unprepare(bank->clk); 789 gpiochip_remove(&bank->gpio_chip); 790 791 return 0; 792 } 793 794 static const struct of_device_id rockchip_gpio_match[] = { 795 { .compatible = "rockchip,gpio-bank", }, 796 { .compatible = "rockchip,rk3188-gpio-bank0" }, 797 { }, 798 }; 799 800 static struct platform_driver rockchip_gpio_driver = { 801 .probe = rockchip_gpio_probe, 802 .remove = rockchip_gpio_remove, 803 .driver = { 804 .name = "rockchip-gpio", 805 .of_match_table = rockchip_gpio_match, 806 }, 807 }; 808 809 static int __init rockchip_gpio_init(void) 810 { 811 return platform_driver_register(&rockchip_gpio_driver); 812 } 813 postcore_initcall(rockchip_gpio_init); 814 815 static void __exit rockchip_gpio_exit(void) 816 { 817 platform_driver_unregister(&rockchip_gpio_driver); 818 } 819 module_exit(rockchip_gpio_exit); 820 821 MODULE_DESCRIPTION("Rockchip gpio driver"); 822 MODULE_ALIAS("platform:rockchip-gpio"); 823 MODULE_LICENSE("GPL v2"); 824 MODULE_DEVICE_TABLE(of, rockchip_gpio_match); 825