1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 * 6 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_device.h> 21 #include <linux/of_irq.h> 22 #include <linux/pinctrl/pinconf-generic.h> 23 #include <linux/regmap.h> 24 25 #include "../pinctrl/core.h" 26 #include "../pinctrl/pinctrl-rockchip.h" 27 28 #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */ 29 #define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */ 30 31 static const struct rockchip_gpio_regs gpio_regs_v1 = { 32 .port_dr = 0x00, 33 .port_ddr = 0x04, 34 .int_en = 0x30, 35 .int_mask = 0x34, 36 .int_type = 0x38, 37 .int_polarity = 0x3c, 38 .int_status = 0x40, 39 .int_rawstatus = 0x44, 40 .debounce = 0x48, 41 .port_eoi = 0x4c, 42 .ext_port = 0x50, 43 }; 44 45 static const struct rockchip_gpio_regs gpio_regs_v2 = { 46 .port_dr = 0x00, 47 .port_ddr = 0x08, 48 .int_en = 0x10, 49 .int_mask = 0x18, 50 .int_type = 0x20, 51 .int_polarity = 0x28, 52 .int_bothedge = 0x30, 53 .int_status = 0x50, 54 .int_rawstatus = 0x58, 55 .debounce = 0x38, 56 .dbclk_div_en = 0x40, 57 .dbclk_div_con = 0x48, 58 .port_eoi = 0x60, 59 .ext_port = 0x70, 60 .version_id = 0x78, 61 }; 62 63 static inline void gpio_writel_v2(u32 val, void __iomem *reg) 64 { 65 writel((val & 0xffff) | 0xffff0000, reg); 66 writel((val >> 16) | 0xffff0000, reg + 0x4); 67 } 68 69 static inline u32 gpio_readl_v2(void __iomem *reg) 70 { 71 return readl(reg + 0x4) << 16 | readl(reg); 72 } 73 74 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, 75 u32 value, unsigned int offset) 76 { 77 void __iomem *reg = bank->reg_base + offset; 78 79 if (bank->gpio_type == GPIO_TYPE_V2) 80 gpio_writel_v2(value, reg); 81 else 82 writel(value, reg); 83 } 84 85 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, 86 unsigned int offset) 87 { 88 void __iomem *reg = bank->reg_base + offset; 89 u32 value; 90 91 if (bank->gpio_type == GPIO_TYPE_V2) 92 value = gpio_readl_v2(reg); 93 else 94 value = readl(reg); 95 96 return value; 97 } 98 99 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, 100 u32 bit, u32 value, 101 unsigned int offset) 102 { 103 void __iomem *reg = bank->reg_base + offset; 104 u32 data; 105 106 if (bank->gpio_type == GPIO_TYPE_V2) { 107 if (value) 108 data = BIT(bit % 16) | BIT(bit % 16 + 16); 109 else 110 data = BIT(bit % 16 + 16); 111 writel(data, bit >= 16 ? reg + 0x4 : reg); 112 } else { 113 data = readl(reg); 114 data &= ~BIT(bit); 115 if (value) 116 data |= BIT(bit); 117 writel(data, reg); 118 } 119 } 120 121 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, 122 u32 bit, unsigned int offset) 123 { 124 void __iomem *reg = bank->reg_base + offset; 125 u32 data; 126 127 if (bank->gpio_type == GPIO_TYPE_V2) { 128 data = readl(bit >= 16 ? reg + 0x4 : reg); 129 data >>= bit % 16; 130 } else { 131 data = readl(reg); 132 data >>= bit; 133 } 134 135 return data & (0x1); 136 } 137 138 static int rockchip_gpio_get_direction(struct gpio_chip *chip, 139 unsigned int offset) 140 { 141 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 142 u32 data; 143 144 data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr); 145 if (data) 146 return GPIO_LINE_DIRECTION_OUT; 147 148 return GPIO_LINE_DIRECTION_IN; 149 } 150 151 static int rockchip_gpio_set_direction(struct gpio_chip *chip, 152 unsigned int offset, bool input) 153 { 154 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 155 unsigned long flags; 156 u32 data = input ? 0 : 1; 157 158 raw_spin_lock_irqsave(&bank->slock, flags); 159 rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr); 160 raw_spin_unlock_irqrestore(&bank->slock, flags); 161 162 return 0; 163 } 164 165 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset, 166 int value) 167 { 168 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 169 unsigned long flags; 170 171 raw_spin_lock_irqsave(&bank->slock, flags); 172 rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr); 173 raw_spin_unlock_irqrestore(&bank->slock, flags); 174 } 175 176 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset) 177 { 178 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 179 u32 data; 180 181 data = readl(bank->reg_base + bank->gpio_regs->ext_port); 182 data >>= offset; 183 data &= 1; 184 185 return data; 186 } 187 188 static int rockchip_gpio_set_debounce(struct gpio_chip *gc, 189 unsigned int offset, 190 unsigned int debounce) 191 { 192 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 193 const struct rockchip_gpio_regs *reg = bank->gpio_regs; 194 unsigned long flags, div_reg, freq, max_debounce; 195 bool div_debounce_support; 196 unsigned int cur_div_reg; 197 u64 div; 198 199 if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) { 200 div_debounce_support = true; 201 freq = clk_get_rate(bank->db_clk); 202 max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq; 203 if (debounce > max_debounce) 204 return -EINVAL; 205 206 div = debounce * freq; 207 div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1; 208 } else { 209 div_debounce_support = false; 210 } 211 212 raw_spin_lock_irqsave(&bank->slock, flags); 213 214 /* Only the v1 needs to configure div_en and div_con for dbclk */ 215 if (debounce) { 216 if (div_debounce_support) { 217 /* Configure the max debounce from consumers */ 218 cur_div_reg = readl(bank->reg_base + 219 reg->dbclk_div_con); 220 if (cur_div_reg < div_reg) 221 writel(div_reg, bank->reg_base + 222 reg->dbclk_div_con); 223 rockchip_gpio_writel_bit(bank, offset, 1, 224 reg->dbclk_div_en); 225 } 226 227 rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce); 228 } else { 229 if (div_debounce_support) 230 rockchip_gpio_writel_bit(bank, offset, 0, 231 reg->dbclk_div_en); 232 233 rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce); 234 } 235 236 raw_spin_unlock_irqrestore(&bank->slock, flags); 237 238 /* Enable or disable dbclk at last */ 239 if (div_debounce_support) { 240 if (debounce) 241 clk_prepare_enable(bank->db_clk); 242 else 243 clk_disable_unprepare(bank->db_clk); 244 } 245 246 return 0; 247 } 248 249 static int rockchip_gpio_direction_input(struct gpio_chip *gc, 250 unsigned int offset) 251 { 252 return rockchip_gpio_set_direction(gc, offset, true); 253 } 254 255 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 256 unsigned int offset, int value) 257 { 258 rockchip_gpio_set(gc, offset, value); 259 260 return rockchip_gpio_set_direction(gc, offset, false); 261 } 262 263 /* 264 * gpiolib set_config callback function. The setting of the pin 265 * mux function as 'gpio output' will be handled by the pinctrl subsystem 266 * interface. 267 */ 268 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 269 unsigned long config) 270 { 271 enum pin_config_param param = pinconf_to_config_param(config); 272 273 switch (param) { 274 case PIN_CONFIG_INPUT_DEBOUNCE: 275 rockchip_gpio_set_debounce(gc, offset, true); 276 /* 277 * Rockchip's gpio could only support up to one period 278 * of the debounce clock(pclk), which is far away from 279 * satisftying the requirement, as pclk is usually near 280 * 100MHz shared by all peripherals. So the fact is it 281 * has crippled debounce capability could only be useful 282 * to prevent any spurious glitches from waking up the system 283 * if the gpio is conguired as wakeup interrupt source. Let's 284 * still return -ENOTSUPP as before, to make sure the caller 285 * of gpiod_set_debounce won't change its behaviour. 286 */ 287 return -ENOTSUPP; 288 default: 289 return -ENOTSUPP; 290 } 291 } 292 293 /* 294 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 295 * and a virtual IRQ, if not already present. 296 */ 297 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) 298 { 299 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 300 unsigned int virq; 301 302 if (!bank->domain) 303 return -ENXIO; 304 305 virq = irq_create_mapping(bank->domain, offset); 306 307 return (virq) ? : -ENXIO; 308 } 309 310 static const struct gpio_chip rockchip_gpiolib_chip = { 311 .request = gpiochip_generic_request, 312 .free = gpiochip_generic_free, 313 .set = rockchip_gpio_set, 314 .get = rockchip_gpio_get, 315 .get_direction = rockchip_gpio_get_direction, 316 .direction_input = rockchip_gpio_direction_input, 317 .direction_output = rockchip_gpio_direction_output, 318 .set_config = rockchip_gpio_set_config, 319 .to_irq = rockchip_gpio_to_irq, 320 .owner = THIS_MODULE, 321 }; 322 323 static void rockchip_irq_demux(struct irq_desc *desc) 324 { 325 struct irq_chip *chip = irq_desc_get_chip(desc); 326 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 327 u32 pend; 328 329 dev_dbg(bank->dev, "got irq for bank %s\n", bank->name); 330 331 chained_irq_enter(chip, desc); 332 333 pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status); 334 335 while (pend) { 336 unsigned int irq, virq; 337 338 irq = __ffs(pend); 339 pend &= ~BIT(irq); 340 virq = irq_find_mapping(bank->domain, irq); 341 342 if (!virq) { 343 dev_err(bank->dev, "unmapped irq %d\n", irq); 344 continue; 345 } 346 347 dev_dbg(bank->dev, "handling irq %d\n", irq); 348 349 /* 350 * Triggering IRQ on both rising and falling edge 351 * needs manual intervention. 352 */ 353 if (bank->toggle_edge_mode & BIT(irq)) { 354 u32 data, data_old, polarity; 355 unsigned long flags; 356 357 data = readl_relaxed(bank->reg_base + 358 bank->gpio_regs->ext_port); 359 do { 360 raw_spin_lock_irqsave(&bank->slock, flags); 361 362 polarity = readl_relaxed(bank->reg_base + 363 bank->gpio_regs->int_polarity); 364 if (data & BIT(irq)) 365 polarity &= ~BIT(irq); 366 else 367 polarity |= BIT(irq); 368 writel(polarity, 369 bank->reg_base + 370 bank->gpio_regs->int_polarity); 371 372 raw_spin_unlock_irqrestore(&bank->slock, flags); 373 374 data_old = data; 375 data = readl_relaxed(bank->reg_base + 376 bank->gpio_regs->ext_port); 377 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 378 } 379 380 generic_handle_irq(virq); 381 } 382 383 chained_irq_exit(chip, desc); 384 } 385 386 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 387 { 388 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 389 struct rockchip_pin_bank *bank = gc->private; 390 u32 mask = BIT(d->hwirq); 391 u32 polarity; 392 u32 level; 393 u32 data; 394 unsigned long flags; 395 int ret = 0; 396 397 raw_spin_lock_irqsave(&bank->slock, flags); 398 399 rockchip_gpio_writel_bit(bank, d->hwirq, 0, 400 bank->gpio_regs->port_ddr); 401 402 raw_spin_unlock_irqrestore(&bank->slock, flags); 403 404 if (type & IRQ_TYPE_EDGE_BOTH) 405 irq_set_handler_locked(d, handle_edge_irq); 406 else 407 irq_set_handler_locked(d, handle_level_irq); 408 409 raw_spin_lock_irqsave(&bank->slock, flags); 410 411 level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type); 412 polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity); 413 414 if (type == IRQ_TYPE_EDGE_BOTH) { 415 if (bank->gpio_type == GPIO_TYPE_V2) { 416 rockchip_gpio_writel_bit(bank, d->hwirq, 1, 417 bank->gpio_regs->int_bothedge); 418 goto out; 419 } else { 420 bank->toggle_edge_mode |= mask; 421 level |= mask; 422 423 /* 424 * Determine gpio state. If 1 next interrupt should be 425 * falling otherwise rising. 426 */ 427 data = readl(bank->reg_base + bank->gpio_regs->ext_port); 428 if (data & mask) 429 polarity &= ~mask; 430 else 431 polarity |= mask; 432 } 433 } else { 434 if (bank->gpio_type == GPIO_TYPE_V2) { 435 rockchip_gpio_writel_bit(bank, d->hwirq, 0, 436 bank->gpio_regs->int_bothedge); 437 } else { 438 bank->toggle_edge_mode &= ~mask; 439 } 440 switch (type) { 441 case IRQ_TYPE_EDGE_RISING: 442 level |= mask; 443 polarity |= mask; 444 break; 445 case IRQ_TYPE_EDGE_FALLING: 446 level |= mask; 447 polarity &= ~mask; 448 break; 449 case IRQ_TYPE_LEVEL_HIGH: 450 level &= ~mask; 451 polarity |= mask; 452 break; 453 case IRQ_TYPE_LEVEL_LOW: 454 level &= ~mask; 455 polarity &= ~mask; 456 break; 457 default: 458 ret = -EINVAL; 459 goto out; 460 } 461 } 462 463 rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type); 464 rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity); 465 out: 466 raw_spin_unlock_irqrestore(&bank->slock, flags); 467 468 return ret; 469 } 470 471 static int rockchip_irq_reqres(struct irq_data *d) 472 { 473 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 474 struct rockchip_pin_bank *bank = gc->private; 475 476 return gpiochip_reqres_irq(&bank->gpio_chip, d->hwirq); 477 } 478 479 static void rockchip_irq_relres(struct irq_data *d) 480 { 481 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 482 struct rockchip_pin_bank *bank = gc->private; 483 484 gpiochip_relres_irq(&bank->gpio_chip, d->hwirq); 485 } 486 487 static void rockchip_irq_suspend(struct irq_data *d) 488 { 489 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 490 struct rockchip_pin_bank *bank = gc->private; 491 492 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask); 493 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask); 494 } 495 496 static void rockchip_irq_resume(struct irq_data *d) 497 { 498 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 499 struct rockchip_pin_bank *bank = gc->private; 500 501 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask); 502 } 503 504 static void rockchip_irq_enable(struct irq_data *d) 505 { 506 irq_gc_mask_clr_bit(d); 507 } 508 509 static void rockchip_irq_disable(struct irq_data *d) 510 { 511 irq_gc_mask_set_bit(d); 512 } 513 514 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) 515 { 516 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 517 struct irq_chip_generic *gc; 518 int ret; 519 520 bank->domain = irq_domain_add_linear(bank->of_node, 32, 521 &irq_generic_chip_ops, NULL); 522 if (!bank->domain) { 523 dev_warn(bank->dev, "could not init irq domain for bank %s\n", 524 bank->name); 525 return -EINVAL; 526 } 527 528 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 529 "rockchip_gpio_irq", 530 handle_level_irq, 531 clr, 0, 0); 532 if (ret) { 533 dev_err(bank->dev, "could not alloc generic chips for bank %s\n", 534 bank->name); 535 irq_domain_remove(bank->domain); 536 return -EINVAL; 537 } 538 539 gc = irq_get_domain_generic_chip(bank->domain, 0); 540 if (bank->gpio_type == GPIO_TYPE_V2) { 541 gc->reg_writel = gpio_writel_v2; 542 gc->reg_readl = gpio_readl_v2; 543 } 544 545 gc->reg_base = bank->reg_base; 546 gc->private = bank; 547 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask; 548 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi; 549 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 550 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 551 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 552 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; 553 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; 554 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 555 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 556 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 557 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 558 gc->chip_types[0].chip.irq_request_resources = rockchip_irq_reqres; 559 gc->chip_types[0].chip.irq_release_resources = rockchip_irq_relres; 560 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 561 562 /* 563 * Linux assumes that all interrupts start out disabled/masked. 564 * Our driver only uses the concept of masked and always keeps 565 * things enabled, so for us that's all masked and all enabled. 566 */ 567 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask); 568 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi); 569 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en); 570 gc->mask_cache = 0xffffffff; 571 572 irq_set_chained_handler_and_data(bank->irq, 573 rockchip_irq_demux, bank); 574 575 return 0; 576 } 577 578 static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank) 579 { 580 struct gpio_chip *gc; 581 int ret; 582 583 bank->gpio_chip = rockchip_gpiolib_chip; 584 585 gc = &bank->gpio_chip; 586 gc->base = bank->pin_base; 587 gc->ngpio = bank->nr_pins; 588 gc->label = bank->name; 589 gc->parent = bank->dev; 590 591 ret = gpiochip_add_data(gc, bank); 592 if (ret) { 593 dev_err(bank->dev, "failed to add gpiochip %s, %d\n", 594 gc->label, ret); 595 return ret; 596 } 597 598 /* 599 * For DeviceTree-supported systems, the gpio core checks the 600 * pinctrl's device node for the "gpio-ranges" property. 601 * If it is present, it takes care of adding the pin ranges 602 * for the driver. In this case the driver can skip ahead. 603 * 604 * In order to remain compatible with older, existing DeviceTree 605 * files which don't set the "gpio-ranges" property or systems that 606 * utilize ACPI the driver has to call gpiochip_add_pin_range(). 607 */ 608 if (!of_property_read_bool(bank->of_node, "gpio-ranges")) { 609 struct device_node *pctlnp = of_get_parent(bank->of_node); 610 struct pinctrl_dev *pctldev = NULL; 611 612 if (!pctlnp) 613 return -ENODATA; 614 615 pctldev = of_pinctrl_get(pctlnp); 616 if (!pctldev) 617 return -ENODEV; 618 619 ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0, 620 gc->base, gc->ngpio); 621 if (ret) { 622 dev_err(bank->dev, "Failed to add pin range\n"); 623 goto fail; 624 } 625 } 626 627 ret = rockchip_interrupts_register(bank); 628 if (ret) { 629 dev_err(bank->dev, "failed to register interrupt, %d\n", ret); 630 goto fail; 631 } 632 633 return 0; 634 635 fail: 636 gpiochip_remove(&bank->gpio_chip); 637 638 return ret; 639 } 640 641 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank) 642 { 643 struct resource res; 644 int id = 0; 645 646 if (of_address_to_resource(bank->of_node, 0, &res)) { 647 dev_err(bank->dev, "cannot find IO resource for bank\n"); 648 return -ENOENT; 649 } 650 651 bank->reg_base = devm_ioremap_resource(bank->dev, &res); 652 if (IS_ERR(bank->reg_base)) 653 return PTR_ERR(bank->reg_base); 654 655 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 656 if (!bank->irq) 657 return -EINVAL; 658 659 bank->clk = of_clk_get(bank->of_node, 0); 660 if (IS_ERR(bank->clk)) 661 return PTR_ERR(bank->clk); 662 663 clk_prepare_enable(bank->clk); 664 id = readl(bank->reg_base + gpio_regs_v2.version_id); 665 666 /* If not gpio v2, that is default to v1. */ 667 if (id == GPIO_TYPE_V2) { 668 bank->gpio_regs = &gpio_regs_v2; 669 bank->gpio_type = GPIO_TYPE_V2; 670 bank->db_clk = of_clk_get(bank->of_node, 1); 671 if (IS_ERR(bank->db_clk)) { 672 dev_err(bank->dev, "cannot find debounce clk\n"); 673 clk_disable_unprepare(bank->clk); 674 return -EINVAL; 675 } 676 } else { 677 bank->gpio_regs = &gpio_regs_v1; 678 bank->gpio_type = GPIO_TYPE_V1; 679 } 680 681 return 0; 682 } 683 684 static struct rockchip_pin_bank * 685 rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id) 686 { 687 struct rockchip_pinctrl *info; 688 struct rockchip_pin_bank *bank; 689 int i, found = 0; 690 691 info = pinctrl_dev_get_drvdata(pctldev); 692 bank = info->ctrl->pin_banks; 693 for (i = 0; i < info->ctrl->nr_banks; i++, bank++) { 694 if (bank->bank_num == id) { 695 found = 1; 696 break; 697 } 698 } 699 700 return found ? bank : NULL; 701 } 702 703 static int rockchip_gpio_probe(struct platform_device *pdev) 704 { 705 struct device *dev = &pdev->dev; 706 struct device_node *np = dev->of_node; 707 struct device_node *pctlnp = of_get_parent(np); 708 struct pinctrl_dev *pctldev = NULL; 709 struct rockchip_pin_bank *bank = NULL; 710 struct rockchip_pin_deferred *cfg; 711 static int gpio; 712 int id, ret; 713 714 if (!np || !pctlnp) 715 return -ENODEV; 716 717 pctldev = of_pinctrl_get(pctlnp); 718 if (!pctldev) 719 return -EPROBE_DEFER; 720 721 id = of_alias_get_id(np, "gpio"); 722 if (id < 0) 723 id = gpio++; 724 725 bank = rockchip_gpio_find_bank(pctldev, id); 726 if (!bank) 727 return -EINVAL; 728 729 bank->dev = dev; 730 bank->of_node = np; 731 732 raw_spin_lock_init(&bank->slock); 733 734 ret = rockchip_get_bank_data(bank); 735 if (ret) 736 return ret; 737 738 /* 739 * Prevent clashes with a deferred output setting 740 * being added right at this moment. 741 */ 742 mutex_lock(&bank->deferred_lock); 743 744 ret = rockchip_gpiolib_register(bank); 745 if (ret) { 746 clk_disable_unprepare(bank->clk); 747 mutex_unlock(&bank->deferred_lock); 748 return ret; 749 } 750 751 while (!list_empty(&bank->deferred_pins)) { 752 cfg = list_first_entry(&bank->deferred_pins, 753 struct rockchip_pin_deferred, head); 754 list_del(&cfg->head); 755 756 switch (cfg->param) { 757 case PIN_CONFIG_OUTPUT: 758 ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg); 759 if (ret) 760 dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin, 761 cfg->arg); 762 break; 763 case PIN_CONFIG_INPUT_ENABLE: 764 ret = rockchip_gpio_direction_input(&bank->gpio_chip, cfg->pin); 765 if (ret) 766 dev_warn(dev, "setting input pin %u failed\n", cfg->pin); 767 break; 768 default: 769 dev_warn(dev, "unknown deferred config param %d\n", cfg->param); 770 break; 771 } 772 kfree(cfg); 773 } 774 775 mutex_unlock(&bank->deferred_lock); 776 777 platform_set_drvdata(pdev, bank); 778 dev_info(dev, "probed %pOF\n", np); 779 780 return 0; 781 } 782 783 static int rockchip_gpio_remove(struct platform_device *pdev) 784 { 785 struct rockchip_pin_bank *bank = platform_get_drvdata(pdev); 786 787 clk_disable_unprepare(bank->clk); 788 gpiochip_remove(&bank->gpio_chip); 789 790 return 0; 791 } 792 793 static const struct of_device_id rockchip_gpio_match[] = { 794 { .compatible = "rockchip,gpio-bank", }, 795 { .compatible = "rockchip,rk3188-gpio-bank0" }, 796 { }, 797 }; 798 799 static struct platform_driver rockchip_gpio_driver = { 800 .probe = rockchip_gpio_probe, 801 .remove = rockchip_gpio_remove, 802 .driver = { 803 .name = "rockchip-gpio", 804 .of_match_table = rockchip_gpio_match, 805 }, 806 }; 807 808 static int __init rockchip_gpio_init(void) 809 { 810 return platform_driver_register(&rockchip_gpio_driver); 811 } 812 postcore_initcall(rockchip_gpio_init); 813 814 static void __exit rockchip_gpio_exit(void) 815 { 816 platform_driver_unregister(&rockchip_gpio_driver); 817 } 818 module_exit(rockchip_gpio_exit); 819 820 MODULE_DESCRIPTION("Rockchip gpio driver"); 821 MODULE_ALIAS("platform:rockchip-gpio"); 822 MODULE_LICENSE("GPL v2"); 823 MODULE_DEVICE_TABLE(of, rockchip_gpio_match); 824