1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/gpio/driver.h> 4 #include <linux/cpumask.h> 5 #include <linux/irq.h> 6 #include <linux/minmax.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/property.h> 11 12 /* 13 * Total register block size is 0x1C for one bank of four ports (A, B, C, D). 14 * An optional second bank, with ports E, F, G, and H, may be present, starting 15 * at register offset 0x1C. 16 */ 17 18 /* 19 * Pin select: (0) "normal", (1) "dedicate peripheral" 20 * Not used on RTL8380/RTL8390, peripheral selection is managed by control bits 21 * in the peripheral registers. 22 */ 23 #define REALTEK_GPIO_REG_CNR 0x00 24 /* Clear bit (0) for input, set bit (1) for output */ 25 #define REALTEK_GPIO_REG_DIR 0x08 26 #define REALTEK_GPIO_REG_DATA 0x0C 27 /* Read bit for IRQ status, write 1 to clear IRQ */ 28 #define REALTEK_GPIO_REG_ISR 0x10 29 /* Two bits per GPIO in IMR registers */ 30 #define REALTEK_GPIO_REG_IMR 0x14 31 #define REALTEK_GPIO_REG_IMR_AB 0x14 32 #define REALTEK_GPIO_REG_IMR_CD 0x18 33 #define REALTEK_GPIO_IMR_LINE_MASK GENMASK(1, 0) 34 #define REALTEK_GPIO_IRQ_EDGE_FALLING 1 35 #define REALTEK_GPIO_IRQ_EDGE_RISING 2 36 #define REALTEK_GPIO_IRQ_EDGE_BOTH 3 37 38 #define REALTEK_GPIO_MAX 32 39 #define REALTEK_GPIO_PORTS_PER_BANK 4 40 41 /** 42 * realtek_gpio_ctrl - Realtek Otto GPIO driver data 43 * 44 * @gc: Associated gpio_chip instance 45 * @base: Base address of the register block for a GPIO bank 46 * @lock: Lock for accessing the IRQ registers and values 47 * @intr_mask: Mask for interrupts lines 48 * @intr_type: Interrupt type selection 49 * 50 * Because the interrupt mask register (IMR) combines the function of IRQ type 51 * selection and masking, two extra values are stored. @intr_mask is used to 52 * mask/unmask the interrupts for a GPIO port, and @intr_type is used to store 53 * the selected interrupt types. The logical AND of these values is written to 54 * IMR on changes. 55 */ 56 struct realtek_gpio_ctrl { 57 struct gpio_chip gc; 58 void __iomem *base; 59 void __iomem *cpumask_base; 60 struct cpumask cpu_irq_maskable; 61 raw_spinlock_t lock; 62 u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK]; 63 u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK]; 64 unsigned int (*port_offset_u8)(unsigned int port); 65 unsigned int (*port_offset_u16)(unsigned int port); 66 }; 67 68 /* Expand with more flags as devices with other quirks are added */ 69 enum realtek_gpio_flags { 70 /* 71 * Allow disabling interrupts, for cases where the port order is 72 * unknown. This may result in a port mismatch between ISR and IMR. 73 * An interrupt would appear to come from a different line than the 74 * line the IRQ handler was assigned to, causing uncaught interrupts. 75 */ 76 GPIO_INTERRUPTS_DISABLED = BIT(0), 77 /* 78 * Port order is reversed, meaning DCBA register layout for 1-bit 79 * fields, and [BA, DC] for 2-bit fields. 80 */ 81 GPIO_PORTS_REVERSED = BIT(1), 82 /* 83 * Interrupts can be enabled per cpu. This requires a secondary IO 84 * range, where the per-cpu enable masks are located. 85 */ 86 GPIO_INTERRUPTS_PER_CPU = BIT(2), 87 }; 88 89 static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data) 90 { 91 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 92 93 return container_of(gc, struct realtek_gpio_ctrl, gc); 94 } 95 96 /* 97 * Normal port order register access 98 * 99 * Port information is stored with the first port at offset 0, followed by the 100 * second, etc. Most registers store one bit per GPIO and use a u8 value per 101 * port. The two interrupt mask registers store two bits per GPIO, so use u16 102 * values. 103 */ 104 static unsigned int realtek_gpio_port_offset_u8(unsigned int port) 105 { 106 return port; 107 } 108 109 static unsigned int realtek_gpio_port_offset_u16(unsigned int port) 110 { 111 return 2 * port; 112 } 113 114 /* 115 * Reversed port order register access 116 * 117 * For registers with one bit per GPIO, all ports are stored as u8-s in one 118 * register in reversed order. The two interrupt mask registers store two bits 119 * per GPIO, so use u16 values. The first register contains ports 1 and 0, the 120 * second ports 3 and 2. 121 */ 122 static unsigned int realtek_gpio_port_offset_u8_rev(unsigned int port) 123 { 124 return 3 - port; 125 } 126 127 static unsigned int realtek_gpio_port_offset_u16_rev(unsigned int port) 128 { 129 return 2 * (port ^ 1); 130 } 131 132 static void realtek_gpio_write_imr(struct realtek_gpio_ctrl *ctrl, 133 unsigned int port, u16 irq_type, u16 irq_mask) 134 { 135 iowrite16(irq_type & irq_mask, 136 ctrl->base + REALTEK_GPIO_REG_IMR + ctrl->port_offset_u16(port)); 137 } 138 139 static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, 140 unsigned int port, u8 mask) 141 { 142 iowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port)); 143 } 144 145 static u8 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl, unsigned int port) 146 { 147 return ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port)); 148 } 149 150 /* Set the rising and falling edge mask bits for a GPIO port pin */ 151 static u16 realtek_gpio_imr_bits(unsigned int pin, u16 value) 152 { 153 return (value & REALTEK_GPIO_IMR_LINE_MASK) << 2 * pin; 154 } 155 156 static void realtek_gpio_irq_ack(struct irq_data *data) 157 { 158 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 159 irq_hw_number_t line = irqd_to_hwirq(data); 160 unsigned int port = line / 8; 161 unsigned int port_pin = line % 8; 162 163 realtek_gpio_clear_isr(ctrl, port, BIT(port_pin)); 164 } 165 166 static void realtek_gpio_irq_unmask(struct irq_data *data) 167 { 168 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 169 unsigned int line = irqd_to_hwirq(data); 170 unsigned int port = line / 8; 171 unsigned int port_pin = line % 8; 172 unsigned long flags; 173 u16 m; 174 175 raw_spin_lock_irqsave(&ctrl->lock, flags); 176 m = ctrl->intr_mask[port]; 177 m |= realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); 178 ctrl->intr_mask[port] = m; 179 realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m); 180 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 181 } 182 183 static void realtek_gpio_irq_mask(struct irq_data *data) 184 { 185 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 186 unsigned int line = irqd_to_hwirq(data); 187 unsigned int port = line / 8; 188 unsigned int port_pin = line % 8; 189 unsigned long flags; 190 u16 m; 191 192 raw_spin_lock_irqsave(&ctrl->lock, flags); 193 m = ctrl->intr_mask[port]; 194 m &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); 195 ctrl->intr_mask[port] = m; 196 realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m); 197 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 198 } 199 200 static int realtek_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) 201 { 202 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 203 unsigned int line = irqd_to_hwirq(data); 204 unsigned int port = line / 8; 205 unsigned int port_pin = line % 8; 206 unsigned long flags; 207 u16 type, t; 208 209 switch (flow_type & IRQ_TYPE_SENSE_MASK) { 210 case IRQ_TYPE_EDGE_FALLING: 211 type = REALTEK_GPIO_IRQ_EDGE_FALLING; 212 break; 213 case IRQ_TYPE_EDGE_RISING: 214 type = REALTEK_GPIO_IRQ_EDGE_RISING; 215 break; 216 case IRQ_TYPE_EDGE_BOTH: 217 type = REALTEK_GPIO_IRQ_EDGE_BOTH; 218 break; 219 default: 220 return -EINVAL; 221 } 222 223 irq_set_handler_locked(data, handle_edge_irq); 224 225 raw_spin_lock_irqsave(&ctrl->lock, flags); 226 t = ctrl->intr_type[port]; 227 t &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); 228 t |= realtek_gpio_imr_bits(port_pin, type); 229 ctrl->intr_type[port] = t; 230 realtek_gpio_write_imr(ctrl, port, t, ctrl->intr_mask[port]); 231 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 232 233 return 0; 234 } 235 236 static void realtek_gpio_irq_handler(struct irq_desc *desc) 237 { 238 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 239 struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); 240 struct irq_chip *irq_chip = irq_desc_get_chip(desc); 241 unsigned int lines_done; 242 unsigned int port_pin_count; 243 unsigned long status; 244 int offset; 245 246 chained_irq_enter(irq_chip, desc); 247 248 for (lines_done = 0; lines_done < gc->ngpio; lines_done += 8) { 249 status = realtek_gpio_read_isr(ctrl, lines_done / 8); 250 port_pin_count = min(gc->ngpio - lines_done, 8U); 251 for_each_set_bit(offset, &status, port_pin_count) 252 generic_handle_domain_irq(gc->irq.domain, offset + lines_done); 253 } 254 255 chained_irq_exit(irq_chip, desc); 256 } 257 258 static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl, 259 unsigned int port, int cpu) 260 { 261 return ctrl->cpumask_base + ctrl->port_offset_u8(port) + 262 REALTEK_GPIO_PORTS_PER_BANK * cpu; 263 } 264 265 static int realtek_gpio_irq_set_affinity(struct irq_data *data, 266 const struct cpumask *dest, bool force) 267 { 268 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 269 unsigned int line = irqd_to_hwirq(data); 270 unsigned int port = line / 8; 271 unsigned int port_pin = line % 8; 272 void __iomem *irq_cpu_mask; 273 unsigned long flags; 274 int cpu; 275 u8 v; 276 277 if (!ctrl->cpumask_base) 278 return -ENXIO; 279 280 raw_spin_lock_irqsave(&ctrl->lock, flags); 281 282 for_each_cpu(cpu, &ctrl->cpu_irq_maskable) { 283 irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, port, cpu); 284 v = ioread8(irq_cpu_mask); 285 286 if (cpumask_test_cpu(cpu, dest)) 287 v |= BIT(port_pin); 288 else 289 v &= ~BIT(port_pin); 290 291 iowrite8(v, irq_cpu_mask); 292 } 293 294 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 295 296 irq_data_update_effective_affinity(data, dest); 297 298 return 0; 299 } 300 301 static int realtek_gpio_irq_init(struct gpio_chip *gc) 302 { 303 struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); 304 unsigned int port; 305 int cpu; 306 307 for (port = 0; (port * 8) < gc->ngpio; port++) { 308 realtek_gpio_write_imr(ctrl, port, 0, 0); 309 realtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0)); 310 311 for_each_cpu(cpu, &ctrl->cpu_irq_maskable) 312 iowrite8(GENMASK(7, 0), realtek_gpio_irq_cpu_mask(ctrl, port, cpu)); 313 } 314 315 return 0; 316 } 317 318 static struct irq_chip realtek_gpio_irq_chip = { 319 .name = "realtek-otto-gpio", 320 .irq_ack = realtek_gpio_irq_ack, 321 .irq_mask = realtek_gpio_irq_mask, 322 .irq_unmask = realtek_gpio_irq_unmask, 323 .irq_set_type = realtek_gpio_irq_set_type, 324 .irq_set_affinity = realtek_gpio_irq_set_affinity, 325 }; 326 327 static const struct of_device_id realtek_gpio_of_match[] = { 328 { 329 .compatible = "realtek,otto-gpio", 330 .data = (void *)GPIO_INTERRUPTS_DISABLED, 331 }, 332 { 333 .compatible = "realtek,rtl8380-gpio", 334 }, 335 { 336 .compatible = "realtek,rtl8390-gpio", 337 }, 338 { 339 .compatible = "realtek,rtl9300-gpio", 340 .data = (void *)(GPIO_PORTS_REVERSED | GPIO_INTERRUPTS_PER_CPU) 341 }, 342 { 343 .compatible = "realtek,rtl9310-gpio", 344 }, 345 {} 346 }; 347 MODULE_DEVICE_TABLE(of, realtek_gpio_of_match); 348 349 static int realtek_gpio_probe(struct platform_device *pdev) 350 { 351 struct device *dev = &pdev->dev; 352 unsigned long bgpio_flags; 353 unsigned int dev_flags; 354 struct gpio_irq_chip *girq; 355 struct realtek_gpio_ctrl *ctrl; 356 struct resource *res; 357 u32 ngpios; 358 unsigned int nr_cpus; 359 int cpu, err, irq; 360 361 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 362 if (!ctrl) 363 return -ENOMEM; 364 365 dev_flags = (unsigned int) device_get_match_data(dev); 366 367 ngpios = REALTEK_GPIO_MAX; 368 device_property_read_u32(dev, "ngpios", &ngpios); 369 370 if (ngpios > REALTEK_GPIO_MAX) { 371 dev_err(&pdev->dev, "invalid ngpios (max. %d)\n", 372 REALTEK_GPIO_MAX); 373 return -EINVAL; 374 } 375 376 ctrl->base = devm_platform_ioremap_resource(pdev, 0); 377 if (IS_ERR(ctrl->base)) 378 return PTR_ERR(ctrl->base); 379 380 raw_spin_lock_init(&ctrl->lock); 381 382 if (dev_flags & GPIO_PORTS_REVERSED) { 383 bgpio_flags = 0; 384 ctrl->port_offset_u8 = realtek_gpio_port_offset_u8_rev; 385 ctrl->port_offset_u16 = realtek_gpio_port_offset_u16_rev; 386 } else { 387 bgpio_flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER; 388 ctrl->port_offset_u8 = realtek_gpio_port_offset_u8; 389 ctrl->port_offset_u16 = realtek_gpio_port_offset_u16; 390 } 391 392 err = bgpio_init(&ctrl->gc, dev, 4, 393 ctrl->base + REALTEK_GPIO_REG_DATA, NULL, NULL, 394 ctrl->base + REALTEK_GPIO_REG_DIR, NULL, 395 bgpio_flags); 396 if (err) { 397 dev_err(dev, "unable to init generic GPIO"); 398 return err; 399 } 400 401 ctrl->gc.ngpio = ngpios; 402 ctrl->gc.owner = THIS_MODULE; 403 404 irq = platform_get_irq_optional(pdev, 0); 405 if (!(dev_flags & GPIO_INTERRUPTS_DISABLED) && irq > 0) { 406 girq = &ctrl->gc.irq; 407 girq->chip = &realtek_gpio_irq_chip; 408 girq->default_type = IRQ_TYPE_NONE; 409 girq->handler = handle_bad_irq; 410 girq->parent_handler = realtek_gpio_irq_handler; 411 girq->num_parents = 1; 412 girq->parents = devm_kcalloc(dev, girq->num_parents, 413 sizeof(*girq->parents), GFP_KERNEL); 414 if (!girq->parents) 415 return -ENOMEM; 416 girq->parents[0] = irq; 417 girq->init_hw = realtek_gpio_irq_init; 418 } 419 420 cpumask_clear(&ctrl->cpu_irq_maskable); 421 422 if ((dev_flags & GPIO_INTERRUPTS_PER_CPU) && irq > 0) { 423 ctrl->cpumask_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); 424 if (IS_ERR(ctrl->cpumask_base)) 425 return dev_err_probe(dev, PTR_ERR(ctrl->cpumask_base), 426 "missing CPU IRQ mask registers"); 427 428 nr_cpus = resource_size(res) / REALTEK_GPIO_PORTS_PER_BANK; 429 nr_cpus = min(nr_cpus, num_present_cpus()); 430 431 for (cpu = 0; cpu < nr_cpus; cpu++) 432 cpumask_set_cpu(cpu, &ctrl->cpu_irq_maskable); 433 } 434 435 return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); 436 } 437 438 static struct platform_driver realtek_gpio_driver = { 439 .driver = { 440 .name = "realtek-otto-gpio", 441 .of_match_table = realtek_gpio_of_match, 442 }, 443 .probe = realtek_gpio_probe, 444 }; 445 module_platform_driver(realtek_gpio_driver); 446 447 MODULE_DESCRIPTION("Realtek Otto GPIO support"); 448 MODULE_AUTHOR("Sander Vanheule <sander@svanheule.net>"); 449 MODULE_LICENSE("GPL v2"); 450