1 /* 2 * Renesas R-Car GPIO Support 3 * 4 * Copyright (C) 2013 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/err.h> 17 #include <linux/gpio.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/ioport.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/platform_data/gpio-rcar.h> 28 #include <linux/platform_device.h> 29 #include <linux/spinlock.h> 30 #include <linux/slab.h> 31 32 struct gpio_rcar_priv { 33 void __iomem *base; 34 spinlock_t lock; 35 struct gpio_rcar_config config; 36 struct platform_device *pdev; 37 struct gpio_chip gpio_chip; 38 struct irq_chip irq_chip; 39 struct irq_domain *irq_domain; 40 }; 41 42 #define IOINTSEL 0x00 43 #define INOUTSEL 0x04 44 #define OUTDT 0x08 45 #define INDT 0x0c 46 #define INTDT 0x10 47 #define INTCLR 0x14 48 #define INTMSK 0x18 49 #define MSKCLR 0x1c 50 #define POSNEG 0x20 51 #define EDGLEVEL 0x24 52 #define FILONOFF 0x28 53 #define BOTHEDGE 0x4c 54 55 #define RCAR_MAX_GPIO_PER_BANK 32 56 57 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs) 58 { 59 return ioread32(p->base + offs); 60 } 61 62 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs, 63 u32 value) 64 { 65 iowrite32(value, p->base + offs); 66 } 67 68 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs, 69 int bit, bool value) 70 { 71 u32 tmp = gpio_rcar_read(p, offs); 72 73 if (value) 74 tmp |= BIT(bit); 75 else 76 tmp &= ~BIT(bit); 77 78 gpio_rcar_write(p, offs, tmp); 79 } 80 81 static void gpio_rcar_irq_disable(struct irq_data *d) 82 { 83 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); 84 85 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d))); 86 } 87 88 static void gpio_rcar_irq_enable(struct irq_data *d) 89 { 90 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); 91 92 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d))); 93 } 94 95 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, 96 unsigned int hwirq, 97 bool active_high_rising_edge, 98 bool level_trigger, 99 bool both) 100 { 101 unsigned long flags; 102 103 /* follow steps in the GPIO documentation for 104 * "Setting Edge-Sensitive Interrupt Input Mode" and 105 * "Setting Level-Sensitive Interrupt Input Mode" 106 */ 107 108 spin_lock_irqsave(&p->lock, flags); 109 110 /* Configure postive or negative logic in POSNEG */ 111 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge); 112 113 /* Configure edge or level trigger in EDGLEVEL */ 114 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); 115 116 /* Select one edge or both edges in BOTHEDGE */ 117 if (p->config.has_both_edge_trigger) 118 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both); 119 120 /* Select "Interrupt Input Mode" in IOINTSEL */ 121 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); 122 123 /* Write INTCLR in case of edge trigger */ 124 if (!level_trigger) 125 gpio_rcar_write(p, INTCLR, BIT(hwirq)); 126 127 spin_unlock_irqrestore(&p->lock, flags); 128 } 129 130 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) 131 { 132 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); 133 unsigned int hwirq = irqd_to_hwirq(d); 134 135 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type); 136 137 switch (type & IRQ_TYPE_SENSE_MASK) { 138 case IRQ_TYPE_LEVEL_HIGH: 139 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true, 140 false); 141 break; 142 case IRQ_TYPE_LEVEL_LOW: 143 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true, 144 false); 145 break; 146 case IRQ_TYPE_EDGE_RISING: 147 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, 148 false); 149 break; 150 case IRQ_TYPE_EDGE_FALLING: 151 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false, 152 false); 153 break; 154 case IRQ_TYPE_EDGE_BOTH: 155 if (!p->config.has_both_edge_trigger) 156 return -EINVAL; 157 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, 158 true); 159 break; 160 default: 161 return -EINVAL; 162 } 163 return 0; 164 } 165 166 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) 167 { 168 struct gpio_rcar_priv *p = dev_id; 169 u32 pending; 170 unsigned int offset, irqs_handled = 0; 171 172 while ((pending = gpio_rcar_read(p, INTDT) & 173 gpio_rcar_read(p, INTMSK))) { 174 offset = __ffs(pending); 175 gpio_rcar_write(p, INTCLR, BIT(offset)); 176 generic_handle_irq(irq_find_mapping(p->irq_domain, offset)); 177 irqs_handled++; 178 } 179 180 return irqs_handled ? IRQ_HANDLED : IRQ_NONE; 181 } 182 183 static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip) 184 { 185 return container_of(chip, struct gpio_rcar_priv, gpio_chip); 186 } 187 188 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip, 189 unsigned int gpio, 190 bool output) 191 { 192 struct gpio_rcar_priv *p = gpio_to_priv(chip); 193 unsigned long flags; 194 195 /* follow steps in the GPIO documentation for 196 * "Setting General Output Mode" and 197 * "Setting General Input Mode" 198 */ 199 200 spin_lock_irqsave(&p->lock, flags); 201 202 /* Configure postive logic in POSNEG */ 203 gpio_rcar_modify_bit(p, POSNEG, gpio, false); 204 205 /* Select "General Input/Output Mode" in IOINTSEL */ 206 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false); 207 208 /* Select Input Mode or Output Mode in INOUTSEL */ 209 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output); 210 211 spin_unlock_irqrestore(&p->lock, flags); 212 } 213 214 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset) 215 { 216 return pinctrl_request_gpio(chip->base + offset); 217 } 218 219 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset) 220 { 221 pinctrl_free_gpio(chip->base + offset); 222 223 /* Set the GPIO as an input to ensure that the next GPIO request won't 224 * drive the GPIO pin as an output. 225 */ 226 gpio_rcar_config_general_input_output_mode(chip, offset, false); 227 } 228 229 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) 230 { 231 gpio_rcar_config_general_input_output_mode(chip, offset, false); 232 return 0; 233 } 234 235 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset) 236 { 237 u32 bit = BIT(offset); 238 239 /* testing on r8a7790 shows that INDT does not show correct pin state 240 * when configured as output, so use OUTDT in case of output pins */ 241 if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit) 242 return (int)(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit); 243 else 244 return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit); 245 } 246 247 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value) 248 { 249 struct gpio_rcar_priv *p = gpio_to_priv(chip); 250 unsigned long flags; 251 252 spin_lock_irqsave(&p->lock, flags); 253 gpio_rcar_modify_bit(p, OUTDT, offset, value); 254 spin_unlock_irqrestore(&p->lock, flags); 255 } 256 257 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset, 258 int value) 259 { 260 /* write GPIO value to output before selecting output mode of pin */ 261 gpio_rcar_set(chip, offset, value); 262 gpio_rcar_config_general_input_output_mode(chip, offset, true); 263 return 0; 264 } 265 266 static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset) 267 { 268 return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset); 269 } 270 271 static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int irq, 272 irq_hw_number_t hwirq) 273 { 274 struct gpio_rcar_priv *p = h->host_data; 275 276 dev_dbg(&p->pdev->dev, "map hw irq = %d, irq = %d\n", (int)hwirq, irq); 277 278 irq_set_chip_data(irq, h->host_data); 279 irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq); 280 set_irq_flags(irq, IRQF_VALID); /* kill me now */ 281 return 0; 282 } 283 284 static struct irq_domain_ops gpio_rcar_irq_domain_ops = { 285 .map = gpio_rcar_irq_domain_map, 286 }; 287 288 struct gpio_rcar_info { 289 bool has_both_edge_trigger; 290 }; 291 292 static const struct of_device_id gpio_rcar_of_table[] = { 293 { 294 .compatible = "renesas,gpio-r8a7790", 295 .data = (void *)&(const struct gpio_rcar_info) { 296 .has_both_edge_trigger = true, 297 }, 298 }, { 299 .compatible = "renesas,gpio-r8a7791", 300 .data = (void *)&(const struct gpio_rcar_info) { 301 .has_both_edge_trigger = true, 302 }, 303 }, { 304 .compatible = "renesas,gpio-rcar", 305 .data = (void *)&(const struct gpio_rcar_info) { 306 .has_both_edge_trigger = false, 307 }, 308 }, { 309 /* Terminator */ 310 }, 311 }; 312 313 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table); 314 315 static int gpio_rcar_parse_pdata(struct gpio_rcar_priv *p) 316 { 317 struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev); 318 struct device_node *np = p->pdev->dev.of_node; 319 struct of_phandle_args args; 320 int ret; 321 322 if (pdata) { 323 p->config = *pdata; 324 } else if (IS_ENABLED(CONFIG_OF) && np) { 325 const struct of_device_id *match; 326 const struct gpio_rcar_info *info; 327 328 match = of_match_node(gpio_rcar_of_table, np); 329 if (!match) 330 return -EINVAL; 331 332 info = match->data; 333 334 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, 335 &args); 336 p->config.number_of_pins = ret == 0 ? args.args[2] 337 : RCAR_MAX_GPIO_PER_BANK; 338 p->config.gpio_base = -1; 339 p->config.has_both_edge_trigger = info->has_both_edge_trigger; 340 } 341 342 if (p->config.number_of_pins == 0 || 343 p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) { 344 dev_warn(&p->pdev->dev, 345 "Invalid number of gpio lines %u, using %u\n", 346 p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK); 347 p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK; 348 } 349 350 return 0; 351 } 352 353 static int gpio_rcar_probe(struct platform_device *pdev) 354 { 355 struct gpio_rcar_priv *p; 356 struct resource *io, *irq; 357 struct gpio_chip *gpio_chip; 358 struct irq_chip *irq_chip; 359 struct device *dev = &pdev->dev; 360 const char *name = dev_name(dev); 361 int ret; 362 363 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); 364 if (!p) { 365 dev_err(dev, "failed to allocate driver data\n"); 366 ret = -ENOMEM; 367 goto err0; 368 } 369 370 p->pdev = pdev; 371 spin_lock_init(&p->lock); 372 373 /* Get device configuration from DT node or platform data. */ 374 ret = gpio_rcar_parse_pdata(p); 375 if (ret < 0) 376 return ret; 377 378 platform_set_drvdata(pdev, p); 379 380 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 381 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 382 383 if (!io || !irq) { 384 dev_err(dev, "missing IRQ or IOMEM\n"); 385 ret = -EINVAL; 386 goto err0; 387 } 388 389 p->base = devm_ioremap_nocache(dev, io->start, resource_size(io)); 390 if (!p->base) { 391 dev_err(dev, "failed to remap I/O memory\n"); 392 ret = -ENXIO; 393 goto err0; 394 } 395 396 gpio_chip = &p->gpio_chip; 397 gpio_chip->request = gpio_rcar_request; 398 gpio_chip->free = gpio_rcar_free; 399 gpio_chip->direction_input = gpio_rcar_direction_input; 400 gpio_chip->get = gpio_rcar_get; 401 gpio_chip->direction_output = gpio_rcar_direction_output; 402 gpio_chip->set = gpio_rcar_set; 403 gpio_chip->to_irq = gpio_rcar_to_irq; 404 gpio_chip->label = name; 405 gpio_chip->dev = dev; 406 gpio_chip->owner = THIS_MODULE; 407 gpio_chip->base = p->config.gpio_base; 408 gpio_chip->ngpio = p->config.number_of_pins; 409 410 irq_chip = &p->irq_chip; 411 irq_chip->name = name; 412 irq_chip->irq_mask = gpio_rcar_irq_disable; 413 irq_chip->irq_unmask = gpio_rcar_irq_enable; 414 irq_chip->irq_set_type = gpio_rcar_irq_set_type; 415 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED 416 | IRQCHIP_MASK_ON_SUSPEND; 417 418 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, 419 p->config.number_of_pins, 420 p->config.irq_base, 421 &gpio_rcar_irq_domain_ops, p); 422 if (!p->irq_domain) { 423 ret = -ENXIO; 424 dev_err(dev, "cannot initialize irq domain\n"); 425 goto err0; 426 } 427 428 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler, 429 IRQF_SHARED, name, p)) { 430 dev_err(dev, "failed to request IRQ\n"); 431 ret = -ENOENT; 432 goto err1; 433 } 434 435 ret = gpiochip_add(gpio_chip); 436 if (ret) { 437 dev_err(dev, "failed to add GPIO controller\n"); 438 goto err1; 439 } 440 441 dev_info(dev, "driving %d GPIOs\n", p->config.number_of_pins); 442 443 /* warn in case of mismatch if irq base is specified */ 444 if (p->config.irq_base) { 445 ret = irq_find_mapping(p->irq_domain, 0); 446 if (p->config.irq_base != ret) 447 dev_warn(dev, "irq base mismatch (%u/%u)\n", 448 p->config.irq_base, ret); 449 } 450 451 if (p->config.pctl_name) { 452 ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0, 453 gpio_chip->base, gpio_chip->ngpio); 454 if (ret < 0) 455 dev_warn(dev, "failed to add pin range\n"); 456 } 457 458 return 0; 459 460 err1: 461 irq_domain_remove(p->irq_domain); 462 err0: 463 return ret; 464 } 465 466 static int gpio_rcar_remove(struct platform_device *pdev) 467 { 468 struct gpio_rcar_priv *p = platform_get_drvdata(pdev); 469 int ret; 470 471 ret = gpiochip_remove(&p->gpio_chip); 472 if (ret) 473 return ret; 474 475 irq_domain_remove(p->irq_domain); 476 return 0; 477 } 478 479 static struct platform_driver gpio_rcar_device_driver = { 480 .probe = gpio_rcar_probe, 481 .remove = gpio_rcar_remove, 482 .driver = { 483 .name = "gpio_rcar", 484 .of_match_table = of_match_ptr(gpio_rcar_of_table), 485 } 486 }; 487 488 module_platform_driver(gpio_rcar_device_driver); 489 490 MODULE_AUTHOR("Magnus Damm"); 491 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver"); 492 MODULE_LICENSE("GPL v2"); 493