xref: /openbmc/linux/drivers/gpio/gpio-rcar.c (revision a06c488d) 
1 /*
2  * Renesas R-Car GPIO Support
3  *
4  *  Copyright (C) 2014 Renesas Electronics Corporation
5  *  Copyright (C) 2013 Magnus Damm
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16 
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/gpio.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/ioport.h>
24 #include <linux/irq.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/spinlock.h>
31 #include <linux/slab.h>
32 
33 struct gpio_rcar_priv {
34 	void __iomem *base;
35 	spinlock_t lock;
36 	struct platform_device *pdev;
37 	struct gpio_chip gpio_chip;
38 	struct irq_chip irq_chip;
39 	struct clk *clk;
40 	unsigned int irq_parent;
41 	bool has_both_edge_trigger;
42 	bool needs_clk;
43 };
44 
45 #define IOINTSEL 0x00	/* General IO/Interrupt Switching Register */
46 #define INOUTSEL 0x04	/* General Input/Output Switching Register */
47 #define OUTDT 0x08	/* General Output Register */
48 #define INDT 0x0c	/* General Input Register */
49 #define INTDT 0x10	/* Interrupt Display Register */
50 #define INTCLR 0x14	/* Interrupt Clear Register */
51 #define INTMSK 0x18	/* Interrupt Mask Register */
52 #define MSKCLR 0x1c	/* Interrupt Mask Clear Register */
53 #define POSNEG 0x20	/* Positive/Negative Logic Select Register */
54 #define EDGLEVEL 0x24	/* Edge/level Select Register */
55 #define FILONOFF 0x28	/* Chattering Prevention On/Off Register */
56 #define BOTHEDGE 0x4c	/* One Edge/Both Edge Select Register */
57 
58 #define RCAR_MAX_GPIO_PER_BANK		32
59 
60 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
61 {
62 	return ioread32(p->base + offs);
63 }
64 
65 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
66 				   u32 value)
67 {
68 	iowrite32(value, p->base + offs);
69 }
70 
71 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
72 				 int bit, bool value)
73 {
74 	u32 tmp = gpio_rcar_read(p, offs);
75 
76 	if (value)
77 		tmp |= BIT(bit);
78 	else
79 		tmp &= ~BIT(bit);
80 
81 	gpio_rcar_write(p, offs, tmp);
82 }
83 
84 static void gpio_rcar_irq_disable(struct irq_data *d)
85 {
86 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
87 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
88 
89 	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
90 }
91 
92 static void gpio_rcar_irq_enable(struct irq_data *d)
93 {
94 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
95 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
96 
97 	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
98 }
99 
100 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
101 						  unsigned int hwirq,
102 						  bool active_high_rising_edge,
103 						  bool level_trigger,
104 						  bool both)
105 {
106 	unsigned long flags;
107 
108 	/* follow steps in the GPIO documentation for
109 	 * "Setting Edge-Sensitive Interrupt Input Mode" and
110 	 * "Setting Level-Sensitive Interrupt Input Mode"
111 	 */
112 
113 	spin_lock_irqsave(&p->lock, flags);
114 
115 	/* Configure postive or negative logic in POSNEG */
116 	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
117 
118 	/* Configure edge or level trigger in EDGLEVEL */
119 	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
120 
121 	/* Select one edge or both edges in BOTHEDGE */
122 	if (p->has_both_edge_trigger)
123 		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
124 
125 	/* Select "Interrupt Input Mode" in IOINTSEL */
126 	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
127 
128 	/* Write INTCLR in case of edge trigger */
129 	if (!level_trigger)
130 		gpio_rcar_write(p, INTCLR, BIT(hwirq));
131 
132 	spin_unlock_irqrestore(&p->lock, flags);
133 }
134 
135 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
136 {
137 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
138 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
139 	unsigned int hwirq = irqd_to_hwirq(d);
140 
141 	dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
142 
143 	switch (type & IRQ_TYPE_SENSE_MASK) {
144 	case IRQ_TYPE_LEVEL_HIGH:
145 		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
146 						      false);
147 		break;
148 	case IRQ_TYPE_LEVEL_LOW:
149 		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
150 						      false);
151 		break;
152 	case IRQ_TYPE_EDGE_RISING:
153 		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
154 						      false);
155 		break;
156 	case IRQ_TYPE_EDGE_FALLING:
157 		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
158 						      false);
159 		break;
160 	case IRQ_TYPE_EDGE_BOTH:
161 		if (!p->has_both_edge_trigger)
162 			return -EINVAL;
163 		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
164 						      true);
165 		break;
166 	default:
167 		return -EINVAL;
168 	}
169 	return 0;
170 }
171 
172 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
173 {
174 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
175 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
176 	int error;
177 
178 	if (p->irq_parent) {
179 		error = irq_set_irq_wake(p->irq_parent, on);
180 		if (error) {
181 			dev_dbg(&p->pdev->dev,
182 				"irq %u doesn't support irq_set_wake\n",
183 				p->irq_parent);
184 			p->irq_parent = 0;
185 		}
186 	}
187 
188 	if (!p->clk)
189 		return 0;
190 
191 	if (on)
192 		clk_enable(p->clk);
193 	else
194 		clk_disable(p->clk);
195 
196 	return 0;
197 }
198 
199 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
200 {
201 	struct gpio_rcar_priv *p = dev_id;
202 	u32 pending;
203 	unsigned int offset, irqs_handled = 0;
204 
205 	while ((pending = gpio_rcar_read(p, INTDT) &
206 			  gpio_rcar_read(p, INTMSK))) {
207 		offset = __ffs(pending);
208 		gpio_rcar_write(p, INTCLR, BIT(offset));
209 		generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,
210 						    offset));
211 		irqs_handled++;
212 	}
213 
214 	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
215 }
216 
217 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
218 						       unsigned int gpio,
219 						       bool output)
220 {
221 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
222 	unsigned long flags;
223 
224 	/* follow steps in the GPIO documentation for
225 	 * "Setting General Output Mode" and
226 	 * "Setting General Input Mode"
227 	 */
228 
229 	spin_lock_irqsave(&p->lock, flags);
230 
231 	/* Configure postive logic in POSNEG */
232 	gpio_rcar_modify_bit(p, POSNEG, gpio, false);
233 
234 	/* Select "General Input/Output Mode" in IOINTSEL */
235 	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
236 
237 	/* Select Input Mode or Output Mode in INOUTSEL */
238 	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
239 
240 	spin_unlock_irqrestore(&p->lock, flags);
241 }
242 
243 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
244 {
245 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
246 	int error;
247 
248 	error = pm_runtime_get_sync(&p->pdev->dev);
249 	if (error < 0)
250 		return error;
251 
252 	error = pinctrl_request_gpio(chip->base + offset);
253 	if (error)
254 		pm_runtime_put(&p->pdev->dev);
255 
256 	return error;
257 }
258 
259 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
260 {
261 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
262 
263 	pinctrl_free_gpio(chip->base + offset);
264 
265 	/* Set the GPIO as an input to ensure that the next GPIO request won't
266 	 * drive the GPIO pin as an output.
267 	 */
268 	gpio_rcar_config_general_input_output_mode(chip, offset, false);
269 
270 	pm_runtime_put(&p->pdev->dev);
271 }
272 
273 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
274 {
275 	gpio_rcar_config_general_input_output_mode(chip, offset, false);
276 	return 0;
277 }
278 
279 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
280 {
281 	u32 bit = BIT(offset);
282 
283 	/* testing on r8a7790 shows that INDT does not show correct pin state
284 	 * when configured as output, so use OUTDT in case of output pins */
285 	if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
286 		return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
287 	else
288 		return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
289 }
290 
291 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
292 {
293 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
294 	unsigned long flags;
295 
296 	spin_lock_irqsave(&p->lock, flags);
297 	gpio_rcar_modify_bit(p, OUTDT, offset, value);
298 	spin_unlock_irqrestore(&p->lock, flags);
299 }
300 
301 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
302 				      int value)
303 {
304 	/* write GPIO value to output before selecting output mode of pin */
305 	gpio_rcar_set(chip, offset, value);
306 	gpio_rcar_config_general_input_output_mode(chip, offset, true);
307 	return 0;
308 }
309 
310 struct gpio_rcar_info {
311 	bool has_both_edge_trigger;
312 	bool needs_clk;
313 };
314 
315 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
316 	.has_both_edge_trigger = false,
317 	.needs_clk = false,
318 };
319 
320 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
321 	.has_both_edge_trigger = true,
322 	.needs_clk = true,
323 };
324 
325 static const struct of_device_id gpio_rcar_of_table[] = {
326 	{
327 		.compatible = "renesas,gpio-r8a7790",
328 		.data = &gpio_rcar_info_gen2,
329 	}, {
330 		.compatible = "renesas,gpio-r8a7791",
331 		.data = &gpio_rcar_info_gen2,
332 	}, {
333 		.compatible = "renesas,gpio-r8a7793",
334 		.data = &gpio_rcar_info_gen2,
335 	}, {
336 		.compatible = "renesas,gpio-r8a7794",
337 		.data = &gpio_rcar_info_gen2,
338 	}, {
339 		.compatible = "renesas,gpio-r8a7795",
340 		/* Gen3 GPIO is identical to Gen2. */
341 		.data = &gpio_rcar_info_gen2,
342 	}, {
343 		.compatible = "renesas,gpio-rcar",
344 		.data = &gpio_rcar_info_gen1,
345 	}, {
346 		/* Terminator */
347 	},
348 };
349 
350 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
351 
352 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
353 {
354 	struct device_node *np = p->pdev->dev.of_node;
355 	const struct of_device_id *match;
356 	const struct gpio_rcar_info *info;
357 	struct of_phandle_args args;
358 	int ret;
359 
360 	match = of_match_node(gpio_rcar_of_table, np);
361 	if (!match)
362 		return -EINVAL;
363 
364 	info = match->data;
365 
366 	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
367 	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
368 	p->has_both_edge_trigger = info->has_both_edge_trigger;
369 	p->needs_clk = info->needs_clk;
370 
371 	if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
372 		dev_warn(&p->pdev->dev,
373 			 "Invalid number of gpio lines %u, using %u\n", *npins,
374 			 RCAR_MAX_GPIO_PER_BANK);
375 		*npins = RCAR_MAX_GPIO_PER_BANK;
376 	}
377 
378 	return 0;
379 }
380 
381 static int gpio_rcar_probe(struct platform_device *pdev)
382 {
383 	struct gpio_rcar_priv *p;
384 	struct resource *io, *irq;
385 	struct gpio_chip *gpio_chip;
386 	struct irq_chip *irq_chip;
387 	struct device *dev = &pdev->dev;
388 	const char *name = dev_name(dev);
389 	unsigned int npins;
390 	int ret;
391 
392 	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
393 	if (!p)
394 		return -ENOMEM;
395 
396 	p->pdev = pdev;
397 	spin_lock_init(&p->lock);
398 
399 	/* Get device configuration from DT node */
400 	ret = gpio_rcar_parse_dt(p, &npins);
401 	if (ret < 0)
402 		return ret;
403 
404 	platform_set_drvdata(pdev, p);
405 
406 	p->clk = devm_clk_get(dev, NULL);
407 	if (IS_ERR(p->clk)) {
408 		if (p->needs_clk) {
409 			dev_err(dev, "unable to get clock\n");
410 			ret = PTR_ERR(p->clk);
411 			goto err0;
412 		}
413 		p->clk = NULL;
414 	}
415 
416 	pm_runtime_enable(dev);
417 
418 	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
419 	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
420 
421 	if (!io || !irq) {
422 		dev_err(dev, "missing IRQ or IOMEM\n");
423 		ret = -EINVAL;
424 		goto err0;
425 	}
426 
427 	p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
428 	if (!p->base) {
429 		dev_err(dev, "failed to remap I/O memory\n");
430 		ret = -ENXIO;
431 		goto err0;
432 	}
433 
434 	gpio_chip = &p->gpio_chip;
435 	gpio_chip->request = gpio_rcar_request;
436 	gpio_chip->free = gpio_rcar_free;
437 	gpio_chip->direction_input = gpio_rcar_direction_input;
438 	gpio_chip->get = gpio_rcar_get;
439 	gpio_chip->direction_output = gpio_rcar_direction_output;
440 	gpio_chip->set = gpio_rcar_set;
441 	gpio_chip->label = name;
442 	gpio_chip->parent = dev;
443 	gpio_chip->owner = THIS_MODULE;
444 	gpio_chip->base = -1;
445 	gpio_chip->ngpio = npins;
446 
447 	irq_chip = &p->irq_chip;
448 	irq_chip->name = name;
449 	irq_chip->irq_mask = gpio_rcar_irq_disable;
450 	irq_chip->irq_unmask = gpio_rcar_irq_enable;
451 	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
452 	irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
453 	irq_chip->flags	= IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
454 
455 	ret = gpiochip_add_data(gpio_chip, p);
456 	if (ret) {
457 		dev_err(dev, "failed to add GPIO controller\n");
458 		goto err0;
459 	}
460 
461 	ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
462 				   IRQ_TYPE_NONE);
463 	if (ret) {
464 		dev_err(dev, "cannot add irqchip\n");
465 		goto err1;
466 	}
467 
468 	p->irq_parent = irq->start;
469 	if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
470 			     IRQF_SHARED, name, p)) {
471 		dev_err(dev, "failed to request IRQ\n");
472 		ret = -ENOENT;
473 		goto err1;
474 	}
475 
476 	dev_info(dev, "driving %d GPIOs\n", npins);
477 
478 	return 0;
479 
480 err1:
481 	gpiochip_remove(gpio_chip);
482 err0:
483 	pm_runtime_disable(dev);
484 	return ret;
485 }
486 
487 static int gpio_rcar_remove(struct platform_device *pdev)
488 {
489 	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
490 
491 	gpiochip_remove(&p->gpio_chip);
492 
493 	pm_runtime_disable(&pdev->dev);
494 	return 0;
495 }
496 
497 static struct platform_driver gpio_rcar_device_driver = {
498 	.probe		= gpio_rcar_probe,
499 	.remove		= gpio_rcar_remove,
500 	.driver		= {
501 		.name	= "gpio_rcar",
502 		.of_match_table = of_match_ptr(gpio_rcar_of_table),
503 	}
504 };
505 
506 module_platform_driver(gpio_rcar_device_driver);
507 
508 MODULE_AUTHOR("Magnus Damm");
509 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
510 MODULE_LICENSE("GPL v2");
511