1 /* 2 * Renesas R-Car GPIO Support 3 * 4 * Copyright (C) 2013 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/err.h> 17 #include <linux/gpio.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/ioport.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/platform_data/gpio-rcar.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/spinlock.h> 31 #include <linux/slab.h> 32 33 struct gpio_rcar_priv { 34 void __iomem *base; 35 spinlock_t lock; 36 struct gpio_rcar_config config; 37 struct platform_device *pdev; 38 struct gpio_chip gpio_chip; 39 struct irq_chip irq_chip; 40 struct irq_domain *irq_domain; 41 }; 42 43 #define IOINTSEL 0x00 44 #define INOUTSEL 0x04 45 #define OUTDT 0x08 46 #define INDT 0x0c 47 #define INTDT 0x10 48 #define INTCLR 0x14 49 #define INTMSK 0x18 50 #define MSKCLR 0x1c 51 #define POSNEG 0x20 52 #define EDGLEVEL 0x24 53 #define FILONOFF 0x28 54 #define BOTHEDGE 0x4c 55 56 #define RCAR_MAX_GPIO_PER_BANK 32 57 58 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs) 59 { 60 return ioread32(p->base + offs); 61 } 62 63 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs, 64 u32 value) 65 { 66 iowrite32(value, p->base + offs); 67 } 68 69 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs, 70 int bit, bool value) 71 { 72 u32 tmp = gpio_rcar_read(p, offs); 73 74 if (value) 75 tmp |= BIT(bit); 76 else 77 tmp &= ~BIT(bit); 78 79 gpio_rcar_write(p, offs, tmp); 80 } 81 82 static void gpio_rcar_irq_disable(struct irq_data *d) 83 { 84 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); 85 86 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d))); 87 } 88 89 static void gpio_rcar_irq_enable(struct irq_data *d) 90 { 91 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); 92 93 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d))); 94 } 95 96 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, 97 unsigned int hwirq, 98 bool active_high_rising_edge, 99 bool level_trigger, 100 bool both) 101 { 102 unsigned long flags; 103 104 /* follow steps in the GPIO documentation for 105 * "Setting Edge-Sensitive Interrupt Input Mode" and 106 * "Setting Level-Sensitive Interrupt Input Mode" 107 */ 108 109 spin_lock_irqsave(&p->lock, flags); 110 111 /* Configure postive or negative logic in POSNEG */ 112 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge); 113 114 /* Configure edge or level trigger in EDGLEVEL */ 115 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); 116 117 /* Select one edge or both edges in BOTHEDGE */ 118 if (p->config.has_both_edge_trigger) 119 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both); 120 121 /* Select "Interrupt Input Mode" in IOINTSEL */ 122 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); 123 124 /* Write INTCLR in case of edge trigger */ 125 if (!level_trigger) 126 gpio_rcar_write(p, INTCLR, BIT(hwirq)); 127 128 spin_unlock_irqrestore(&p->lock, flags); 129 } 130 131 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) 132 { 133 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); 134 unsigned int hwirq = irqd_to_hwirq(d); 135 136 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type); 137 138 switch (type & IRQ_TYPE_SENSE_MASK) { 139 case IRQ_TYPE_LEVEL_HIGH: 140 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true, 141 false); 142 break; 143 case IRQ_TYPE_LEVEL_LOW: 144 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true, 145 false); 146 break; 147 case IRQ_TYPE_EDGE_RISING: 148 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, 149 false); 150 break; 151 case IRQ_TYPE_EDGE_FALLING: 152 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false, 153 false); 154 break; 155 case IRQ_TYPE_EDGE_BOTH: 156 if (!p->config.has_both_edge_trigger) 157 return -EINVAL; 158 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, 159 true); 160 break; 161 default: 162 return -EINVAL; 163 } 164 return 0; 165 } 166 167 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) 168 { 169 struct gpio_rcar_priv *p = dev_id; 170 u32 pending; 171 unsigned int offset, irqs_handled = 0; 172 173 while ((pending = gpio_rcar_read(p, INTDT) & 174 gpio_rcar_read(p, INTMSK))) { 175 offset = __ffs(pending); 176 gpio_rcar_write(p, INTCLR, BIT(offset)); 177 generic_handle_irq(irq_find_mapping(p->irq_domain, offset)); 178 irqs_handled++; 179 } 180 181 return irqs_handled ? IRQ_HANDLED : IRQ_NONE; 182 } 183 184 static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip) 185 { 186 return container_of(chip, struct gpio_rcar_priv, gpio_chip); 187 } 188 189 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip, 190 unsigned int gpio, 191 bool output) 192 { 193 struct gpio_rcar_priv *p = gpio_to_priv(chip); 194 unsigned long flags; 195 196 /* follow steps in the GPIO documentation for 197 * "Setting General Output Mode" and 198 * "Setting General Input Mode" 199 */ 200 201 spin_lock_irqsave(&p->lock, flags); 202 203 /* Configure postive logic in POSNEG */ 204 gpio_rcar_modify_bit(p, POSNEG, gpio, false); 205 206 /* Select "General Input/Output Mode" in IOINTSEL */ 207 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false); 208 209 /* Select Input Mode or Output Mode in INOUTSEL */ 210 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output); 211 212 spin_unlock_irqrestore(&p->lock, flags); 213 } 214 215 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset) 216 { 217 return pinctrl_request_gpio(chip->base + offset); 218 } 219 220 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset) 221 { 222 pinctrl_free_gpio(chip->base + offset); 223 224 /* Set the GPIO as an input to ensure that the next GPIO request won't 225 * drive the GPIO pin as an output. 226 */ 227 gpio_rcar_config_general_input_output_mode(chip, offset, false); 228 } 229 230 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) 231 { 232 gpio_rcar_config_general_input_output_mode(chip, offset, false); 233 return 0; 234 } 235 236 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset) 237 { 238 u32 bit = BIT(offset); 239 240 /* testing on r8a7790 shows that INDT does not show correct pin state 241 * when configured as output, so use OUTDT in case of output pins */ 242 if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit) 243 return (int)(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit); 244 else 245 return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit); 246 } 247 248 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value) 249 { 250 struct gpio_rcar_priv *p = gpio_to_priv(chip); 251 unsigned long flags; 252 253 spin_lock_irqsave(&p->lock, flags); 254 gpio_rcar_modify_bit(p, OUTDT, offset, value); 255 spin_unlock_irqrestore(&p->lock, flags); 256 } 257 258 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset, 259 int value) 260 { 261 /* write GPIO value to output before selecting output mode of pin */ 262 gpio_rcar_set(chip, offset, value); 263 gpio_rcar_config_general_input_output_mode(chip, offset, true); 264 return 0; 265 } 266 267 static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset) 268 { 269 return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset); 270 } 271 272 static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int irq, 273 irq_hw_number_t hwirq) 274 { 275 struct gpio_rcar_priv *p = h->host_data; 276 277 dev_dbg(&p->pdev->dev, "map hw irq = %d, irq = %d\n", (int)hwirq, irq); 278 279 irq_set_chip_data(irq, h->host_data); 280 irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq); 281 set_irq_flags(irq, IRQF_VALID); /* kill me now */ 282 return 0; 283 } 284 285 static struct irq_domain_ops gpio_rcar_irq_domain_ops = { 286 .map = gpio_rcar_irq_domain_map, 287 }; 288 289 struct gpio_rcar_info { 290 bool has_both_edge_trigger; 291 }; 292 293 static const struct of_device_id gpio_rcar_of_table[] = { 294 { 295 .compatible = "renesas,gpio-r8a7790", 296 .data = (void *)&(const struct gpio_rcar_info) { 297 .has_both_edge_trigger = true, 298 }, 299 }, { 300 .compatible = "renesas,gpio-r8a7791", 301 .data = (void *)&(const struct gpio_rcar_info) { 302 .has_both_edge_trigger = true, 303 }, 304 }, { 305 .compatible = "renesas,gpio-rcar", 306 .data = (void *)&(const struct gpio_rcar_info) { 307 .has_both_edge_trigger = false, 308 }, 309 }, { 310 /* Terminator */ 311 }, 312 }; 313 314 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table); 315 316 static int gpio_rcar_parse_pdata(struct gpio_rcar_priv *p) 317 { 318 struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev); 319 struct device_node *np = p->pdev->dev.of_node; 320 struct of_phandle_args args; 321 int ret; 322 323 if (pdata) { 324 p->config = *pdata; 325 } else if (IS_ENABLED(CONFIG_OF) && np) { 326 const struct of_device_id *match; 327 const struct gpio_rcar_info *info; 328 329 match = of_match_node(gpio_rcar_of_table, np); 330 if (!match) 331 return -EINVAL; 332 333 info = match->data; 334 335 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, 336 &args); 337 p->config.number_of_pins = ret == 0 ? args.args[2] 338 : RCAR_MAX_GPIO_PER_BANK; 339 p->config.gpio_base = -1; 340 p->config.has_both_edge_trigger = info->has_both_edge_trigger; 341 } 342 343 if (p->config.number_of_pins == 0 || 344 p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) { 345 dev_warn(&p->pdev->dev, 346 "Invalid number of gpio lines %u, using %u\n", 347 p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK); 348 p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK; 349 } 350 351 return 0; 352 } 353 354 static int gpio_rcar_probe(struct platform_device *pdev) 355 { 356 struct gpio_rcar_priv *p; 357 struct resource *io, *irq; 358 struct gpio_chip *gpio_chip; 359 struct irq_chip *irq_chip; 360 struct device *dev = &pdev->dev; 361 const char *name = dev_name(dev); 362 int ret; 363 364 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); 365 if (!p) { 366 ret = -ENOMEM; 367 goto err0; 368 } 369 370 p->pdev = pdev; 371 spin_lock_init(&p->lock); 372 373 /* Get device configuration from DT node or platform data. */ 374 ret = gpio_rcar_parse_pdata(p); 375 if (ret < 0) 376 return ret; 377 378 platform_set_drvdata(pdev, p); 379 380 pm_runtime_enable(dev); 381 pm_runtime_get_sync(dev); 382 383 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 384 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 385 386 if (!io || !irq) { 387 dev_err(dev, "missing IRQ or IOMEM\n"); 388 ret = -EINVAL; 389 goto err0; 390 } 391 392 p->base = devm_ioremap_nocache(dev, io->start, resource_size(io)); 393 if (!p->base) { 394 dev_err(dev, "failed to remap I/O memory\n"); 395 ret = -ENXIO; 396 goto err0; 397 } 398 399 gpio_chip = &p->gpio_chip; 400 gpio_chip->request = gpio_rcar_request; 401 gpio_chip->free = gpio_rcar_free; 402 gpio_chip->direction_input = gpio_rcar_direction_input; 403 gpio_chip->get = gpio_rcar_get; 404 gpio_chip->direction_output = gpio_rcar_direction_output; 405 gpio_chip->set = gpio_rcar_set; 406 gpio_chip->to_irq = gpio_rcar_to_irq; 407 gpio_chip->label = name; 408 gpio_chip->dev = dev; 409 gpio_chip->owner = THIS_MODULE; 410 gpio_chip->base = p->config.gpio_base; 411 gpio_chip->ngpio = p->config.number_of_pins; 412 413 irq_chip = &p->irq_chip; 414 irq_chip->name = name; 415 irq_chip->irq_mask = gpio_rcar_irq_disable; 416 irq_chip->irq_unmask = gpio_rcar_irq_enable; 417 irq_chip->irq_set_type = gpio_rcar_irq_set_type; 418 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED 419 | IRQCHIP_MASK_ON_SUSPEND; 420 421 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, 422 p->config.number_of_pins, 423 p->config.irq_base, 424 &gpio_rcar_irq_domain_ops, p); 425 if (!p->irq_domain) { 426 ret = -ENXIO; 427 dev_err(dev, "cannot initialize irq domain\n"); 428 goto err0; 429 } 430 431 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler, 432 IRQF_SHARED, name, p)) { 433 dev_err(dev, "failed to request IRQ\n"); 434 ret = -ENOENT; 435 goto err1; 436 } 437 438 ret = gpiochip_add(gpio_chip); 439 if (ret) { 440 dev_err(dev, "failed to add GPIO controller\n"); 441 goto err1; 442 } 443 444 dev_info(dev, "driving %d GPIOs\n", p->config.number_of_pins); 445 446 /* warn in case of mismatch if irq base is specified */ 447 if (p->config.irq_base) { 448 ret = irq_find_mapping(p->irq_domain, 0); 449 if (p->config.irq_base != ret) 450 dev_warn(dev, "irq base mismatch (%u/%u)\n", 451 p->config.irq_base, ret); 452 } 453 454 if (p->config.pctl_name) { 455 ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0, 456 gpio_chip->base, gpio_chip->ngpio); 457 if (ret < 0) 458 dev_warn(dev, "failed to add pin range\n"); 459 } 460 461 return 0; 462 463 err1: 464 irq_domain_remove(p->irq_domain); 465 err0: 466 pm_runtime_put(dev); 467 pm_runtime_disable(dev); 468 return ret; 469 } 470 471 static int gpio_rcar_remove(struct platform_device *pdev) 472 { 473 struct gpio_rcar_priv *p = platform_get_drvdata(pdev); 474 int ret; 475 476 ret = gpiochip_remove(&p->gpio_chip); 477 if (ret) 478 return ret; 479 480 irq_domain_remove(p->irq_domain); 481 pm_runtime_put(&pdev->dev); 482 pm_runtime_disable(&pdev->dev); 483 return 0; 484 } 485 486 static struct platform_driver gpio_rcar_device_driver = { 487 .probe = gpio_rcar_probe, 488 .remove = gpio_rcar_remove, 489 .driver = { 490 .name = "gpio_rcar", 491 .of_match_table = of_match_ptr(gpio_rcar_of_table), 492 } 493 }; 494 495 module_platform_driver(gpio_rcar_device_driver); 496 497 MODULE_AUTHOR("Magnus Damm"); 498 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver"); 499 MODULE_LICENSE("GPL v2"); 500