1 /* 2 * Renesas R-Car GPIO Support 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * Copyright (C) 2013 Magnus Damm 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/err.h> 19 #include <linux/gpio.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/ioport.h> 24 #include <linux/irq.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/spinlock.h> 31 #include <linux/slab.h> 32 33 struct gpio_rcar_priv { 34 void __iomem *base; 35 spinlock_t lock; 36 struct platform_device *pdev; 37 struct gpio_chip gpio_chip; 38 struct irq_chip irq_chip; 39 struct clk *clk; 40 unsigned int irq_parent; 41 bool has_both_edge_trigger; 42 bool needs_clk; 43 }; 44 45 #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */ 46 #define INOUTSEL 0x04 /* General Input/Output Switching Register */ 47 #define OUTDT 0x08 /* General Output Register */ 48 #define INDT 0x0c /* General Input Register */ 49 #define INTDT 0x10 /* Interrupt Display Register */ 50 #define INTCLR 0x14 /* Interrupt Clear Register */ 51 #define INTMSK 0x18 /* Interrupt Mask Register */ 52 #define MSKCLR 0x1c /* Interrupt Mask Clear Register */ 53 #define POSNEG 0x20 /* Positive/Negative Logic Select Register */ 54 #define EDGLEVEL 0x24 /* Edge/level Select Register */ 55 #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */ 56 #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */ 57 58 #define RCAR_MAX_GPIO_PER_BANK 32 59 60 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs) 61 { 62 return ioread32(p->base + offs); 63 } 64 65 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs, 66 u32 value) 67 { 68 iowrite32(value, p->base + offs); 69 } 70 71 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs, 72 int bit, bool value) 73 { 74 u32 tmp = gpio_rcar_read(p, offs); 75 76 if (value) 77 tmp |= BIT(bit); 78 else 79 tmp &= ~BIT(bit); 80 81 gpio_rcar_write(p, offs, tmp); 82 } 83 84 static void gpio_rcar_irq_disable(struct irq_data *d) 85 { 86 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 87 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 88 89 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d))); 90 } 91 92 static void gpio_rcar_irq_enable(struct irq_data *d) 93 { 94 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 95 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 96 97 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d))); 98 } 99 100 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, 101 unsigned int hwirq, 102 bool active_high_rising_edge, 103 bool level_trigger, 104 bool both) 105 { 106 unsigned long flags; 107 108 /* follow steps in the GPIO documentation for 109 * "Setting Edge-Sensitive Interrupt Input Mode" and 110 * "Setting Level-Sensitive Interrupt Input Mode" 111 */ 112 113 spin_lock_irqsave(&p->lock, flags); 114 115 /* Configure postive or negative logic in POSNEG */ 116 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge); 117 118 /* Configure edge or level trigger in EDGLEVEL */ 119 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); 120 121 /* Select one edge or both edges in BOTHEDGE */ 122 if (p->has_both_edge_trigger) 123 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both); 124 125 /* Select "Interrupt Input Mode" in IOINTSEL */ 126 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); 127 128 /* Write INTCLR in case of edge trigger */ 129 if (!level_trigger) 130 gpio_rcar_write(p, INTCLR, BIT(hwirq)); 131 132 spin_unlock_irqrestore(&p->lock, flags); 133 } 134 135 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) 136 { 137 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 138 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 139 unsigned int hwirq = irqd_to_hwirq(d); 140 141 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type); 142 143 switch (type & IRQ_TYPE_SENSE_MASK) { 144 case IRQ_TYPE_LEVEL_HIGH: 145 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true, 146 false); 147 break; 148 case IRQ_TYPE_LEVEL_LOW: 149 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true, 150 false); 151 break; 152 case IRQ_TYPE_EDGE_RISING: 153 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, 154 false); 155 break; 156 case IRQ_TYPE_EDGE_FALLING: 157 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false, 158 false); 159 break; 160 case IRQ_TYPE_EDGE_BOTH: 161 if (!p->has_both_edge_trigger) 162 return -EINVAL; 163 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, 164 true); 165 break; 166 default: 167 return -EINVAL; 168 } 169 return 0; 170 } 171 172 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on) 173 { 174 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 175 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 176 int error; 177 178 if (p->irq_parent) { 179 error = irq_set_irq_wake(p->irq_parent, on); 180 if (error) { 181 dev_dbg(&p->pdev->dev, 182 "irq %u doesn't support irq_set_wake\n", 183 p->irq_parent); 184 p->irq_parent = 0; 185 } 186 } 187 188 if (!p->clk) 189 return 0; 190 191 if (on) 192 clk_enable(p->clk); 193 else 194 clk_disable(p->clk); 195 196 return 0; 197 } 198 199 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) 200 { 201 struct gpio_rcar_priv *p = dev_id; 202 u32 pending; 203 unsigned int offset, irqs_handled = 0; 204 205 while ((pending = gpio_rcar_read(p, INTDT) & 206 gpio_rcar_read(p, INTMSK))) { 207 offset = __ffs(pending); 208 gpio_rcar_write(p, INTCLR, BIT(offset)); 209 generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain, 210 offset)); 211 irqs_handled++; 212 } 213 214 return irqs_handled ? IRQ_HANDLED : IRQ_NONE; 215 } 216 217 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip, 218 unsigned int gpio, 219 bool output) 220 { 221 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 222 unsigned long flags; 223 224 /* follow steps in the GPIO documentation for 225 * "Setting General Output Mode" and 226 * "Setting General Input Mode" 227 */ 228 229 spin_lock_irqsave(&p->lock, flags); 230 231 /* Configure postive logic in POSNEG */ 232 gpio_rcar_modify_bit(p, POSNEG, gpio, false); 233 234 /* Select "General Input/Output Mode" in IOINTSEL */ 235 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false); 236 237 /* Select Input Mode or Output Mode in INOUTSEL */ 238 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output); 239 240 spin_unlock_irqrestore(&p->lock, flags); 241 } 242 243 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset) 244 { 245 return pinctrl_request_gpio(chip->base + offset); 246 } 247 248 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset) 249 { 250 pinctrl_free_gpio(chip->base + offset); 251 252 /* 253 * Set the GPIO as an input to ensure that the next GPIO request won't 254 * drive the GPIO pin as an output. 255 */ 256 gpio_rcar_config_general_input_output_mode(chip, offset, false); 257 } 258 259 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) 260 { 261 gpio_rcar_config_general_input_output_mode(chip, offset, false); 262 return 0; 263 } 264 265 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset) 266 { 267 u32 bit = BIT(offset); 268 269 /* testing on r8a7790 shows that INDT does not show correct pin state 270 * when configured as output, so use OUTDT in case of output pins */ 271 if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit) 272 return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit); 273 else 274 return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit); 275 } 276 277 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value) 278 { 279 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 280 unsigned long flags; 281 282 spin_lock_irqsave(&p->lock, flags); 283 gpio_rcar_modify_bit(p, OUTDT, offset, value); 284 spin_unlock_irqrestore(&p->lock, flags); 285 } 286 287 static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask, 288 unsigned long *bits) 289 { 290 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 291 unsigned long flags; 292 u32 val, bankmask; 293 294 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); 295 if (!bankmask) 296 return; 297 298 spin_lock_irqsave(&p->lock, flags); 299 val = gpio_rcar_read(p, OUTDT); 300 val &= ~bankmask; 301 val |= (bankmask & bits[0]); 302 gpio_rcar_write(p, OUTDT, val); 303 spin_unlock_irqrestore(&p->lock, flags); 304 } 305 306 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset, 307 int value) 308 { 309 /* write GPIO value to output before selecting output mode of pin */ 310 gpio_rcar_set(chip, offset, value); 311 gpio_rcar_config_general_input_output_mode(chip, offset, true); 312 return 0; 313 } 314 315 struct gpio_rcar_info { 316 bool has_both_edge_trigger; 317 bool needs_clk; 318 }; 319 320 static const struct gpio_rcar_info gpio_rcar_info_gen1 = { 321 .has_both_edge_trigger = false, 322 .needs_clk = false, 323 }; 324 325 static const struct gpio_rcar_info gpio_rcar_info_gen2 = { 326 .has_both_edge_trigger = true, 327 .needs_clk = true, 328 }; 329 330 static const struct of_device_id gpio_rcar_of_table[] = { 331 { 332 .compatible = "renesas,gpio-r8a7790", 333 .data = &gpio_rcar_info_gen2, 334 }, { 335 .compatible = "renesas,gpio-r8a7791", 336 .data = &gpio_rcar_info_gen2, 337 }, { 338 .compatible = "renesas,gpio-r8a7792", 339 .data = &gpio_rcar_info_gen2, 340 }, { 341 .compatible = "renesas,gpio-r8a7793", 342 .data = &gpio_rcar_info_gen2, 343 }, { 344 .compatible = "renesas,gpio-r8a7794", 345 .data = &gpio_rcar_info_gen2, 346 }, { 347 .compatible = "renesas,gpio-r8a7795", 348 /* Gen3 GPIO is identical to Gen2. */ 349 .data = &gpio_rcar_info_gen2, 350 }, { 351 .compatible = "renesas,gpio-r8a7796", 352 /* Gen3 GPIO is identical to Gen2. */ 353 .data = &gpio_rcar_info_gen2, 354 }, { 355 .compatible = "renesas,gpio-rcar", 356 .data = &gpio_rcar_info_gen1, 357 }, { 358 /* Terminator */ 359 }, 360 }; 361 362 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table); 363 364 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins) 365 { 366 struct device_node *np = p->pdev->dev.of_node; 367 const struct of_device_id *match; 368 const struct gpio_rcar_info *info; 369 struct of_phandle_args args; 370 int ret; 371 372 match = of_match_node(gpio_rcar_of_table, np); 373 if (!match) 374 return -EINVAL; 375 376 info = match->data; 377 378 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args); 379 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK; 380 p->has_both_edge_trigger = info->has_both_edge_trigger; 381 p->needs_clk = info->needs_clk; 382 383 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) { 384 dev_warn(&p->pdev->dev, 385 "Invalid number of gpio lines %u, using %u\n", *npins, 386 RCAR_MAX_GPIO_PER_BANK); 387 *npins = RCAR_MAX_GPIO_PER_BANK; 388 } 389 390 return 0; 391 } 392 393 static int gpio_rcar_probe(struct platform_device *pdev) 394 { 395 struct gpio_rcar_priv *p; 396 struct resource *io, *irq; 397 struct gpio_chip *gpio_chip; 398 struct irq_chip *irq_chip; 399 struct device *dev = &pdev->dev; 400 const char *name = dev_name(dev); 401 unsigned int npins; 402 int ret; 403 404 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); 405 if (!p) 406 return -ENOMEM; 407 408 p->pdev = pdev; 409 spin_lock_init(&p->lock); 410 411 /* Get device configuration from DT node */ 412 ret = gpio_rcar_parse_dt(p, &npins); 413 if (ret < 0) 414 return ret; 415 416 platform_set_drvdata(pdev, p); 417 418 p->clk = devm_clk_get(dev, NULL); 419 if (IS_ERR(p->clk)) { 420 if (p->needs_clk) { 421 dev_err(dev, "unable to get clock\n"); 422 ret = PTR_ERR(p->clk); 423 goto err0; 424 } 425 p->clk = NULL; 426 } 427 428 pm_runtime_enable(dev); 429 pm_runtime_get_sync(dev); 430 431 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 432 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 433 434 if (!io || !irq) { 435 dev_err(dev, "missing IRQ or IOMEM\n"); 436 ret = -EINVAL; 437 goto err0; 438 } 439 440 p->base = devm_ioremap_nocache(dev, io->start, resource_size(io)); 441 if (!p->base) { 442 dev_err(dev, "failed to remap I/O memory\n"); 443 ret = -ENXIO; 444 goto err0; 445 } 446 447 gpio_chip = &p->gpio_chip; 448 gpio_chip->request = gpio_rcar_request; 449 gpio_chip->free = gpio_rcar_free; 450 gpio_chip->direction_input = gpio_rcar_direction_input; 451 gpio_chip->get = gpio_rcar_get; 452 gpio_chip->direction_output = gpio_rcar_direction_output; 453 gpio_chip->set = gpio_rcar_set; 454 gpio_chip->set_multiple = gpio_rcar_set_multiple; 455 gpio_chip->label = name; 456 gpio_chip->parent = dev; 457 gpio_chip->owner = THIS_MODULE; 458 gpio_chip->base = -1; 459 gpio_chip->ngpio = npins; 460 461 irq_chip = &p->irq_chip; 462 irq_chip->name = name; 463 irq_chip->irq_mask = gpio_rcar_irq_disable; 464 irq_chip->irq_unmask = gpio_rcar_irq_enable; 465 irq_chip->irq_set_type = gpio_rcar_irq_set_type; 466 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake; 467 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND; 468 469 ret = gpiochip_add_data(gpio_chip, p); 470 if (ret) { 471 dev_err(dev, "failed to add GPIO controller\n"); 472 goto err0; 473 } 474 475 ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq, 476 IRQ_TYPE_NONE); 477 if (ret) { 478 dev_err(dev, "cannot add irqchip\n"); 479 goto err1; 480 } 481 482 p->irq_parent = irq->start; 483 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler, 484 IRQF_SHARED, name, p)) { 485 dev_err(dev, "failed to request IRQ\n"); 486 ret = -ENOENT; 487 goto err1; 488 } 489 490 dev_info(dev, "driving %d GPIOs\n", npins); 491 492 return 0; 493 494 err1: 495 gpiochip_remove(gpio_chip); 496 err0: 497 pm_runtime_put(dev); 498 pm_runtime_disable(dev); 499 return ret; 500 } 501 502 static int gpio_rcar_remove(struct platform_device *pdev) 503 { 504 struct gpio_rcar_priv *p = platform_get_drvdata(pdev); 505 506 gpiochip_remove(&p->gpio_chip); 507 508 pm_runtime_put(&pdev->dev); 509 pm_runtime_disable(&pdev->dev); 510 return 0; 511 } 512 513 static struct platform_driver gpio_rcar_device_driver = { 514 .probe = gpio_rcar_probe, 515 .remove = gpio_rcar_remove, 516 .driver = { 517 .name = "gpio_rcar", 518 .of_match_table = of_match_ptr(gpio_rcar_of_table), 519 } 520 }; 521 522 module_platform_driver(gpio_rcar_device_driver); 523 524 MODULE_AUTHOR("Magnus Damm"); 525 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver"); 526 MODULE_LICENSE("GPL v2"); 527