1119f5e44SMagnus Damm /* 2119f5e44SMagnus Damm * Renesas R-Car GPIO Support 3119f5e44SMagnus Damm * 4119f5e44SMagnus Damm * Copyright (C) 2013 Magnus Damm 5119f5e44SMagnus Damm * 6119f5e44SMagnus Damm * This program is free software; you can redistribute it and/or modify 7119f5e44SMagnus Damm * it under the terms of the GNU General Public License as published by 8119f5e44SMagnus Damm * the Free Software Foundation; either version 2 of the License 9119f5e44SMagnus Damm * 10119f5e44SMagnus Damm * This program is distributed in the hope that it will be useful, 11119f5e44SMagnus Damm * but WITHOUT ANY WARRANTY; without even the implied warranty of 12119f5e44SMagnus Damm * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13119f5e44SMagnus Damm * GNU General Public License for more details. 14119f5e44SMagnus Damm */ 15119f5e44SMagnus Damm 16119f5e44SMagnus Damm #include <linux/err.h> 17119f5e44SMagnus Damm #include <linux/gpio.h> 18119f5e44SMagnus Damm #include <linux/init.h> 19119f5e44SMagnus Damm #include <linux/interrupt.h> 20119f5e44SMagnus Damm #include <linux/io.h> 21119f5e44SMagnus Damm #include <linux/ioport.h> 22119f5e44SMagnus Damm #include <linux/irq.h> 23119f5e44SMagnus Damm #include <linux/irqdomain.h> 24119f5e44SMagnus Damm #include <linux/module.h> 25dc3465a9SLaurent Pinchart #include <linux/pinctrl/consumer.h> 26119f5e44SMagnus Damm #include <linux/platform_data/gpio-rcar.h> 27119f5e44SMagnus Damm #include <linux/platform_device.h> 28119f5e44SMagnus Damm #include <linux/spinlock.h> 29119f5e44SMagnus Damm #include <linux/slab.h> 30119f5e44SMagnus Damm 31119f5e44SMagnus Damm struct gpio_rcar_priv { 32119f5e44SMagnus Damm void __iomem *base; 33119f5e44SMagnus Damm spinlock_t lock; 34119f5e44SMagnus Damm struct gpio_rcar_config config; 35119f5e44SMagnus Damm struct platform_device *pdev; 36119f5e44SMagnus Damm struct gpio_chip gpio_chip; 37119f5e44SMagnus Damm struct irq_chip irq_chip; 38119f5e44SMagnus Damm struct irq_domain *irq_domain; 39119f5e44SMagnus Damm }; 40119f5e44SMagnus Damm 41119f5e44SMagnus Damm #define IOINTSEL 0x00 42119f5e44SMagnus Damm #define INOUTSEL 0x04 43119f5e44SMagnus Damm #define OUTDT 0x08 44119f5e44SMagnus Damm #define INDT 0x0c 45119f5e44SMagnus Damm #define INTDT 0x10 46119f5e44SMagnus Damm #define INTCLR 0x14 47119f5e44SMagnus Damm #define INTMSK 0x18 48119f5e44SMagnus Damm #define MSKCLR 0x1c 49119f5e44SMagnus Damm #define POSNEG 0x20 50119f5e44SMagnus Damm #define EDGLEVEL 0x24 51119f5e44SMagnus Damm #define FILONOFF 0x28 52119f5e44SMagnus Damm 53119f5e44SMagnus Damm static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs) 54119f5e44SMagnus Damm { 55119f5e44SMagnus Damm return ioread32(p->base + offs); 56119f5e44SMagnus Damm } 57119f5e44SMagnus Damm 58119f5e44SMagnus Damm static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs, 59119f5e44SMagnus Damm u32 value) 60119f5e44SMagnus Damm { 61119f5e44SMagnus Damm iowrite32(value, p->base + offs); 62119f5e44SMagnus Damm } 63119f5e44SMagnus Damm 64119f5e44SMagnus Damm static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs, 65119f5e44SMagnus Damm int bit, bool value) 66119f5e44SMagnus Damm { 67119f5e44SMagnus Damm u32 tmp = gpio_rcar_read(p, offs); 68119f5e44SMagnus Damm 69119f5e44SMagnus Damm if (value) 70119f5e44SMagnus Damm tmp |= BIT(bit); 71119f5e44SMagnus Damm else 72119f5e44SMagnus Damm tmp &= ~BIT(bit); 73119f5e44SMagnus Damm 74119f5e44SMagnus Damm gpio_rcar_write(p, offs, tmp); 75119f5e44SMagnus Damm } 76119f5e44SMagnus Damm 77119f5e44SMagnus Damm static void gpio_rcar_irq_disable(struct irq_data *d) 78119f5e44SMagnus Damm { 79119f5e44SMagnus Damm struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); 80119f5e44SMagnus Damm 81119f5e44SMagnus Damm gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d))); 82119f5e44SMagnus Damm } 83119f5e44SMagnus Damm 84119f5e44SMagnus Damm static void gpio_rcar_irq_enable(struct irq_data *d) 85119f5e44SMagnus Damm { 86119f5e44SMagnus Damm struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); 87119f5e44SMagnus Damm 88119f5e44SMagnus Damm gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d))); 89119f5e44SMagnus Damm } 90119f5e44SMagnus Damm 91119f5e44SMagnus Damm static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, 92119f5e44SMagnus Damm unsigned int hwirq, 93119f5e44SMagnus Damm bool active_high_rising_edge, 94119f5e44SMagnus Damm bool level_trigger) 95119f5e44SMagnus Damm { 96119f5e44SMagnus Damm unsigned long flags; 97119f5e44SMagnus Damm 98119f5e44SMagnus Damm /* follow steps in the GPIO documentation for 99119f5e44SMagnus Damm * "Setting Edge-Sensitive Interrupt Input Mode" and 100119f5e44SMagnus Damm * "Setting Level-Sensitive Interrupt Input Mode" 101119f5e44SMagnus Damm */ 102119f5e44SMagnus Damm 103119f5e44SMagnus Damm spin_lock_irqsave(&p->lock, flags); 104119f5e44SMagnus Damm 105119f5e44SMagnus Damm /* Configure postive or negative logic in POSNEG */ 106119f5e44SMagnus Damm gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge); 107119f5e44SMagnus Damm 108119f5e44SMagnus Damm /* Configure edge or level trigger in EDGLEVEL */ 109119f5e44SMagnus Damm gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); 110119f5e44SMagnus Damm 111119f5e44SMagnus Damm /* Select "Interrupt Input Mode" in IOINTSEL */ 112119f5e44SMagnus Damm gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); 113119f5e44SMagnus Damm 114119f5e44SMagnus Damm /* Write INTCLR in case of edge trigger */ 115119f5e44SMagnus Damm if (!level_trigger) 116119f5e44SMagnus Damm gpio_rcar_write(p, INTCLR, BIT(hwirq)); 117119f5e44SMagnus Damm 118119f5e44SMagnus Damm spin_unlock_irqrestore(&p->lock, flags); 119119f5e44SMagnus Damm } 120119f5e44SMagnus Damm 121119f5e44SMagnus Damm static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) 122119f5e44SMagnus Damm { 123119f5e44SMagnus Damm struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); 124119f5e44SMagnus Damm unsigned int hwirq = irqd_to_hwirq(d); 125119f5e44SMagnus Damm 126119f5e44SMagnus Damm dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type); 127119f5e44SMagnus Damm 128119f5e44SMagnus Damm switch (type & IRQ_TYPE_SENSE_MASK) { 129119f5e44SMagnus Damm case IRQ_TYPE_LEVEL_HIGH: 130119f5e44SMagnus Damm gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true); 131119f5e44SMagnus Damm break; 132119f5e44SMagnus Damm case IRQ_TYPE_LEVEL_LOW: 133119f5e44SMagnus Damm gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true); 134119f5e44SMagnus Damm break; 135119f5e44SMagnus Damm case IRQ_TYPE_EDGE_RISING: 136119f5e44SMagnus Damm gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false); 137119f5e44SMagnus Damm break; 138119f5e44SMagnus Damm case IRQ_TYPE_EDGE_FALLING: 139119f5e44SMagnus Damm gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false); 140119f5e44SMagnus Damm break; 141119f5e44SMagnus Damm default: 142119f5e44SMagnus Damm return -EINVAL; 143119f5e44SMagnus Damm } 144119f5e44SMagnus Damm return 0; 145119f5e44SMagnus Damm } 146119f5e44SMagnus Damm 147119f5e44SMagnus Damm static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) 148119f5e44SMagnus Damm { 149119f5e44SMagnus Damm struct gpio_rcar_priv *p = dev_id; 150119f5e44SMagnus Damm u32 pending; 151119f5e44SMagnus Damm unsigned int offset, irqs_handled = 0; 152119f5e44SMagnus Damm 153119f5e44SMagnus Damm while ((pending = gpio_rcar_read(p, INTDT))) { 154119f5e44SMagnus Damm offset = __ffs(pending); 155119f5e44SMagnus Damm gpio_rcar_write(p, INTCLR, BIT(offset)); 156119f5e44SMagnus Damm generic_handle_irq(irq_find_mapping(p->irq_domain, offset)); 157119f5e44SMagnus Damm irqs_handled++; 158119f5e44SMagnus Damm } 159119f5e44SMagnus Damm 160119f5e44SMagnus Damm return irqs_handled ? IRQ_HANDLED : IRQ_NONE; 161119f5e44SMagnus Damm } 162119f5e44SMagnus Damm 163119f5e44SMagnus Damm static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip) 164119f5e44SMagnus Damm { 165119f5e44SMagnus Damm return container_of(chip, struct gpio_rcar_priv, gpio_chip); 166119f5e44SMagnus Damm } 167119f5e44SMagnus Damm 168119f5e44SMagnus Damm static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip, 169119f5e44SMagnus Damm unsigned int gpio, 170119f5e44SMagnus Damm bool output) 171119f5e44SMagnus Damm { 172119f5e44SMagnus Damm struct gpio_rcar_priv *p = gpio_to_priv(chip); 173119f5e44SMagnus Damm unsigned long flags; 174119f5e44SMagnus Damm 175119f5e44SMagnus Damm /* follow steps in the GPIO documentation for 176119f5e44SMagnus Damm * "Setting General Output Mode" and 177119f5e44SMagnus Damm * "Setting General Input Mode" 178119f5e44SMagnus Damm */ 179119f5e44SMagnus Damm 180119f5e44SMagnus Damm spin_lock_irqsave(&p->lock, flags); 181119f5e44SMagnus Damm 182119f5e44SMagnus Damm /* Configure postive logic in POSNEG */ 183119f5e44SMagnus Damm gpio_rcar_modify_bit(p, POSNEG, gpio, false); 184119f5e44SMagnus Damm 185119f5e44SMagnus Damm /* Select "General Input/Output Mode" in IOINTSEL */ 186119f5e44SMagnus Damm gpio_rcar_modify_bit(p, IOINTSEL, gpio, false); 187119f5e44SMagnus Damm 188119f5e44SMagnus Damm /* Select Input Mode or Output Mode in INOUTSEL */ 189119f5e44SMagnus Damm gpio_rcar_modify_bit(p, INOUTSEL, gpio, output); 190119f5e44SMagnus Damm 191119f5e44SMagnus Damm spin_unlock_irqrestore(&p->lock, flags); 192119f5e44SMagnus Damm } 193119f5e44SMagnus Damm 194dc3465a9SLaurent Pinchart static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset) 195dc3465a9SLaurent Pinchart { 196dc3465a9SLaurent Pinchart return pinctrl_request_gpio(chip->base + offset); 197dc3465a9SLaurent Pinchart } 198dc3465a9SLaurent Pinchart 199dc3465a9SLaurent Pinchart static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset) 200dc3465a9SLaurent Pinchart { 201dc3465a9SLaurent Pinchart pinctrl_free_gpio(chip->base + offset); 202dc3465a9SLaurent Pinchart 203dc3465a9SLaurent Pinchart /* Set the GPIO as an input to ensure that the next GPIO request won't 204dc3465a9SLaurent Pinchart * drive the GPIO pin as an output. 205dc3465a9SLaurent Pinchart */ 206dc3465a9SLaurent Pinchart gpio_rcar_config_general_input_output_mode(chip, offset, false); 207dc3465a9SLaurent Pinchart } 208dc3465a9SLaurent Pinchart 209119f5e44SMagnus Damm static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) 210119f5e44SMagnus Damm { 211119f5e44SMagnus Damm gpio_rcar_config_general_input_output_mode(chip, offset, false); 212119f5e44SMagnus Damm return 0; 213119f5e44SMagnus Damm } 214119f5e44SMagnus Damm 215119f5e44SMagnus Damm static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset) 216119f5e44SMagnus Damm { 217119f5e44SMagnus Damm return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & BIT(offset)); 218119f5e44SMagnus Damm } 219119f5e44SMagnus Damm 220119f5e44SMagnus Damm static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value) 221119f5e44SMagnus Damm { 222119f5e44SMagnus Damm struct gpio_rcar_priv *p = gpio_to_priv(chip); 223119f5e44SMagnus Damm unsigned long flags; 224119f5e44SMagnus Damm 225119f5e44SMagnus Damm spin_lock_irqsave(&p->lock, flags); 226119f5e44SMagnus Damm gpio_rcar_modify_bit(p, OUTDT, offset, value); 227119f5e44SMagnus Damm spin_unlock_irqrestore(&p->lock, flags); 228119f5e44SMagnus Damm } 229119f5e44SMagnus Damm 230119f5e44SMagnus Damm static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset, 231119f5e44SMagnus Damm int value) 232119f5e44SMagnus Damm { 233119f5e44SMagnus Damm /* write GPIO value to output before selecting output mode of pin */ 234119f5e44SMagnus Damm gpio_rcar_set(chip, offset, value); 235119f5e44SMagnus Damm gpio_rcar_config_general_input_output_mode(chip, offset, true); 236119f5e44SMagnus Damm return 0; 237119f5e44SMagnus Damm } 238119f5e44SMagnus Damm 239119f5e44SMagnus Damm static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset) 240119f5e44SMagnus Damm { 241119f5e44SMagnus Damm return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset); 242119f5e44SMagnus Damm } 243119f5e44SMagnus Damm 244119f5e44SMagnus Damm static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int virq, 245119f5e44SMagnus Damm irq_hw_number_t hw) 246119f5e44SMagnus Damm { 247119f5e44SMagnus Damm struct gpio_rcar_priv *p = h->host_data; 248119f5e44SMagnus Damm 249119f5e44SMagnus Damm dev_dbg(&p->pdev->dev, "map hw irq = %d, virq = %d\n", (int)hw, virq); 250119f5e44SMagnus Damm 251119f5e44SMagnus Damm irq_set_chip_data(virq, h->host_data); 252119f5e44SMagnus Damm irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); 253119f5e44SMagnus Damm set_irq_flags(virq, IRQF_VALID); /* kill me now */ 254119f5e44SMagnus Damm return 0; 255119f5e44SMagnus Damm } 256119f5e44SMagnus Damm 257119f5e44SMagnus Damm static struct irq_domain_ops gpio_rcar_irq_domain_ops = { 258119f5e44SMagnus Damm .map = gpio_rcar_irq_domain_map, 259119f5e44SMagnus Damm }; 260119f5e44SMagnus Damm 261119f5e44SMagnus Damm static int gpio_rcar_probe(struct platform_device *pdev) 262119f5e44SMagnus Damm { 263119f5e44SMagnus Damm struct gpio_rcar_config *pdata = pdev->dev.platform_data; 264119f5e44SMagnus Damm struct gpio_rcar_priv *p; 265119f5e44SMagnus Damm struct resource *io, *irq; 266119f5e44SMagnus Damm struct gpio_chip *gpio_chip; 267119f5e44SMagnus Damm struct irq_chip *irq_chip; 268119f5e44SMagnus Damm const char *name = dev_name(&pdev->dev); 269119f5e44SMagnus Damm int ret; 270119f5e44SMagnus Damm 271119f5e44SMagnus Damm p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); 272119f5e44SMagnus Damm if (!p) { 273119f5e44SMagnus Damm dev_err(&pdev->dev, "failed to allocate driver data\n"); 274119f5e44SMagnus Damm ret = -ENOMEM; 275119f5e44SMagnus Damm goto err0; 276119f5e44SMagnus Damm } 277119f5e44SMagnus Damm 278119f5e44SMagnus Damm /* deal with driver instance configuration */ 279119f5e44SMagnus Damm if (pdata) 280119f5e44SMagnus Damm p->config = *pdata; 281119f5e44SMagnus Damm 282119f5e44SMagnus Damm p->pdev = pdev; 283119f5e44SMagnus Damm platform_set_drvdata(pdev, p); 284119f5e44SMagnus Damm spin_lock_init(&p->lock); 285119f5e44SMagnus Damm 286119f5e44SMagnus Damm io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 287119f5e44SMagnus Damm irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 288119f5e44SMagnus Damm 289119f5e44SMagnus Damm if (!io || !irq) { 290119f5e44SMagnus Damm dev_err(&pdev->dev, "missing IRQ or IOMEM\n"); 291119f5e44SMagnus Damm ret = -EINVAL; 292119f5e44SMagnus Damm goto err0; 293119f5e44SMagnus Damm } 294119f5e44SMagnus Damm 295119f5e44SMagnus Damm p->base = devm_ioremap_nocache(&pdev->dev, io->start, 296119f5e44SMagnus Damm resource_size(io)); 297119f5e44SMagnus Damm if (!p->base) { 298119f5e44SMagnus Damm dev_err(&pdev->dev, "failed to remap I/O memory\n"); 299119f5e44SMagnus Damm ret = -ENXIO; 300119f5e44SMagnus Damm goto err0; 301119f5e44SMagnus Damm } 302119f5e44SMagnus Damm 303119f5e44SMagnus Damm gpio_chip = &p->gpio_chip; 304dc3465a9SLaurent Pinchart gpio_chip->request = gpio_rcar_request; 305dc3465a9SLaurent Pinchart gpio_chip->free = gpio_rcar_free; 306119f5e44SMagnus Damm gpio_chip->direction_input = gpio_rcar_direction_input; 307119f5e44SMagnus Damm gpio_chip->get = gpio_rcar_get; 308119f5e44SMagnus Damm gpio_chip->direction_output = gpio_rcar_direction_output; 309119f5e44SMagnus Damm gpio_chip->set = gpio_rcar_set; 310119f5e44SMagnus Damm gpio_chip->to_irq = gpio_rcar_to_irq; 311119f5e44SMagnus Damm gpio_chip->label = name; 312119f5e44SMagnus Damm gpio_chip->owner = THIS_MODULE; 313119f5e44SMagnus Damm gpio_chip->base = p->config.gpio_base; 314119f5e44SMagnus Damm gpio_chip->ngpio = p->config.number_of_pins; 315119f5e44SMagnus Damm 316119f5e44SMagnus Damm irq_chip = &p->irq_chip; 317119f5e44SMagnus Damm irq_chip->name = name; 318119f5e44SMagnus Damm irq_chip->irq_mask = gpio_rcar_irq_disable; 319119f5e44SMagnus Damm irq_chip->irq_unmask = gpio_rcar_irq_enable; 320119f5e44SMagnus Damm irq_chip->irq_enable = gpio_rcar_irq_enable; 321119f5e44SMagnus Damm irq_chip->irq_disable = gpio_rcar_irq_disable; 322119f5e44SMagnus Damm irq_chip->irq_set_type = gpio_rcar_irq_set_type; 323119f5e44SMagnus Damm irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED; 324119f5e44SMagnus Damm 325119f5e44SMagnus Damm p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, 326119f5e44SMagnus Damm p->config.number_of_pins, 327119f5e44SMagnus Damm p->config.irq_base, 328119f5e44SMagnus Damm &gpio_rcar_irq_domain_ops, p); 329119f5e44SMagnus Damm if (!p->irq_domain) { 330119f5e44SMagnus Damm ret = -ENXIO; 331119f5e44SMagnus Damm dev_err(&pdev->dev, "cannot initialize irq domain\n"); 332119f5e44SMagnus Damm goto err1; 333119f5e44SMagnus Damm } 334119f5e44SMagnus Damm 335119f5e44SMagnus Damm if (devm_request_irq(&pdev->dev, irq->start, 336c234962bSKuninori Morimoto gpio_rcar_irq_handler, IRQF_SHARED, name, p)) { 337119f5e44SMagnus Damm dev_err(&pdev->dev, "failed to request IRQ\n"); 338119f5e44SMagnus Damm ret = -ENOENT; 339119f5e44SMagnus Damm goto err1; 340119f5e44SMagnus Damm } 341119f5e44SMagnus Damm 342119f5e44SMagnus Damm ret = gpiochip_add(gpio_chip); 343119f5e44SMagnus Damm if (ret) { 344119f5e44SMagnus Damm dev_err(&pdev->dev, "failed to add GPIO controller\n"); 345119f5e44SMagnus Damm goto err1; 346119f5e44SMagnus Damm } 347119f5e44SMagnus Damm 348119f5e44SMagnus Damm dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins); 349119f5e44SMagnus Damm 350119f5e44SMagnus Damm /* warn in case of mismatch if irq base is specified */ 351119f5e44SMagnus Damm if (p->config.irq_base) { 352119f5e44SMagnus Damm ret = irq_find_mapping(p->irq_domain, 0); 353119f5e44SMagnus Damm if (p->config.irq_base != ret) 354119f5e44SMagnus Damm dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n", 355119f5e44SMagnus Damm p->config.irq_base, ret); 356119f5e44SMagnus Damm } 357119f5e44SMagnus Damm 358dc3465a9SLaurent Pinchart ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0, 359dc3465a9SLaurent Pinchart gpio_chip->base, gpio_chip->ngpio); 360dc3465a9SLaurent Pinchart if (ret < 0) 361dc3465a9SLaurent Pinchart dev_warn(&pdev->dev, "failed to add pin range\n"); 362dc3465a9SLaurent Pinchart 363119f5e44SMagnus Damm return 0; 364119f5e44SMagnus Damm 365119f5e44SMagnus Damm err1: 366119f5e44SMagnus Damm irq_domain_remove(p->irq_domain); 367119f5e44SMagnus Damm err0: 368119f5e44SMagnus Damm return ret; 369119f5e44SMagnus Damm } 370119f5e44SMagnus Damm 371119f5e44SMagnus Damm static int gpio_rcar_remove(struct platform_device *pdev) 372119f5e44SMagnus Damm { 373119f5e44SMagnus Damm struct gpio_rcar_priv *p = platform_get_drvdata(pdev); 374119f5e44SMagnus Damm int ret; 375119f5e44SMagnus Damm 376119f5e44SMagnus Damm ret = gpiochip_remove(&p->gpio_chip); 377119f5e44SMagnus Damm if (ret) 378119f5e44SMagnus Damm return ret; 379119f5e44SMagnus Damm 380119f5e44SMagnus Damm irq_domain_remove(p->irq_domain); 381119f5e44SMagnus Damm return 0; 382119f5e44SMagnus Damm } 383119f5e44SMagnus Damm 384119f5e44SMagnus Damm static struct platform_driver gpio_rcar_device_driver = { 385119f5e44SMagnus Damm .probe = gpio_rcar_probe, 386119f5e44SMagnus Damm .remove = gpio_rcar_remove, 387119f5e44SMagnus Damm .driver = { 388119f5e44SMagnus Damm .name = "gpio_rcar", 389119f5e44SMagnus Damm } 390119f5e44SMagnus Damm }; 391119f5e44SMagnus Damm 392119f5e44SMagnus Damm module_platform_driver(gpio_rcar_device_driver); 393119f5e44SMagnus Damm 394119f5e44SMagnus Damm MODULE_AUTHOR("Magnus Damm"); 395119f5e44SMagnus Damm MODULE_DESCRIPTION("Renesas R-Car GPIO Driver"); 396119f5e44SMagnus Damm MODULE_LICENSE("GPL v2"); 397