1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/plat-pxa/gpio.c 4 * 5 * Generic PXA GPIO handling 6 * 7 * Author: Nicolas Pitre 8 * Created: Jun 15, 2001 9 * Copyright: MontaVista Software Inc. 10 */ 11 #include <linux/module.h> 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/gpio-pxa.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/irq.h> 19 #include <linux/irqdomain.h> 20 #include <linux/irqchip/chained_irq.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/syscore_ops.h> 27 #include <linux/slab.h> 28 29 /* 30 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with 31 * one set of registers. The register offsets are organized below: 32 * 33 * GPLR GPDR GPSR GPCR GRER GFER GEDR 34 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 35 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C 36 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 37 * 38 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 39 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C 40 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 41 * 42 * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248 43 * 44 * NOTE: 45 * BANK 3 is only available on PXA27x and later processors. 46 * BANK 4 and 5 are only available on PXA935, PXA1928 47 * BANK 6 is only available on PXA1928 48 */ 49 50 #define GPLR_OFFSET 0x00 51 #define GPDR_OFFSET 0x0C 52 #define GPSR_OFFSET 0x18 53 #define GPCR_OFFSET 0x24 54 #define GRER_OFFSET 0x30 55 #define GFER_OFFSET 0x3C 56 #define GEDR_OFFSET 0x48 57 #define GAFR_OFFSET 0x54 58 #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */ 59 60 #define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2) 61 62 int pxa_last_gpio; 63 static int irq_base; 64 65 struct pxa_gpio_bank { 66 void __iomem *regbase; 67 unsigned long irq_mask; 68 unsigned long irq_edge_rise; 69 unsigned long irq_edge_fall; 70 71 #ifdef CONFIG_PM 72 unsigned long saved_gplr; 73 unsigned long saved_gpdr; 74 unsigned long saved_grer; 75 unsigned long saved_gfer; 76 #endif 77 }; 78 79 struct pxa_gpio_chip { 80 struct device *dev; 81 struct gpio_chip chip; 82 struct pxa_gpio_bank *banks; 83 struct irq_domain *irqdomain; 84 85 int irq0; 86 int irq1; 87 int (*set_wake)(unsigned int gpio, unsigned int on); 88 }; 89 90 enum pxa_gpio_type { 91 PXA25X_GPIO = 0, 92 PXA26X_GPIO, 93 PXA27X_GPIO, 94 PXA3XX_GPIO, 95 PXA93X_GPIO, 96 MMP_GPIO = 0x10, 97 MMP2_GPIO, 98 PXA1928_GPIO, 99 }; 100 101 struct pxa_gpio_id { 102 enum pxa_gpio_type type; 103 int gpio_nums; 104 }; 105 106 static DEFINE_SPINLOCK(gpio_lock); 107 static struct pxa_gpio_chip *pxa_gpio_chip; 108 static enum pxa_gpio_type gpio_type; 109 110 static struct pxa_gpio_id pxa25x_id = { 111 .type = PXA25X_GPIO, 112 .gpio_nums = 85, 113 }; 114 115 static struct pxa_gpio_id pxa26x_id = { 116 .type = PXA26X_GPIO, 117 .gpio_nums = 90, 118 }; 119 120 static struct pxa_gpio_id pxa27x_id = { 121 .type = PXA27X_GPIO, 122 .gpio_nums = 121, 123 }; 124 125 static struct pxa_gpio_id pxa3xx_id = { 126 .type = PXA3XX_GPIO, 127 .gpio_nums = 128, 128 }; 129 130 static struct pxa_gpio_id pxa93x_id = { 131 .type = PXA93X_GPIO, 132 .gpio_nums = 192, 133 }; 134 135 static struct pxa_gpio_id mmp_id = { 136 .type = MMP_GPIO, 137 .gpio_nums = 128, 138 }; 139 140 static struct pxa_gpio_id mmp2_id = { 141 .type = MMP2_GPIO, 142 .gpio_nums = 192, 143 }; 144 145 static struct pxa_gpio_id pxa1928_id = { 146 .type = PXA1928_GPIO, 147 .gpio_nums = 224, 148 }; 149 150 #define for_each_gpio_bank(i, b, pc) \ 151 for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++) 152 153 static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c) 154 { 155 struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c); 156 157 return pxa_chip; 158 } 159 160 static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio) 161 { 162 struct pxa_gpio_chip *p = gpiochip_get_data(c); 163 struct pxa_gpio_bank *bank = p->banks + (gpio / 32); 164 165 return bank->regbase; 166 } 167 168 static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c, 169 unsigned gpio) 170 { 171 return chip_to_pxachip(c)->banks + gpio / 32; 172 } 173 174 static inline int gpio_is_pxa_type(int type) 175 { 176 return (type & MMP_GPIO) == 0; 177 } 178 179 static inline int gpio_is_mmp_type(int type) 180 { 181 return (type & MMP_GPIO) != 0; 182 } 183 184 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, 185 * as well as their Alternate Function value being '1' for GPIO in GAFRx. 186 */ 187 static inline int __gpio_is_inverted(int gpio) 188 { 189 if ((gpio_type == PXA26X_GPIO) && (gpio > 85)) 190 return 1; 191 return 0; 192 } 193 194 /* 195 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate 196 * function of a GPIO, and GPDRx cannot be altered once configured. It 197 * is attributed as "occupied" here (I know this terminology isn't 198 * accurate, you are welcome to propose a better one :-) 199 */ 200 static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio) 201 { 202 void __iomem *base; 203 unsigned long gafr = 0, gpdr = 0; 204 int ret, af = 0, dir = 0; 205 206 base = gpio_bank_base(&pchip->chip, gpio); 207 gpdr = readl_relaxed(base + GPDR_OFFSET); 208 209 switch (gpio_type) { 210 case PXA25X_GPIO: 211 case PXA26X_GPIO: 212 case PXA27X_GPIO: 213 gafr = readl_relaxed(base + GAFR_OFFSET); 214 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3; 215 dir = gpdr & GPIO_bit(gpio); 216 217 if (__gpio_is_inverted(gpio)) 218 ret = (af != 1) || (dir == 0); 219 else 220 ret = (af != 0) || (dir != 0); 221 break; 222 default: 223 ret = gpdr & GPIO_bit(gpio); 224 break; 225 } 226 return ret; 227 } 228 229 int pxa_irq_to_gpio(int irq) 230 { 231 struct pxa_gpio_chip *pchip = pxa_gpio_chip; 232 int irq_gpio0; 233 234 irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0); 235 if (irq_gpio0 > 0) 236 return irq - irq_gpio0; 237 238 return irq_gpio0; 239 } 240 241 static bool pxa_gpio_has_pinctrl(void) 242 { 243 switch (gpio_type) { 244 case PXA3XX_GPIO: 245 case MMP2_GPIO: 246 return false; 247 248 default: 249 return true; 250 } 251 } 252 253 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 254 { 255 struct pxa_gpio_chip *pchip = chip_to_pxachip(chip); 256 257 return irq_find_mapping(pchip->irqdomain, offset); 258 } 259 260 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 261 { 262 void __iomem *base = gpio_bank_base(chip, offset); 263 uint32_t value, mask = GPIO_bit(offset); 264 unsigned long flags; 265 int ret; 266 267 if (pxa_gpio_has_pinctrl()) { 268 ret = pinctrl_gpio_direction_input(chip->base + offset); 269 if (ret) 270 return ret; 271 } 272 273 spin_lock_irqsave(&gpio_lock, flags); 274 275 value = readl_relaxed(base + GPDR_OFFSET); 276 if (__gpio_is_inverted(chip->base + offset)) 277 value |= mask; 278 else 279 value &= ~mask; 280 writel_relaxed(value, base + GPDR_OFFSET); 281 282 spin_unlock_irqrestore(&gpio_lock, flags); 283 return 0; 284 } 285 286 static int pxa_gpio_direction_output(struct gpio_chip *chip, 287 unsigned offset, int value) 288 { 289 void __iomem *base = gpio_bank_base(chip, offset); 290 uint32_t tmp, mask = GPIO_bit(offset); 291 unsigned long flags; 292 int ret; 293 294 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); 295 296 if (pxa_gpio_has_pinctrl()) { 297 ret = pinctrl_gpio_direction_output(chip->base + offset); 298 if (ret) 299 return ret; 300 } 301 302 spin_lock_irqsave(&gpio_lock, flags); 303 304 tmp = readl_relaxed(base + GPDR_OFFSET); 305 if (__gpio_is_inverted(chip->base + offset)) 306 tmp &= ~mask; 307 else 308 tmp |= mask; 309 writel_relaxed(tmp, base + GPDR_OFFSET); 310 311 spin_unlock_irqrestore(&gpio_lock, flags); 312 return 0; 313 } 314 315 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) 316 { 317 void __iomem *base = gpio_bank_base(chip, offset); 318 u32 gplr = readl_relaxed(base + GPLR_OFFSET); 319 320 return !!(gplr & GPIO_bit(offset)); 321 } 322 323 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 324 { 325 void __iomem *base = gpio_bank_base(chip, offset); 326 327 writel_relaxed(GPIO_bit(offset), 328 base + (value ? GPSR_OFFSET : GPCR_OFFSET)); 329 } 330 331 #ifdef CONFIG_OF_GPIO 332 static int pxa_gpio_of_xlate(struct gpio_chip *gc, 333 const struct of_phandle_args *gpiospec, 334 u32 *flags) 335 { 336 if (gpiospec->args[0] > pxa_last_gpio) 337 return -EINVAL; 338 339 if (flags) 340 *flags = gpiospec->args[1]; 341 342 return gpiospec->args[0]; 343 } 344 #endif 345 346 static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, 347 struct device_node *np, void __iomem *regbase) 348 { 349 int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32); 350 struct pxa_gpio_bank *bank; 351 352 pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks), 353 GFP_KERNEL); 354 if (!pchip->banks) 355 return -ENOMEM; 356 357 pchip->chip.label = "gpio-pxa"; 358 pchip->chip.direction_input = pxa_gpio_direction_input; 359 pchip->chip.direction_output = pxa_gpio_direction_output; 360 pchip->chip.get = pxa_gpio_get; 361 pchip->chip.set = pxa_gpio_set; 362 pchip->chip.to_irq = pxa_gpio_to_irq; 363 pchip->chip.ngpio = ngpio; 364 pchip->chip.request = gpiochip_generic_request; 365 pchip->chip.free = gpiochip_generic_free; 366 367 #ifdef CONFIG_OF_GPIO 368 pchip->chip.of_node = np; 369 pchip->chip.of_xlate = pxa_gpio_of_xlate; 370 pchip->chip.of_gpio_n_cells = 2; 371 #endif 372 373 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { 374 bank = pchip->banks + i; 375 bank->regbase = regbase + BANK_OFF(i); 376 } 377 378 return gpiochip_add_data(&pchip->chip, pchip); 379 } 380 381 /* Update only those GRERx and GFERx edge detection register bits if those 382 * bits are set in c->irq_mask 383 */ 384 static inline void update_edge_detect(struct pxa_gpio_bank *c) 385 { 386 uint32_t grer, gfer; 387 388 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; 389 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; 390 grer |= c->irq_edge_rise & c->irq_mask; 391 gfer |= c->irq_edge_fall & c->irq_mask; 392 writel_relaxed(grer, c->regbase + GRER_OFFSET); 393 writel_relaxed(gfer, c->regbase + GFER_OFFSET); 394 } 395 396 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) 397 { 398 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 399 unsigned int gpio = irqd_to_hwirq(d); 400 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); 401 unsigned long gpdr, mask = GPIO_bit(gpio); 402 403 if (type == IRQ_TYPE_PROBE) { 404 /* Don't mess with enabled GPIOs using preconfigured edges or 405 * GPIOs set to alternate function or to output during probe 406 */ 407 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) 408 return 0; 409 410 if (__gpio_is_occupied(pchip, gpio)) 411 return 0; 412 413 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 414 } 415 416 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); 417 418 if (__gpio_is_inverted(gpio)) 419 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); 420 else 421 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); 422 423 if (type & IRQ_TYPE_EDGE_RISING) 424 c->irq_edge_rise |= mask; 425 else 426 c->irq_edge_rise &= ~mask; 427 428 if (type & IRQ_TYPE_EDGE_FALLING) 429 c->irq_edge_fall |= mask; 430 else 431 c->irq_edge_fall &= ~mask; 432 433 update_edge_detect(c); 434 435 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, 436 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), 437 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); 438 return 0; 439 } 440 441 static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d) 442 { 443 int loop, gpio, n, handled = 0; 444 unsigned long gedr; 445 struct pxa_gpio_chip *pchip = d; 446 struct pxa_gpio_bank *c; 447 448 do { 449 loop = 0; 450 for_each_gpio_bank(gpio, c, pchip) { 451 gedr = readl_relaxed(c->regbase + GEDR_OFFSET); 452 gedr = gedr & c->irq_mask; 453 writel_relaxed(gedr, c->regbase + GEDR_OFFSET); 454 455 for_each_set_bit(n, &gedr, BITS_PER_LONG) { 456 loop = 1; 457 458 generic_handle_irq( 459 irq_find_mapping(pchip->irqdomain, 460 gpio + n)); 461 } 462 } 463 handled += loop; 464 } while (loop); 465 466 return handled ? IRQ_HANDLED : IRQ_NONE; 467 } 468 469 static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d) 470 { 471 struct pxa_gpio_chip *pchip = d; 472 473 if (in_irq == pchip->irq0) { 474 generic_handle_irq(irq_find_mapping(pchip->irqdomain, 0)); 475 } else if (in_irq == pchip->irq1) { 476 generic_handle_irq(irq_find_mapping(pchip->irqdomain, 1)); 477 } else { 478 pr_err("%s() unknown irq %d\n", __func__, in_irq); 479 return IRQ_NONE; 480 } 481 return IRQ_HANDLED; 482 } 483 484 static void pxa_ack_muxed_gpio(struct irq_data *d) 485 { 486 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 487 unsigned int gpio = irqd_to_hwirq(d); 488 void __iomem *base = gpio_bank_base(&pchip->chip, gpio); 489 490 writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET); 491 } 492 493 static void pxa_mask_muxed_gpio(struct irq_data *d) 494 { 495 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 496 unsigned int gpio = irqd_to_hwirq(d); 497 struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio); 498 void __iomem *base = gpio_bank_base(&pchip->chip, gpio); 499 uint32_t grer, gfer; 500 501 b->irq_mask &= ~GPIO_bit(gpio); 502 503 grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio); 504 gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio); 505 writel_relaxed(grer, base + GRER_OFFSET); 506 writel_relaxed(gfer, base + GFER_OFFSET); 507 } 508 509 static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) 510 { 511 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 512 unsigned int gpio = irqd_to_hwirq(d); 513 514 if (pchip->set_wake) 515 return pchip->set_wake(gpio, on); 516 else 517 return 0; 518 } 519 520 static void pxa_unmask_muxed_gpio(struct irq_data *d) 521 { 522 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 523 unsigned int gpio = irqd_to_hwirq(d); 524 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); 525 526 c->irq_mask |= GPIO_bit(gpio); 527 update_edge_detect(c); 528 } 529 530 static struct irq_chip pxa_muxed_gpio_chip = { 531 .name = "GPIO", 532 .irq_ack = pxa_ack_muxed_gpio, 533 .irq_mask = pxa_mask_muxed_gpio, 534 .irq_unmask = pxa_unmask_muxed_gpio, 535 .irq_set_type = pxa_gpio_irq_type, 536 .irq_set_wake = pxa_gpio_set_wake, 537 }; 538 539 static int pxa_gpio_nums(struct platform_device *pdev) 540 { 541 const struct platform_device_id *id = platform_get_device_id(pdev); 542 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data; 543 int count = 0; 544 545 switch (pxa_id->type) { 546 case PXA25X_GPIO: 547 case PXA26X_GPIO: 548 case PXA27X_GPIO: 549 case PXA3XX_GPIO: 550 case PXA93X_GPIO: 551 case MMP_GPIO: 552 case MMP2_GPIO: 553 case PXA1928_GPIO: 554 gpio_type = pxa_id->type; 555 count = pxa_id->gpio_nums - 1; 556 break; 557 default: 558 count = -EINVAL; 559 break; 560 } 561 return count; 562 } 563 564 static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, 565 irq_hw_number_t hw) 566 { 567 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 568 handle_edge_irq); 569 irq_set_chip_data(irq, d->host_data); 570 irq_set_noprobe(irq); 571 return 0; 572 } 573 574 static const struct irq_domain_ops pxa_irq_domain_ops = { 575 .map = pxa_irq_domain_map, 576 .xlate = irq_domain_xlate_twocell, 577 }; 578 579 #ifdef CONFIG_OF 580 static const struct of_device_id pxa_gpio_dt_ids[] = { 581 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, }, 582 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, }, 583 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, }, 584 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, }, 585 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, }, 586 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, }, 587 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, }, 588 { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, }, 589 {} 590 }; 591 592 static int pxa_gpio_probe_dt(struct platform_device *pdev, 593 struct pxa_gpio_chip *pchip) 594 { 595 int nr_gpios; 596 const struct pxa_gpio_id *gpio_id; 597 598 gpio_id = of_device_get_match_data(&pdev->dev); 599 gpio_type = gpio_id->type; 600 601 nr_gpios = gpio_id->gpio_nums; 602 pxa_last_gpio = nr_gpios - 1; 603 604 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, nr_gpios, 0); 605 if (irq_base < 0) { 606 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); 607 return irq_base; 608 } 609 return irq_base; 610 } 611 #else 612 #define pxa_gpio_probe_dt(pdev, pchip) (-1) 613 #endif 614 615 static int pxa_gpio_probe(struct platform_device *pdev) 616 { 617 struct pxa_gpio_chip *pchip; 618 struct pxa_gpio_bank *c; 619 struct clk *clk; 620 struct pxa_gpio_platform_data *info; 621 void __iomem *gpio_reg_base; 622 int gpio, ret; 623 int irq0 = 0, irq1 = 0, irq_mux; 624 625 pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL); 626 if (!pchip) 627 return -ENOMEM; 628 pchip->dev = &pdev->dev; 629 630 info = dev_get_platdata(&pdev->dev); 631 if (info) { 632 irq_base = info->irq_base; 633 if (irq_base <= 0) 634 return -EINVAL; 635 pxa_last_gpio = pxa_gpio_nums(pdev); 636 pchip->set_wake = info->gpio_set_wake; 637 } else { 638 irq_base = pxa_gpio_probe_dt(pdev, pchip); 639 if (irq_base < 0) 640 return -EINVAL; 641 } 642 643 if (!pxa_last_gpio) 644 return -EINVAL; 645 646 pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node, 647 pxa_last_gpio + 1, irq_base, 648 0, &pxa_irq_domain_ops, pchip); 649 if (!pchip->irqdomain) 650 return -ENOMEM; 651 652 irq0 = platform_get_irq_byname_optional(pdev, "gpio0"); 653 irq1 = platform_get_irq_byname_optional(pdev, "gpio1"); 654 irq_mux = platform_get_irq_byname(pdev, "gpio_mux"); 655 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0) 656 || (irq_mux <= 0)) 657 return -EINVAL; 658 659 pchip->irq0 = irq0; 660 pchip->irq1 = irq1; 661 662 gpio_reg_base = devm_platform_ioremap_resource(pdev, 0); 663 if (IS_ERR(gpio_reg_base)) 664 return PTR_ERR(gpio_reg_base); 665 666 clk = clk_get(&pdev->dev, NULL); 667 if (IS_ERR(clk)) { 668 dev_err(&pdev->dev, "Error %ld to get gpio clock\n", 669 PTR_ERR(clk)); 670 return PTR_ERR(clk); 671 } 672 ret = clk_prepare_enable(clk); 673 if (ret) { 674 clk_put(clk); 675 return ret; 676 } 677 678 /* Initialize GPIO chips */ 679 ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, pdev->dev.of_node, 680 gpio_reg_base); 681 if (ret) { 682 clk_put(clk); 683 return ret; 684 } 685 686 /* clear all GPIO edge detects */ 687 for_each_gpio_bank(gpio, c, pchip) { 688 writel_relaxed(0, c->regbase + GFER_OFFSET); 689 writel_relaxed(0, c->regbase + GRER_OFFSET); 690 writel_relaxed(~0, c->regbase + GEDR_OFFSET); 691 /* unmask GPIO edge detect for AP side */ 692 if (gpio_is_mmp_type(gpio_type)) 693 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); 694 } 695 696 if (irq0 > 0) { 697 ret = devm_request_irq(&pdev->dev, 698 irq0, pxa_gpio_direct_handler, 0, 699 "gpio-0", pchip); 700 if (ret) 701 dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n", 702 ret); 703 } 704 if (irq1 > 0) { 705 ret = devm_request_irq(&pdev->dev, 706 irq1, pxa_gpio_direct_handler, 0, 707 "gpio-1", pchip); 708 if (ret) 709 dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n", 710 ret); 711 } 712 ret = devm_request_irq(&pdev->dev, 713 irq_mux, pxa_gpio_demux_handler, 0, 714 "gpio-mux", pchip); 715 if (ret) 716 dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n", 717 ret); 718 719 pxa_gpio_chip = pchip; 720 721 return 0; 722 } 723 724 static const struct platform_device_id gpio_id_table[] = { 725 { "pxa25x-gpio", (unsigned long)&pxa25x_id }, 726 { "pxa26x-gpio", (unsigned long)&pxa26x_id }, 727 { "pxa27x-gpio", (unsigned long)&pxa27x_id }, 728 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id }, 729 { "pxa93x-gpio", (unsigned long)&pxa93x_id }, 730 { "mmp-gpio", (unsigned long)&mmp_id }, 731 { "mmp2-gpio", (unsigned long)&mmp2_id }, 732 { "pxa1928-gpio", (unsigned long)&pxa1928_id }, 733 { }, 734 }; 735 736 static struct platform_driver pxa_gpio_driver = { 737 .probe = pxa_gpio_probe, 738 .driver = { 739 .name = "pxa-gpio", 740 .of_match_table = of_match_ptr(pxa_gpio_dt_ids), 741 }, 742 .id_table = gpio_id_table, 743 }; 744 745 static int __init pxa_gpio_legacy_init(void) 746 { 747 if (of_have_populated_dt()) 748 return 0; 749 750 return platform_driver_register(&pxa_gpio_driver); 751 } 752 postcore_initcall(pxa_gpio_legacy_init); 753 754 static int __init pxa_gpio_dt_init(void) 755 { 756 if (of_have_populated_dt()) 757 return platform_driver_register(&pxa_gpio_driver); 758 759 return 0; 760 } 761 device_initcall(pxa_gpio_dt_init); 762 763 #ifdef CONFIG_PM 764 static int pxa_gpio_suspend(void) 765 { 766 struct pxa_gpio_chip *pchip = pxa_gpio_chip; 767 struct pxa_gpio_bank *c; 768 int gpio; 769 770 if (!pchip) 771 return 0; 772 773 for_each_gpio_bank(gpio, c, pchip) { 774 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET); 775 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); 776 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET); 777 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET); 778 779 /* Clear GPIO transition detect bits */ 780 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET); 781 } 782 return 0; 783 } 784 785 static void pxa_gpio_resume(void) 786 { 787 struct pxa_gpio_chip *pchip = pxa_gpio_chip; 788 struct pxa_gpio_bank *c; 789 int gpio; 790 791 if (!pchip) 792 return; 793 794 for_each_gpio_bank(gpio, c, pchip) { 795 /* restore level with set/clear */ 796 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET); 797 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET); 798 799 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET); 800 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET); 801 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET); 802 } 803 } 804 #else 805 #define pxa_gpio_suspend NULL 806 #define pxa_gpio_resume NULL 807 #endif 808 809 static struct syscore_ops pxa_gpio_syscore_ops = { 810 .suspend = pxa_gpio_suspend, 811 .resume = pxa_gpio_resume, 812 }; 813 814 static int __init pxa_gpio_sysinit(void) 815 { 816 register_syscore_ops(&pxa_gpio_syscore_ops); 817 return 0; 818 } 819 postcore_initcall(pxa_gpio_sysinit); 820