1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/plat-pxa/gpio.c 4 * 5 * Generic PXA GPIO handling 6 * 7 * Author: Nicolas Pitre 8 * Created: Jun 15, 2001 9 * Copyright: MontaVista Software Inc. 10 */ 11 #include <linux/module.h> 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/gpio-pxa.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/irq.h> 19 #include <linux/irqdomain.h> 20 #include <linux/irqchip/chained_irq.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/platform_device.h> 25 #include <linux/syscore_ops.h> 26 #include <linux/slab.h> 27 28 /* 29 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with 30 * one set of registers. The register offsets are organized below: 31 * 32 * GPLR GPDR GPSR GPCR GRER GFER GEDR 33 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 34 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C 35 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 36 * 37 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 38 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C 39 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 40 * 41 * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248 42 * 43 * NOTE: 44 * BANK 3 is only available on PXA27x and later processors. 45 * BANK 4 and 5 are only available on PXA935, PXA1928 46 * BANK 6 is only available on PXA1928 47 */ 48 49 #define GPLR_OFFSET 0x00 50 #define GPDR_OFFSET 0x0C 51 #define GPSR_OFFSET 0x18 52 #define GPCR_OFFSET 0x24 53 #define GRER_OFFSET 0x30 54 #define GFER_OFFSET 0x3C 55 #define GEDR_OFFSET 0x48 56 #define GAFR_OFFSET 0x54 57 #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */ 58 59 #define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2) 60 61 int pxa_last_gpio; 62 static int irq_base; 63 64 struct pxa_gpio_bank { 65 void __iomem *regbase; 66 unsigned long irq_mask; 67 unsigned long irq_edge_rise; 68 unsigned long irq_edge_fall; 69 70 #ifdef CONFIG_PM 71 unsigned long saved_gplr; 72 unsigned long saved_gpdr; 73 unsigned long saved_grer; 74 unsigned long saved_gfer; 75 #endif 76 }; 77 78 struct pxa_gpio_chip { 79 struct device *dev; 80 struct gpio_chip chip; 81 struct pxa_gpio_bank *banks; 82 struct irq_domain *irqdomain; 83 84 int irq0; 85 int irq1; 86 int (*set_wake)(unsigned int gpio, unsigned int on); 87 }; 88 89 enum pxa_gpio_type { 90 PXA25X_GPIO = 0, 91 PXA26X_GPIO, 92 PXA27X_GPIO, 93 PXA3XX_GPIO, 94 PXA93X_GPIO, 95 MMP_GPIO = 0x10, 96 MMP2_GPIO, 97 PXA1928_GPIO, 98 }; 99 100 struct pxa_gpio_id { 101 enum pxa_gpio_type type; 102 int gpio_nums; 103 }; 104 105 static DEFINE_SPINLOCK(gpio_lock); 106 static struct pxa_gpio_chip *pxa_gpio_chip; 107 static enum pxa_gpio_type gpio_type; 108 109 static struct pxa_gpio_id pxa25x_id = { 110 .type = PXA25X_GPIO, 111 .gpio_nums = 85, 112 }; 113 114 static struct pxa_gpio_id pxa26x_id = { 115 .type = PXA26X_GPIO, 116 .gpio_nums = 90, 117 }; 118 119 static struct pxa_gpio_id pxa27x_id = { 120 .type = PXA27X_GPIO, 121 .gpio_nums = 121, 122 }; 123 124 static struct pxa_gpio_id pxa3xx_id = { 125 .type = PXA3XX_GPIO, 126 .gpio_nums = 128, 127 }; 128 129 static struct pxa_gpio_id pxa93x_id = { 130 .type = PXA93X_GPIO, 131 .gpio_nums = 192, 132 }; 133 134 static struct pxa_gpio_id mmp_id = { 135 .type = MMP_GPIO, 136 .gpio_nums = 128, 137 }; 138 139 static struct pxa_gpio_id mmp2_id = { 140 .type = MMP2_GPIO, 141 .gpio_nums = 192, 142 }; 143 144 static struct pxa_gpio_id pxa1928_id = { 145 .type = PXA1928_GPIO, 146 .gpio_nums = 224, 147 }; 148 149 #define for_each_gpio_bank(i, b, pc) \ 150 for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++) 151 152 static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c) 153 { 154 struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c); 155 156 return pxa_chip; 157 } 158 159 static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio) 160 { 161 struct pxa_gpio_chip *p = gpiochip_get_data(c); 162 struct pxa_gpio_bank *bank = p->banks + (gpio / 32); 163 164 return bank->regbase; 165 } 166 167 static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c, 168 unsigned gpio) 169 { 170 return chip_to_pxachip(c)->banks + gpio / 32; 171 } 172 173 static inline int gpio_is_mmp_type(int type) 174 { 175 return (type & MMP_GPIO) != 0; 176 } 177 178 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, 179 * as well as their Alternate Function value being '1' for GPIO in GAFRx. 180 */ 181 static inline int __gpio_is_inverted(int gpio) 182 { 183 if ((gpio_type == PXA26X_GPIO) && (gpio > 85)) 184 return 1; 185 return 0; 186 } 187 188 /* 189 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate 190 * function of a GPIO, and GPDRx cannot be altered once configured. It 191 * is attributed as "occupied" here (I know this terminology isn't 192 * accurate, you are welcome to propose a better one :-) 193 */ 194 static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio) 195 { 196 void __iomem *base; 197 unsigned long gafr = 0, gpdr = 0; 198 int ret, af = 0, dir = 0; 199 200 base = gpio_bank_base(&pchip->chip, gpio); 201 gpdr = readl_relaxed(base + GPDR_OFFSET); 202 203 switch (gpio_type) { 204 case PXA25X_GPIO: 205 case PXA26X_GPIO: 206 case PXA27X_GPIO: 207 gafr = readl_relaxed(base + GAFR_OFFSET); 208 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3; 209 dir = gpdr & GPIO_bit(gpio); 210 211 if (__gpio_is_inverted(gpio)) 212 ret = (af != 1) || (dir == 0); 213 else 214 ret = (af != 0) || (dir != 0); 215 break; 216 default: 217 ret = gpdr & GPIO_bit(gpio); 218 break; 219 } 220 return ret; 221 } 222 223 int pxa_irq_to_gpio(int irq) 224 { 225 struct pxa_gpio_chip *pchip = pxa_gpio_chip; 226 int irq_gpio0; 227 228 irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0); 229 if (irq_gpio0 > 0) 230 return irq - irq_gpio0; 231 232 return irq_gpio0; 233 } 234 235 static bool pxa_gpio_has_pinctrl(void) 236 { 237 switch (gpio_type) { 238 case PXA3XX_GPIO: 239 case MMP2_GPIO: 240 return false; 241 242 default: 243 return true; 244 } 245 } 246 247 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 248 { 249 struct pxa_gpio_chip *pchip = chip_to_pxachip(chip); 250 251 return irq_find_mapping(pchip->irqdomain, offset); 252 } 253 254 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 255 { 256 void __iomem *base = gpio_bank_base(chip, offset); 257 uint32_t value, mask = GPIO_bit(offset); 258 unsigned long flags; 259 int ret; 260 261 if (pxa_gpio_has_pinctrl()) { 262 ret = pinctrl_gpio_direction_input(chip->base + offset); 263 if (ret) 264 return ret; 265 } 266 267 spin_lock_irqsave(&gpio_lock, flags); 268 269 value = readl_relaxed(base + GPDR_OFFSET); 270 if (__gpio_is_inverted(chip->base + offset)) 271 value |= mask; 272 else 273 value &= ~mask; 274 writel_relaxed(value, base + GPDR_OFFSET); 275 276 spin_unlock_irqrestore(&gpio_lock, flags); 277 return 0; 278 } 279 280 static int pxa_gpio_direction_output(struct gpio_chip *chip, 281 unsigned offset, int value) 282 { 283 void __iomem *base = gpio_bank_base(chip, offset); 284 uint32_t tmp, mask = GPIO_bit(offset); 285 unsigned long flags; 286 int ret; 287 288 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); 289 290 if (pxa_gpio_has_pinctrl()) { 291 ret = pinctrl_gpio_direction_output(chip->base + offset); 292 if (ret) 293 return ret; 294 } 295 296 spin_lock_irqsave(&gpio_lock, flags); 297 298 tmp = readl_relaxed(base + GPDR_OFFSET); 299 if (__gpio_is_inverted(chip->base + offset)) 300 tmp &= ~mask; 301 else 302 tmp |= mask; 303 writel_relaxed(tmp, base + GPDR_OFFSET); 304 305 spin_unlock_irqrestore(&gpio_lock, flags); 306 return 0; 307 } 308 309 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) 310 { 311 void __iomem *base = gpio_bank_base(chip, offset); 312 u32 gplr = readl_relaxed(base + GPLR_OFFSET); 313 314 return !!(gplr & GPIO_bit(offset)); 315 } 316 317 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 318 { 319 void __iomem *base = gpio_bank_base(chip, offset); 320 321 writel_relaxed(GPIO_bit(offset), 322 base + (value ? GPSR_OFFSET : GPCR_OFFSET)); 323 } 324 325 #ifdef CONFIG_OF_GPIO 326 static int pxa_gpio_of_xlate(struct gpio_chip *gc, 327 const struct of_phandle_args *gpiospec, 328 u32 *flags) 329 { 330 if (gpiospec->args[0] > pxa_last_gpio) 331 return -EINVAL; 332 333 if (flags) 334 *flags = gpiospec->args[1]; 335 336 return gpiospec->args[0]; 337 } 338 #endif 339 340 static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, void __iomem *regbase) 341 { 342 int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32); 343 struct pxa_gpio_bank *bank; 344 345 pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks), 346 GFP_KERNEL); 347 if (!pchip->banks) 348 return -ENOMEM; 349 350 pchip->chip.parent = pchip->dev; 351 pchip->chip.label = "gpio-pxa"; 352 pchip->chip.direction_input = pxa_gpio_direction_input; 353 pchip->chip.direction_output = pxa_gpio_direction_output; 354 pchip->chip.get = pxa_gpio_get; 355 pchip->chip.set = pxa_gpio_set; 356 pchip->chip.to_irq = pxa_gpio_to_irq; 357 pchip->chip.ngpio = ngpio; 358 pchip->chip.request = gpiochip_generic_request; 359 pchip->chip.free = gpiochip_generic_free; 360 361 #ifdef CONFIG_OF_GPIO 362 pchip->chip.of_xlate = pxa_gpio_of_xlate; 363 pchip->chip.of_gpio_n_cells = 2; 364 #endif 365 366 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { 367 bank = pchip->banks + i; 368 bank->regbase = regbase + BANK_OFF(i); 369 } 370 371 return gpiochip_add_data(&pchip->chip, pchip); 372 } 373 374 /* Update only those GRERx and GFERx edge detection register bits if those 375 * bits are set in c->irq_mask 376 */ 377 static inline void update_edge_detect(struct pxa_gpio_bank *c) 378 { 379 uint32_t grer, gfer; 380 381 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; 382 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; 383 grer |= c->irq_edge_rise & c->irq_mask; 384 gfer |= c->irq_edge_fall & c->irq_mask; 385 writel_relaxed(grer, c->regbase + GRER_OFFSET); 386 writel_relaxed(gfer, c->regbase + GFER_OFFSET); 387 } 388 389 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) 390 { 391 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 392 unsigned int gpio = irqd_to_hwirq(d); 393 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); 394 unsigned long gpdr, mask = GPIO_bit(gpio); 395 396 if (type == IRQ_TYPE_PROBE) { 397 /* Don't mess with enabled GPIOs using preconfigured edges or 398 * GPIOs set to alternate function or to output during probe 399 */ 400 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) 401 return 0; 402 403 if (__gpio_is_occupied(pchip, gpio)) 404 return 0; 405 406 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 407 } 408 409 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); 410 411 if (__gpio_is_inverted(gpio)) 412 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); 413 else 414 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); 415 416 if (type & IRQ_TYPE_EDGE_RISING) 417 c->irq_edge_rise |= mask; 418 else 419 c->irq_edge_rise &= ~mask; 420 421 if (type & IRQ_TYPE_EDGE_FALLING) 422 c->irq_edge_fall |= mask; 423 else 424 c->irq_edge_fall &= ~mask; 425 426 update_edge_detect(c); 427 428 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, 429 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), 430 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); 431 return 0; 432 } 433 434 static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d) 435 { 436 int loop, gpio, n, handled = 0; 437 unsigned long gedr; 438 struct pxa_gpio_chip *pchip = d; 439 struct pxa_gpio_bank *c; 440 441 do { 442 loop = 0; 443 for_each_gpio_bank(gpio, c, pchip) { 444 gedr = readl_relaxed(c->regbase + GEDR_OFFSET); 445 gedr = gedr & c->irq_mask; 446 writel_relaxed(gedr, c->regbase + GEDR_OFFSET); 447 448 for_each_set_bit(n, &gedr, BITS_PER_LONG) { 449 loop = 1; 450 451 generic_handle_domain_irq(pchip->irqdomain, 452 gpio + n); 453 } 454 } 455 handled += loop; 456 } while (loop); 457 458 return handled ? IRQ_HANDLED : IRQ_NONE; 459 } 460 461 static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d) 462 { 463 struct pxa_gpio_chip *pchip = d; 464 465 if (in_irq == pchip->irq0) { 466 generic_handle_domain_irq(pchip->irqdomain, 0); 467 } else if (in_irq == pchip->irq1) { 468 generic_handle_domain_irq(pchip->irqdomain, 1); 469 } else { 470 pr_err("%s() unknown irq %d\n", __func__, in_irq); 471 return IRQ_NONE; 472 } 473 return IRQ_HANDLED; 474 } 475 476 static void pxa_ack_muxed_gpio(struct irq_data *d) 477 { 478 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 479 unsigned int gpio = irqd_to_hwirq(d); 480 void __iomem *base = gpio_bank_base(&pchip->chip, gpio); 481 482 writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET); 483 } 484 485 static void pxa_mask_muxed_gpio(struct irq_data *d) 486 { 487 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 488 unsigned int gpio = irqd_to_hwirq(d); 489 struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio); 490 void __iomem *base = gpio_bank_base(&pchip->chip, gpio); 491 uint32_t grer, gfer; 492 493 b->irq_mask &= ~GPIO_bit(gpio); 494 495 grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio); 496 gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio); 497 writel_relaxed(grer, base + GRER_OFFSET); 498 writel_relaxed(gfer, base + GFER_OFFSET); 499 } 500 501 static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) 502 { 503 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 504 unsigned int gpio = irqd_to_hwirq(d); 505 506 if (pchip->set_wake) 507 return pchip->set_wake(gpio, on); 508 else 509 return 0; 510 } 511 512 static void pxa_unmask_muxed_gpio(struct irq_data *d) 513 { 514 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 515 unsigned int gpio = irqd_to_hwirq(d); 516 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); 517 518 c->irq_mask |= GPIO_bit(gpio); 519 update_edge_detect(c); 520 } 521 522 static struct irq_chip pxa_muxed_gpio_chip = { 523 .name = "GPIO", 524 .irq_ack = pxa_ack_muxed_gpio, 525 .irq_mask = pxa_mask_muxed_gpio, 526 .irq_unmask = pxa_unmask_muxed_gpio, 527 .irq_set_type = pxa_gpio_irq_type, 528 .irq_set_wake = pxa_gpio_set_wake, 529 }; 530 531 static int pxa_gpio_nums(struct platform_device *pdev) 532 { 533 const struct platform_device_id *id = platform_get_device_id(pdev); 534 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data; 535 int count = 0; 536 537 switch (pxa_id->type) { 538 case PXA25X_GPIO: 539 case PXA26X_GPIO: 540 case PXA27X_GPIO: 541 case PXA3XX_GPIO: 542 case PXA93X_GPIO: 543 case MMP_GPIO: 544 case MMP2_GPIO: 545 case PXA1928_GPIO: 546 gpio_type = pxa_id->type; 547 count = pxa_id->gpio_nums - 1; 548 break; 549 default: 550 count = -EINVAL; 551 break; 552 } 553 return count; 554 } 555 556 static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, 557 irq_hw_number_t hw) 558 { 559 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 560 handle_edge_irq); 561 irq_set_chip_data(irq, d->host_data); 562 irq_set_noprobe(irq); 563 return 0; 564 } 565 566 static const struct irq_domain_ops pxa_irq_domain_ops = { 567 .map = pxa_irq_domain_map, 568 .xlate = irq_domain_xlate_twocell, 569 }; 570 571 #ifdef CONFIG_OF 572 static const struct of_device_id pxa_gpio_dt_ids[] = { 573 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, }, 574 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, }, 575 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, }, 576 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, }, 577 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, }, 578 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, }, 579 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, }, 580 { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, }, 581 {} 582 }; 583 584 static int pxa_gpio_probe_dt(struct platform_device *pdev, 585 struct pxa_gpio_chip *pchip) 586 { 587 int nr_gpios; 588 const struct pxa_gpio_id *gpio_id; 589 590 gpio_id = of_device_get_match_data(&pdev->dev); 591 gpio_type = gpio_id->type; 592 593 nr_gpios = gpio_id->gpio_nums; 594 pxa_last_gpio = nr_gpios - 1; 595 596 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, nr_gpios, 0); 597 if (irq_base < 0) { 598 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); 599 return irq_base; 600 } 601 return irq_base; 602 } 603 #else 604 #define pxa_gpio_probe_dt(pdev, pchip) (-1) 605 #endif 606 607 static int pxa_gpio_probe(struct platform_device *pdev) 608 { 609 struct pxa_gpio_chip *pchip; 610 struct pxa_gpio_bank *c; 611 struct clk *clk; 612 struct pxa_gpio_platform_data *info; 613 void __iomem *gpio_reg_base; 614 int gpio, ret; 615 int irq0 = 0, irq1 = 0, irq_mux; 616 617 pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL); 618 if (!pchip) 619 return -ENOMEM; 620 pchip->dev = &pdev->dev; 621 622 info = dev_get_platdata(&pdev->dev); 623 if (info) { 624 irq_base = info->irq_base; 625 if (irq_base <= 0) 626 return -EINVAL; 627 pxa_last_gpio = pxa_gpio_nums(pdev); 628 pchip->set_wake = info->gpio_set_wake; 629 } else { 630 irq_base = pxa_gpio_probe_dt(pdev, pchip); 631 if (irq_base < 0) 632 return -EINVAL; 633 } 634 635 if (!pxa_last_gpio) 636 return -EINVAL; 637 638 pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node, 639 pxa_last_gpio + 1, irq_base, 640 0, &pxa_irq_domain_ops, pchip); 641 if (!pchip->irqdomain) 642 return -ENOMEM; 643 644 irq0 = platform_get_irq_byname_optional(pdev, "gpio0"); 645 irq1 = platform_get_irq_byname_optional(pdev, "gpio1"); 646 irq_mux = platform_get_irq_byname(pdev, "gpio_mux"); 647 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0) 648 || (irq_mux <= 0)) 649 return -EINVAL; 650 651 pchip->irq0 = irq0; 652 pchip->irq1 = irq1; 653 654 gpio_reg_base = devm_platform_ioremap_resource(pdev, 0); 655 if (IS_ERR(gpio_reg_base)) 656 return PTR_ERR(gpio_reg_base); 657 658 clk = devm_clk_get_enabled(&pdev->dev, NULL); 659 if (IS_ERR(clk)) { 660 dev_err(&pdev->dev, "Error %ld to get gpio clock\n", 661 PTR_ERR(clk)); 662 return PTR_ERR(clk); 663 } 664 665 /* Initialize GPIO chips */ 666 ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, gpio_reg_base); 667 if (ret) 668 return ret; 669 670 /* clear all GPIO edge detects */ 671 for_each_gpio_bank(gpio, c, pchip) { 672 writel_relaxed(0, c->regbase + GFER_OFFSET); 673 writel_relaxed(0, c->regbase + GRER_OFFSET); 674 writel_relaxed(~0, c->regbase + GEDR_OFFSET); 675 /* unmask GPIO edge detect for AP side */ 676 if (gpio_is_mmp_type(gpio_type)) 677 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); 678 } 679 680 if (irq0 > 0) { 681 ret = devm_request_irq(&pdev->dev, 682 irq0, pxa_gpio_direct_handler, 0, 683 "gpio-0", pchip); 684 if (ret) 685 dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n", 686 ret); 687 } 688 if (irq1 > 0) { 689 ret = devm_request_irq(&pdev->dev, 690 irq1, pxa_gpio_direct_handler, 0, 691 "gpio-1", pchip); 692 if (ret) 693 dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n", 694 ret); 695 } 696 ret = devm_request_irq(&pdev->dev, 697 irq_mux, pxa_gpio_demux_handler, 0, 698 "gpio-mux", pchip); 699 if (ret) 700 dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n", 701 ret); 702 703 pxa_gpio_chip = pchip; 704 705 return 0; 706 } 707 708 static const struct platform_device_id gpio_id_table[] = { 709 { "pxa25x-gpio", (unsigned long)&pxa25x_id }, 710 { "pxa26x-gpio", (unsigned long)&pxa26x_id }, 711 { "pxa27x-gpio", (unsigned long)&pxa27x_id }, 712 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id }, 713 { "pxa93x-gpio", (unsigned long)&pxa93x_id }, 714 { "mmp-gpio", (unsigned long)&mmp_id }, 715 { "mmp2-gpio", (unsigned long)&mmp2_id }, 716 { "pxa1928-gpio", (unsigned long)&pxa1928_id }, 717 { }, 718 }; 719 720 static struct platform_driver pxa_gpio_driver = { 721 .probe = pxa_gpio_probe, 722 .driver = { 723 .name = "pxa-gpio", 724 .of_match_table = of_match_ptr(pxa_gpio_dt_ids), 725 }, 726 .id_table = gpio_id_table, 727 }; 728 729 static int __init pxa_gpio_legacy_init(void) 730 { 731 if (of_have_populated_dt()) 732 return 0; 733 734 return platform_driver_register(&pxa_gpio_driver); 735 } 736 postcore_initcall(pxa_gpio_legacy_init); 737 738 static int __init pxa_gpio_dt_init(void) 739 { 740 if (of_have_populated_dt()) 741 return platform_driver_register(&pxa_gpio_driver); 742 743 return 0; 744 } 745 device_initcall(pxa_gpio_dt_init); 746 747 #ifdef CONFIG_PM 748 static int pxa_gpio_suspend(void) 749 { 750 struct pxa_gpio_chip *pchip = pxa_gpio_chip; 751 struct pxa_gpio_bank *c; 752 int gpio; 753 754 if (!pchip) 755 return 0; 756 757 for_each_gpio_bank(gpio, c, pchip) { 758 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET); 759 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); 760 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET); 761 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET); 762 763 /* Clear GPIO transition detect bits */ 764 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET); 765 } 766 return 0; 767 } 768 769 static void pxa_gpio_resume(void) 770 { 771 struct pxa_gpio_chip *pchip = pxa_gpio_chip; 772 struct pxa_gpio_bank *c; 773 int gpio; 774 775 if (!pchip) 776 return; 777 778 for_each_gpio_bank(gpio, c, pchip) { 779 /* restore level with set/clear */ 780 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET); 781 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET); 782 783 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET); 784 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET); 785 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET); 786 } 787 } 788 #else 789 #define pxa_gpio_suspend NULL 790 #define pxa_gpio_resume NULL 791 #endif 792 793 static struct syscore_ops pxa_gpio_syscore_ops = { 794 .suspend = pxa_gpio_suspend, 795 .resume = pxa_gpio_resume, 796 }; 797 798 static int __init pxa_gpio_sysinit(void) 799 { 800 register_syscore_ops(&pxa_gpio_syscore_ops); 801 return 0; 802 } 803 postcore_initcall(pxa_gpio_sysinit); 804