1 /* 2 * linux/arch/arm/plat-pxa/gpio.c 3 * 4 * Generic PXA GPIO handling 5 * 6 * Author: Nicolas Pitre 7 * Created: Jun 15, 2001 8 * Copyright: MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/module.h> 15 #include <linux/clk.h> 16 #include <linux/err.h> 17 #include <linux/gpio.h> 18 #include <linux/gpio-pxa.h> 19 #include <linux/init.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/irqchip/chained_irq.h> 23 #include <linux/io.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/syscore_ops.h> 28 #include <linux/slab.h> 29 30 #include <mach/irqs.h> 31 32 /* 33 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with 34 * one set of registers. The register offsets are organized below: 35 * 36 * GPLR GPDR GPSR GPCR GRER GFER GEDR 37 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 38 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C 39 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 40 * 41 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 42 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C 43 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 44 * 45 * NOTE: 46 * BANK 3 is only available on PXA27x and later processors. 47 * BANK 4 and 5 are only available on PXA935 48 */ 49 50 #define GPLR_OFFSET 0x00 51 #define GPDR_OFFSET 0x0C 52 #define GPSR_OFFSET 0x18 53 #define GPCR_OFFSET 0x24 54 #define GRER_OFFSET 0x30 55 #define GFER_OFFSET 0x3C 56 #define GEDR_OFFSET 0x48 57 #define GAFR_OFFSET 0x54 58 #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */ 59 60 #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) 61 62 int pxa_last_gpio; 63 static int irq_base; 64 65 #ifdef CONFIG_OF 66 static struct irq_domain *domain; 67 static struct device_node *pxa_gpio_of_node; 68 #endif 69 70 struct pxa_gpio_chip { 71 struct gpio_chip chip; 72 void __iomem *regbase; 73 char label[10]; 74 75 unsigned long irq_mask; 76 unsigned long irq_edge_rise; 77 unsigned long irq_edge_fall; 78 int (*set_wake)(unsigned int gpio, unsigned int on); 79 80 #ifdef CONFIG_PM 81 unsigned long saved_gplr; 82 unsigned long saved_gpdr; 83 unsigned long saved_grer; 84 unsigned long saved_gfer; 85 #endif 86 }; 87 88 enum pxa_gpio_type { 89 PXA25X_GPIO = 0, 90 PXA26X_GPIO, 91 PXA27X_GPIO, 92 PXA3XX_GPIO, 93 PXA93X_GPIO, 94 MMP_GPIO = 0x10, 95 MMP2_GPIO, 96 }; 97 98 struct pxa_gpio_id { 99 enum pxa_gpio_type type; 100 int gpio_nums; 101 }; 102 103 static DEFINE_SPINLOCK(gpio_lock); 104 static struct pxa_gpio_chip *pxa_gpio_chips; 105 static enum pxa_gpio_type gpio_type; 106 static void __iomem *gpio_reg_base; 107 108 static struct pxa_gpio_id pxa25x_id = { 109 .type = PXA25X_GPIO, 110 .gpio_nums = 85, 111 }; 112 113 static struct pxa_gpio_id pxa26x_id = { 114 .type = PXA26X_GPIO, 115 .gpio_nums = 90, 116 }; 117 118 static struct pxa_gpio_id pxa27x_id = { 119 .type = PXA27X_GPIO, 120 .gpio_nums = 121, 121 }; 122 123 static struct pxa_gpio_id pxa3xx_id = { 124 .type = PXA3XX_GPIO, 125 .gpio_nums = 128, 126 }; 127 128 static struct pxa_gpio_id pxa93x_id = { 129 .type = PXA93X_GPIO, 130 .gpio_nums = 192, 131 }; 132 133 static struct pxa_gpio_id mmp_id = { 134 .type = MMP_GPIO, 135 .gpio_nums = 128, 136 }; 137 138 static struct pxa_gpio_id mmp2_id = { 139 .type = MMP2_GPIO, 140 .gpio_nums = 192, 141 }; 142 143 #define for_each_gpio_chip(i, c) \ 144 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++) 145 146 static inline void __iomem *gpio_chip_base(struct gpio_chip *c) 147 { 148 return container_of(c, struct pxa_gpio_chip, chip)->regbase; 149 } 150 151 static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio) 152 { 153 return &pxa_gpio_chips[gpio_to_bank(gpio)]; 154 } 155 156 static inline int gpio_is_pxa_type(int type) 157 { 158 return (type & MMP_GPIO) == 0; 159 } 160 161 static inline int gpio_is_mmp_type(int type) 162 { 163 return (type & MMP_GPIO) != 0; 164 } 165 166 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, 167 * as well as their Alternate Function value being '1' for GPIO in GAFRx. 168 */ 169 static inline int __gpio_is_inverted(int gpio) 170 { 171 if ((gpio_type == PXA26X_GPIO) && (gpio > 85)) 172 return 1; 173 return 0; 174 } 175 176 /* 177 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate 178 * function of a GPIO, and GPDRx cannot be altered once configured. It 179 * is attributed as "occupied" here (I know this terminology isn't 180 * accurate, you are welcome to propose a better one :-) 181 */ 182 static inline int __gpio_is_occupied(unsigned gpio) 183 { 184 struct pxa_gpio_chip *pxachip; 185 void __iomem *base; 186 unsigned long gafr = 0, gpdr = 0; 187 int ret, af = 0, dir = 0; 188 189 pxachip = gpio_to_pxachip(gpio); 190 base = gpio_chip_base(&pxachip->chip); 191 gpdr = readl_relaxed(base + GPDR_OFFSET); 192 193 switch (gpio_type) { 194 case PXA25X_GPIO: 195 case PXA26X_GPIO: 196 case PXA27X_GPIO: 197 gafr = readl_relaxed(base + GAFR_OFFSET); 198 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3; 199 dir = gpdr & GPIO_bit(gpio); 200 201 if (__gpio_is_inverted(gpio)) 202 ret = (af != 1) || (dir == 0); 203 else 204 ret = (af != 0) || (dir != 0); 205 break; 206 default: 207 ret = gpdr & GPIO_bit(gpio); 208 break; 209 } 210 return ret; 211 } 212 213 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 214 { 215 return chip->base + offset + irq_base; 216 } 217 218 int pxa_irq_to_gpio(int irq) 219 { 220 return irq - irq_base; 221 } 222 223 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 224 { 225 void __iomem *base = gpio_chip_base(chip); 226 uint32_t value, mask = 1 << offset; 227 unsigned long flags; 228 229 spin_lock_irqsave(&gpio_lock, flags); 230 231 value = readl_relaxed(base + GPDR_OFFSET); 232 if (__gpio_is_inverted(chip->base + offset)) 233 value |= mask; 234 else 235 value &= ~mask; 236 writel_relaxed(value, base + GPDR_OFFSET); 237 238 spin_unlock_irqrestore(&gpio_lock, flags); 239 return 0; 240 } 241 242 static int pxa_gpio_direction_output(struct gpio_chip *chip, 243 unsigned offset, int value) 244 { 245 void __iomem *base = gpio_chip_base(chip); 246 uint32_t tmp, mask = 1 << offset; 247 unsigned long flags; 248 249 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); 250 251 spin_lock_irqsave(&gpio_lock, flags); 252 253 tmp = readl_relaxed(base + GPDR_OFFSET); 254 if (__gpio_is_inverted(chip->base + offset)) 255 tmp &= ~mask; 256 else 257 tmp |= mask; 258 writel_relaxed(tmp, base + GPDR_OFFSET); 259 260 spin_unlock_irqrestore(&gpio_lock, flags); 261 return 0; 262 } 263 264 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) 265 { 266 u32 gplr = readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET); 267 return !!(gplr & (1 << offset)); 268 } 269 270 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 271 { 272 writel_relaxed(1 << offset, gpio_chip_base(chip) + 273 (value ? GPSR_OFFSET : GPCR_OFFSET)); 274 } 275 276 #ifdef CONFIG_OF_GPIO 277 static int pxa_gpio_of_xlate(struct gpio_chip *gc, 278 const struct of_phandle_args *gpiospec, 279 u32 *flags) 280 { 281 if (gpiospec->args[0] > pxa_last_gpio) 282 return -EINVAL; 283 284 if (gc != &pxa_gpio_chips[gpiospec->args[0] / 32].chip) 285 return -EINVAL; 286 287 if (flags) 288 *flags = gpiospec->args[1]; 289 290 return gpiospec->args[0] % 32; 291 } 292 #endif 293 294 static int pxa_init_gpio_chip(int gpio_end, 295 int (*set_wake)(unsigned int, unsigned int)) 296 { 297 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; 298 struct pxa_gpio_chip *chips; 299 300 chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL); 301 if (chips == NULL) { 302 pr_err("%s: failed to allocate GPIO chips\n", __func__); 303 return -ENOMEM; 304 } 305 306 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { 307 struct gpio_chip *c = &chips[i].chip; 308 309 sprintf(chips[i].label, "gpio-%d", i); 310 chips[i].regbase = gpio_reg_base + BANK_OFF(i); 311 chips[i].set_wake = set_wake; 312 313 c->base = gpio; 314 c->label = chips[i].label; 315 316 c->direction_input = pxa_gpio_direction_input; 317 c->direction_output = pxa_gpio_direction_output; 318 c->get = pxa_gpio_get; 319 c->set = pxa_gpio_set; 320 c->to_irq = pxa_gpio_to_irq; 321 #ifdef CONFIG_OF_GPIO 322 c->of_node = pxa_gpio_of_node; 323 c->of_xlate = pxa_gpio_of_xlate; 324 c->of_gpio_n_cells = 2; 325 #endif 326 327 /* number of GPIOs on last bank may be less than 32 */ 328 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32; 329 gpiochip_add(c); 330 } 331 pxa_gpio_chips = chips; 332 return 0; 333 } 334 335 /* Update only those GRERx and GFERx edge detection register bits if those 336 * bits are set in c->irq_mask 337 */ 338 static inline void update_edge_detect(struct pxa_gpio_chip *c) 339 { 340 uint32_t grer, gfer; 341 342 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; 343 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; 344 grer |= c->irq_edge_rise & c->irq_mask; 345 gfer |= c->irq_edge_fall & c->irq_mask; 346 writel_relaxed(grer, c->regbase + GRER_OFFSET); 347 writel_relaxed(gfer, c->regbase + GFER_OFFSET); 348 } 349 350 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) 351 { 352 struct pxa_gpio_chip *c; 353 int gpio = pxa_irq_to_gpio(d->irq); 354 unsigned long gpdr, mask = GPIO_bit(gpio); 355 356 c = gpio_to_pxachip(gpio); 357 358 if (type == IRQ_TYPE_PROBE) { 359 /* Don't mess with enabled GPIOs using preconfigured edges or 360 * GPIOs set to alternate function or to output during probe 361 */ 362 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) 363 return 0; 364 365 if (__gpio_is_occupied(gpio)) 366 return 0; 367 368 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 369 } 370 371 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); 372 373 if (__gpio_is_inverted(gpio)) 374 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); 375 else 376 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); 377 378 if (type & IRQ_TYPE_EDGE_RISING) 379 c->irq_edge_rise |= mask; 380 else 381 c->irq_edge_rise &= ~mask; 382 383 if (type & IRQ_TYPE_EDGE_FALLING) 384 c->irq_edge_fall |= mask; 385 else 386 c->irq_edge_fall &= ~mask; 387 388 update_edge_detect(c); 389 390 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, 391 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), 392 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); 393 return 0; 394 } 395 396 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) 397 { 398 struct pxa_gpio_chip *c; 399 int loop, gpio, gpio_base, n; 400 unsigned long gedr; 401 struct irq_chip *chip = irq_desc_get_chip(desc); 402 403 chained_irq_enter(chip, desc); 404 405 do { 406 loop = 0; 407 for_each_gpio_chip(gpio, c) { 408 gpio_base = c->chip.base; 409 410 gedr = readl_relaxed(c->regbase + GEDR_OFFSET); 411 gedr = gedr & c->irq_mask; 412 writel_relaxed(gedr, c->regbase + GEDR_OFFSET); 413 414 for_each_set_bit(n, &gedr, BITS_PER_LONG) { 415 loop = 1; 416 417 generic_handle_irq(gpio_to_irq(gpio_base + n)); 418 } 419 } 420 } while (loop); 421 422 chained_irq_exit(chip, desc); 423 } 424 425 static void pxa_ack_muxed_gpio(struct irq_data *d) 426 { 427 int gpio = pxa_irq_to_gpio(d->irq); 428 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); 429 430 writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); 431 } 432 433 static void pxa_mask_muxed_gpio(struct irq_data *d) 434 { 435 int gpio = pxa_irq_to_gpio(d->irq); 436 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); 437 uint32_t grer, gfer; 438 439 c->irq_mask &= ~GPIO_bit(gpio); 440 441 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio); 442 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio); 443 writel_relaxed(grer, c->regbase + GRER_OFFSET); 444 writel_relaxed(gfer, c->regbase + GFER_OFFSET); 445 } 446 447 static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) 448 { 449 int gpio = pxa_irq_to_gpio(d->irq); 450 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); 451 452 if (c->set_wake) 453 return c->set_wake(gpio, on); 454 else 455 return 0; 456 } 457 458 static void pxa_unmask_muxed_gpio(struct irq_data *d) 459 { 460 int gpio = pxa_irq_to_gpio(d->irq); 461 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); 462 463 c->irq_mask |= GPIO_bit(gpio); 464 update_edge_detect(c); 465 } 466 467 static struct irq_chip pxa_muxed_gpio_chip = { 468 .name = "GPIO", 469 .irq_ack = pxa_ack_muxed_gpio, 470 .irq_mask = pxa_mask_muxed_gpio, 471 .irq_unmask = pxa_unmask_muxed_gpio, 472 .irq_set_type = pxa_gpio_irq_type, 473 .irq_set_wake = pxa_gpio_set_wake, 474 }; 475 476 static int pxa_gpio_nums(struct platform_device *pdev) 477 { 478 const struct platform_device_id *id = platform_get_device_id(pdev); 479 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data; 480 int count = 0; 481 482 switch (pxa_id->type) { 483 case PXA25X_GPIO: 484 case PXA26X_GPIO: 485 case PXA27X_GPIO: 486 case PXA3XX_GPIO: 487 case PXA93X_GPIO: 488 case MMP_GPIO: 489 case MMP2_GPIO: 490 gpio_type = pxa_id->type; 491 count = pxa_id->gpio_nums - 1; 492 break; 493 default: 494 count = -EINVAL; 495 break; 496 } 497 return count; 498 } 499 500 #ifdef CONFIG_OF 501 static struct of_device_id pxa_gpio_dt_ids[] = { 502 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, }, 503 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, }, 504 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, }, 505 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, }, 506 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, }, 507 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, }, 508 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, }, 509 {} 510 }; 511 512 static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, 513 irq_hw_number_t hw) 514 { 515 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 516 handle_edge_irq); 517 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 518 return 0; 519 } 520 521 const struct irq_domain_ops pxa_irq_domain_ops = { 522 .map = pxa_irq_domain_map, 523 .xlate = irq_domain_xlate_twocell, 524 }; 525 526 static int pxa_gpio_probe_dt(struct platform_device *pdev) 527 { 528 int ret = 0, nr_gpios; 529 struct device_node *np = pdev->dev.of_node; 530 const struct of_device_id *of_id = 531 of_match_device(pxa_gpio_dt_ids, &pdev->dev); 532 const struct pxa_gpio_id *gpio_id; 533 534 if (!of_id || !of_id->data) { 535 dev_err(&pdev->dev, "Failed to find gpio controller\n"); 536 return -EFAULT; 537 } 538 gpio_id = of_id->data; 539 gpio_type = gpio_id->type; 540 541 nr_gpios = gpio_id->gpio_nums; 542 pxa_last_gpio = nr_gpios - 1; 543 544 irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0); 545 if (irq_base < 0) { 546 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); 547 ret = irq_base; 548 goto err; 549 } 550 domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0, 551 &pxa_irq_domain_ops, NULL); 552 pxa_gpio_of_node = np; 553 return 0; 554 err: 555 iounmap(gpio_reg_base); 556 return ret; 557 } 558 #else 559 #define pxa_gpio_probe_dt(pdev) (-1) 560 #endif 561 562 static int pxa_gpio_probe(struct platform_device *pdev) 563 { 564 struct pxa_gpio_chip *c; 565 struct resource *res; 566 struct clk *clk; 567 struct pxa_gpio_platform_data *info; 568 int gpio, irq, ret, use_of = 0; 569 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; 570 571 info = dev_get_platdata(&pdev->dev); 572 if (info) { 573 irq_base = info->irq_base; 574 if (irq_base <= 0) 575 return -EINVAL; 576 pxa_last_gpio = pxa_gpio_nums(pdev); 577 } else { 578 irq_base = 0; 579 use_of = 1; 580 ret = pxa_gpio_probe_dt(pdev); 581 if (ret < 0) 582 return -EINVAL; 583 } 584 585 if (!pxa_last_gpio) 586 return -EINVAL; 587 588 irq0 = platform_get_irq_byname(pdev, "gpio0"); 589 irq1 = platform_get_irq_byname(pdev, "gpio1"); 590 irq_mux = platform_get_irq_byname(pdev, "gpio_mux"); 591 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0) 592 || (irq_mux <= 0)) 593 return -EINVAL; 594 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 595 if (!res) 596 return -EINVAL; 597 gpio_reg_base = ioremap(res->start, resource_size(res)); 598 if (!gpio_reg_base) 599 return -EINVAL; 600 601 if (irq0 > 0) 602 gpio_offset = 2; 603 604 clk = clk_get(&pdev->dev, NULL); 605 if (IS_ERR(clk)) { 606 dev_err(&pdev->dev, "Error %ld to get gpio clock\n", 607 PTR_ERR(clk)); 608 iounmap(gpio_reg_base); 609 return PTR_ERR(clk); 610 } 611 ret = clk_prepare_enable(clk); 612 if (ret) { 613 clk_put(clk); 614 iounmap(gpio_reg_base); 615 return ret; 616 } 617 618 /* Initialize GPIO chips */ 619 pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL); 620 621 /* clear all GPIO edge detects */ 622 for_each_gpio_chip(gpio, c) { 623 writel_relaxed(0, c->regbase + GFER_OFFSET); 624 writel_relaxed(0, c->regbase + GRER_OFFSET); 625 writel_relaxed(~0, c->regbase + GEDR_OFFSET); 626 /* unmask GPIO edge detect for AP side */ 627 if (gpio_is_mmp_type(gpio_type)) 628 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); 629 } 630 631 if (!use_of) { 632 #ifdef CONFIG_ARCH_PXA 633 irq = gpio_to_irq(0); 634 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 635 handle_edge_irq); 636 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 637 irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler); 638 639 irq = gpio_to_irq(1); 640 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 641 handle_edge_irq); 642 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 643 irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler); 644 #endif 645 646 for (irq = gpio_to_irq(gpio_offset); 647 irq <= gpio_to_irq(pxa_last_gpio); irq++) { 648 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 649 handle_edge_irq); 650 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 651 } 652 } 653 654 irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler); 655 return 0; 656 } 657 658 static const struct platform_device_id gpio_id_table[] = { 659 { "pxa25x-gpio", (unsigned long)&pxa25x_id }, 660 { "pxa26x-gpio", (unsigned long)&pxa26x_id }, 661 { "pxa27x-gpio", (unsigned long)&pxa27x_id }, 662 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id }, 663 { "pxa93x-gpio", (unsigned long)&pxa93x_id }, 664 { "mmp-gpio", (unsigned long)&mmp_id }, 665 { "mmp2-gpio", (unsigned long)&mmp2_id }, 666 { }, 667 }; 668 669 static struct platform_driver pxa_gpio_driver = { 670 .probe = pxa_gpio_probe, 671 .driver = { 672 .name = "pxa-gpio", 673 .of_match_table = of_match_ptr(pxa_gpio_dt_ids), 674 }, 675 .id_table = gpio_id_table, 676 }; 677 678 static int __init pxa_gpio_init(void) 679 { 680 return platform_driver_register(&pxa_gpio_driver); 681 } 682 postcore_initcall(pxa_gpio_init); 683 684 #ifdef CONFIG_PM 685 static int pxa_gpio_suspend(void) 686 { 687 struct pxa_gpio_chip *c; 688 int gpio; 689 690 for_each_gpio_chip(gpio, c) { 691 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET); 692 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); 693 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET); 694 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET); 695 696 /* Clear GPIO transition detect bits */ 697 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET); 698 } 699 return 0; 700 } 701 702 static void pxa_gpio_resume(void) 703 { 704 struct pxa_gpio_chip *c; 705 int gpio; 706 707 for_each_gpio_chip(gpio, c) { 708 /* restore level with set/clear */ 709 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET); 710 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET); 711 712 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET); 713 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET); 714 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET); 715 } 716 } 717 #else 718 #define pxa_gpio_suspend NULL 719 #define pxa_gpio_resume NULL 720 #endif 721 722 struct syscore_ops pxa_gpio_syscore_ops = { 723 .suspend = pxa_gpio_suspend, 724 .resume = pxa_gpio_resume, 725 }; 726 727 static int __init pxa_gpio_sysinit(void) 728 { 729 register_syscore_ops(&pxa_gpio_syscore_ops); 730 return 0; 731 } 732 postcore_initcall(pxa_gpio_sysinit); 733