1 /* 2 * linux/arch/arm/plat-pxa/gpio.c 3 * 4 * Generic PXA GPIO handling 5 * 6 * Author: Nicolas Pitre 7 * Created: Jun 15, 2001 8 * Copyright: MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/module.h> 15 #include <linux/clk.h> 16 #include <linux/err.h> 17 #include <linux/gpio.h> 18 #include <linux/gpio-pxa.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/irq.h> 22 #include <linux/irqdomain.h> 23 #include <linux/irqchip/chained_irq.h> 24 #include <linux/io.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/platform_device.h> 28 #include <linux/syscore_ops.h> 29 #include <linux/slab.h> 30 31 /* 32 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with 33 * one set of registers. The register offsets are organized below: 34 * 35 * GPLR GPDR GPSR GPCR GRER GFER GEDR 36 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 37 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C 38 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 39 * 40 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 41 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C 42 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 43 * 44 * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248 45 * 46 * NOTE: 47 * BANK 3 is only available on PXA27x and later processors. 48 * BANK 4 and 5 are only available on PXA935, PXA1928 49 * BANK 6 is only available on PXA1928 50 */ 51 52 #define GPLR_OFFSET 0x00 53 #define GPDR_OFFSET 0x0C 54 #define GPSR_OFFSET 0x18 55 #define GPCR_OFFSET 0x24 56 #define GRER_OFFSET 0x30 57 #define GFER_OFFSET 0x3C 58 #define GEDR_OFFSET 0x48 59 #define GAFR_OFFSET 0x54 60 #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */ 61 62 #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : ((n) > 5 ? 0x200 : 0x100) \ 63 + (((n) % 3) << 2)) 64 65 int pxa_last_gpio; 66 static int irq_base; 67 68 #ifdef CONFIG_OF 69 static struct irq_domain *domain; 70 static struct device_node *pxa_gpio_of_node; 71 #endif 72 73 struct pxa_gpio_chip { 74 struct gpio_chip chip; 75 void __iomem *regbase; 76 char label[10]; 77 78 unsigned long irq_mask; 79 unsigned long irq_edge_rise; 80 unsigned long irq_edge_fall; 81 int (*set_wake)(unsigned int gpio, unsigned int on); 82 83 #ifdef CONFIG_PM 84 unsigned long saved_gplr; 85 unsigned long saved_gpdr; 86 unsigned long saved_grer; 87 unsigned long saved_gfer; 88 #endif 89 }; 90 91 enum pxa_gpio_type { 92 PXA25X_GPIO = 0, 93 PXA26X_GPIO, 94 PXA27X_GPIO, 95 PXA3XX_GPIO, 96 PXA93X_GPIO, 97 MMP_GPIO = 0x10, 98 MMP2_GPIO, 99 PXA1928_GPIO, 100 }; 101 102 struct pxa_gpio_id { 103 enum pxa_gpio_type type; 104 int gpio_nums; 105 }; 106 107 static DEFINE_SPINLOCK(gpio_lock); 108 static struct pxa_gpio_chip *pxa_gpio_chips; 109 static enum pxa_gpio_type gpio_type; 110 static void __iomem *gpio_reg_base; 111 112 static struct pxa_gpio_id pxa25x_id = { 113 .type = PXA25X_GPIO, 114 .gpio_nums = 85, 115 }; 116 117 static struct pxa_gpio_id pxa26x_id = { 118 .type = PXA26X_GPIO, 119 .gpio_nums = 90, 120 }; 121 122 static struct pxa_gpio_id pxa27x_id = { 123 .type = PXA27X_GPIO, 124 .gpio_nums = 121, 125 }; 126 127 static struct pxa_gpio_id pxa3xx_id = { 128 .type = PXA3XX_GPIO, 129 .gpio_nums = 128, 130 }; 131 132 static struct pxa_gpio_id pxa93x_id = { 133 .type = PXA93X_GPIO, 134 .gpio_nums = 192, 135 }; 136 137 static struct pxa_gpio_id mmp_id = { 138 .type = MMP_GPIO, 139 .gpio_nums = 128, 140 }; 141 142 static struct pxa_gpio_id mmp2_id = { 143 .type = MMP2_GPIO, 144 .gpio_nums = 192, 145 }; 146 147 static struct pxa_gpio_id pxa1928_id = { 148 .type = PXA1928_GPIO, 149 .gpio_nums = 224, 150 }; 151 152 #define for_each_gpio_chip(i, c) \ 153 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++) 154 155 static inline void __iomem *gpio_chip_base(struct gpio_chip *c) 156 { 157 return container_of(c, struct pxa_gpio_chip, chip)->regbase; 158 } 159 160 static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio) 161 { 162 return &pxa_gpio_chips[gpio_to_bank(gpio)]; 163 } 164 165 static inline int gpio_is_pxa_type(int type) 166 { 167 return (type & MMP_GPIO) == 0; 168 } 169 170 static inline int gpio_is_mmp_type(int type) 171 { 172 return (type & MMP_GPIO) != 0; 173 } 174 175 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, 176 * as well as their Alternate Function value being '1' for GPIO in GAFRx. 177 */ 178 static inline int __gpio_is_inverted(int gpio) 179 { 180 if ((gpio_type == PXA26X_GPIO) && (gpio > 85)) 181 return 1; 182 return 0; 183 } 184 185 /* 186 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate 187 * function of a GPIO, and GPDRx cannot be altered once configured. It 188 * is attributed as "occupied" here (I know this terminology isn't 189 * accurate, you are welcome to propose a better one :-) 190 */ 191 static inline int __gpio_is_occupied(unsigned gpio) 192 { 193 struct pxa_gpio_chip *pxachip; 194 void __iomem *base; 195 unsigned long gafr = 0, gpdr = 0; 196 int ret, af = 0, dir = 0; 197 198 pxachip = gpio_to_pxachip(gpio); 199 base = gpio_chip_base(&pxachip->chip); 200 gpdr = readl_relaxed(base + GPDR_OFFSET); 201 202 switch (gpio_type) { 203 case PXA25X_GPIO: 204 case PXA26X_GPIO: 205 case PXA27X_GPIO: 206 gafr = readl_relaxed(base + GAFR_OFFSET); 207 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3; 208 dir = gpdr & GPIO_bit(gpio); 209 210 if (__gpio_is_inverted(gpio)) 211 ret = (af != 1) || (dir == 0); 212 else 213 ret = (af != 0) || (dir != 0); 214 break; 215 default: 216 ret = gpdr & GPIO_bit(gpio); 217 break; 218 } 219 return ret; 220 } 221 222 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 223 { 224 return chip->base + offset + irq_base; 225 } 226 227 int pxa_irq_to_gpio(int irq) 228 { 229 return irq - irq_base; 230 } 231 232 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 233 { 234 void __iomem *base = gpio_chip_base(chip); 235 uint32_t value, mask = 1 << offset; 236 unsigned long flags; 237 238 spin_lock_irqsave(&gpio_lock, flags); 239 240 value = readl_relaxed(base + GPDR_OFFSET); 241 if (__gpio_is_inverted(chip->base + offset)) 242 value |= mask; 243 else 244 value &= ~mask; 245 writel_relaxed(value, base + GPDR_OFFSET); 246 247 spin_unlock_irqrestore(&gpio_lock, flags); 248 return 0; 249 } 250 251 static int pxa_gpio_direction_output(struct gpio_chip *chip, 252 unsigned offset, int value) 253 { 254 void __iomem *base = gpio_chip_base(chip); 255 uint32_t tmp, mask = 1 << offset; 256 unsigned long flags; 257 258 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); 259 260 spin_lock_irqsave(&gpio_lock, flags); 261 262 tmp = readl_relaxed(base + GPDR_OFFSET); 263 if (__gpio_is_inverted(chip->base + offset)) 264 tmp &= ~mask; 265 else 266 tmp |= mask; 267 writel_relaxed(tmp, base + GPDR_OFFSET); 268 269 spin_unlock_irqrestore(&gpio_lock, flags); 270 return 0; 271 } 272 273 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) 274 { 275 u32 gplr = readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET); 276 return !!(gplr & (1 << offset)); 277 } 278 279 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 280 { 281 writel_relaxed(1 << offset, gpio_chip_base(chip) + 282 (value ? GPSR_OFFSET : GPCR_OFFSET)); 283 } 284 285 #ifdef CONFIG_OF_GPIO 286 static int pxa_gpio_of_xlate(struct gpio_chip *gc, 287 const struct of_phandle_args *gpiospec, 288 u32 *flags) 289 { 290 if (gpiospec->args[0] > pxa_last_gpio) 291 return -EINVAL; 292 293 if (gc != &pxa_gpio_chips[gpiospec->args[0] / 32].chip) 294 return -EINVAL; 295 296 if (flags) 297 *flags = gpiospec->args[1]; 298 299 return gpiospec->args[0] % 32; 300 } 301 #endif 302 303 static int pxa_init_gpio_chip(int gpio_end, 304 int (*set_wake)(unsigned int, unsigned int)) 305 { 306 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; 307 struct pxa_gpio_chip *chips; 308 309 chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL); 310 if (chips == NULL) { 311 pr_err("%s: failed to allocate GPIO chips\n", __func__); 312 return -ENOMEM; 313 } 314 315 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { 316 struct gpio_chip *c = &chips[i].chip; 317 318 sprintf(chips[i].label, "gpio-%d", i); 319 chips[i].regbase = gpio_reg_base + BANK_OFF(i); 320 chips[i].set_wake = set_wake; 321 322 c->base = gpio; 323 c->label = chips[i].label; 324 325 c->direction_input = pxa_gpio_direction_input; 326 c->direction_output = pxa_gpio_direction_output; 327 c->get = pxa_gpio_get; 328 c->set = pxa_gpio_set; 329 c->to_irq = pxa_gpio_to_irq; 330 #ifdef CONFIG_OF_GPIO 331 c->of_node = pxa_gpio_of_node; 332 c->of_xlate = pxa_gpio_of_xlate; 333 c->of_gpio_n_cells = 2; 334 #endif 335 336 /* number of GPIOs on last bank may be less than 32 */ 337 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32; 338 gpiochip_add(c); 339 } 340 pxa_gpio_chips = chips; 341 return 0; 342 } 343 344 /* Update only those GRERx and GFERx edge detection register bits if those 345 * bits are set in c->irq_mask 346 */ 347 static inline void update_edge_detect(struct pxa_gpio_chip *c) 348 { 349 uint32_t grer, gfer; 350 351 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; 352 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; 353 grer |= c->irq_edge_rise & c->irq_mask; 354 gfer |= c->irq_edge_fall & c->irq_mask; 355 writel_relaxed(grer, c->regbase + GRER_OFFSET); 356 writel_relaxed(gfer, c->regbase + GFER_OFFSET); 357 } 358 359 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) 360 { 361 struct pxa_gpio_chip *c; 362 int gpio = pxa_irq_to_gpio(d->irq); 363 unsigned long gpdr, mask = GPIO_bit(gpio); 364 365 c = gpio_to_pxachip(gpio); 366 367 if (type == IRQ_TYPE_PROBE) { 368 /* Don't mess with enabled GPIOs using preconfigured edges or 369 * GPIOs set to alternate function or to output during probe 370 */ 371 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) 372 return 0; 373 374 if (__gpio_is_occupied(gpio)) 375 return 0; 376 377 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 378 } 379 380 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); 381 382 if (__gpio_is_inverted(gpio)) 383 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); 384 else 385 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); 386 387 if (type & IRQ_TYPE_EDGE_RISING) 388 c->irq_edge_rise |= mask; 389 else 390 c->irq_edge_rise &= ~mask; 391 392 if (type & IRQ_TYPE_EDGE_FALLING) 393 c->irq_edge_fall |= mask; 394 else 395 c->irq_edge_fall &= ~mask; 396 397 update_edge_detect(c); 398 399 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, 400 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), 401 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); 402 return 0; 403 } 404 405 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) 406 { 407 struct pxa_gpio_chip *c; 408 int loop, gpio, gpio_base, n; 409 unsigned long gedr; 410 struct irq_chip *chip = irq_desc_get_chip(desc); 411 412 chained_irq_enter(chip, desc); 413 414 do { 415 loop = 0; 416 for_each_gpio_chip(gpio, c) { 417 gpio_base = c->chip.base; 418 419 gedr = readl_relaxed(c->regbase + GEDR_OFFSET); 420 gedr = gedr & c->irq_mask; 421 writel_relaxed(gedr, c->regbase + GEDR_OFFSET); 422 423 for_each_set_bit(n, &gedr, BITS_PER_LONG) { 424 loop = 1; 425 426 generic_handle_irq(gpio_to_irq(gpio_base + n)); 427 } 428 } 429 } while (loop); 430 431 chained_irq_exit(chip, desc); 432 } 433 434 static void pxa_ack_muxed_gpio(struct irq_data *d) 435 { 436 int gpio = pxa_irq_to_gpio(d->irq); 437 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); 438 439 writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); 440 } 441 442 static void pxa_mask_muxed_gpio(struct irq_data *d) 443 { 444 int gpio = pxa_irq_to_gpio(d->irq); 445 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); 446 uint32_t grer, gfer; 447 448 c->irq_mask &= ~GPIO_bit(gpio); 449 450 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio); 451 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio); 452 writel_relaxed(grer, c->regbase + GRER_OFFSET); 453 writel_relaxed(gfer, c->regbase + GFER_OFFSET); 454 } 455 456 static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) 457 { 458 int gpio = pxa_irq_to_gpio(d->irq); 459 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); 460 461 if (c->set_wake) 462 return c->set_wake(gpio, on); 463 else 464 return 0; 465 } 466 467 static void pxa_unmask_muxed_gpio(struct irq_data *d) 468 { 469 int gpio = pxa_irq_to_gpio(d->irq); 470 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); 471 472 c->irq_mask |= GPIO_bit(gpio); 473 update_edge_detect(c); 474 } 475 476 static struct irq_chip pxa_muxed_gpio_chip = { 477 .name = "GPIO", 478 .irq_ack = pxa_ack_muxed_gpio, 479 .irq_mask = pxa_mask_muxed_gpio, 480 .irq_unmask = pxa_unmask_muxed_gpio, 481 .irq_set_type = pxa_gpio_irq_type, 482 .irq_set_wake = pxa_gpio_set_wake, 483 }; 484 485 static int pxa_gpio_nums(struct platform_device *pdev) 486 { 487 const struct platform_device_id *id = platform_get_device_id(pdev); 488 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data; 489 int count = 0; 490 491 switch (pxa_id->type) { 492 case PXA25X_GPIO: 493 case PXA26X_GPIO: 494 case PXA27X_GPIO: 495 case PXA3XX_GPIO: 496 case PXA93X_GPIO: 497 case MMP_GPIO: 498 case MMP2_GPIO: 499 case PXA1928_GPIO: 500 gpio_type = pxa_id->type; 501 count = pxa_id->gpio_nums - 1; 502 break; 503 default: 504 count = -EINVAL; 505 break; 506 } 507 return count; 508 } 509 510 #ifdef CONFIG_OF 511 static const struct of_device_id pxa_gpio_dt_ids[] = { 512 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, }, 513 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, }, 514 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, }, 515 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, }, 516 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, }, 517 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, }, 518 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, }, 519 { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, }, 520 {} 521 }; 522 523 static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, 524 irq_hw_number_t hw) 525 { 526 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 527 handle_edge_irq); 528 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 529 return 0; 530 } 531 532 const struct irq_domain_ops pxa_irq_domain_ops = { 533 .map = pxa_irq_domain_map, 534 .xlate = irq_domain_xlate_twocell, 535 }; 536 537 static int pxa_gpio_probe_dt(struct platform_device *pdev) 538 { 539 int ret = 0, nr_gpios; 540 struct device_node *np = pdev->dev.of_node; 541 const struct of_device_id *of_id = 542 of_match_device(pxa_gpio_dt_ids, &pdev->dev); 543 const struct pxa_gpio_id *gpio_id; 544 545 if (!of_id || !of_id->data) { 546 dev_err(&pdev->dev, "Failed to find gpio controller\n"); 547 return -EFAULT; 548 } 549 gpio_id = of_id->data; 550 gpio_type = gpio_id->type; 551 552 nr_gpios = gpio_id->gpio_nums; 553 pxa_last_gpio = nr_gpios - 1; 554 555 irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0); 556 if (irq_base < 0) { 557 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); 558 ret = irq_base; 559 goto err; 560 } 561 domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0, 562 &pxa_irq_domain_ops, NULL); 563 pxa_gpio_of_node = np; 564 return 0; 565 err: 566 iounmap(gpio_reg_base); 567 return ret; 568 } 569 #else 570 #define pxa_gpio_probe_dt(pdev) (-1) 571 #endif 572 573 static int pxa_gpio_probe(struct platform_device *pdev) 574 { 575 struct pxa_gpio_chip *c; 576 struct resource *res; 577 struct clk *clk; 578 struct pxa_gpio_platform_data *info; 579 int gpio, irq, ret, use_of = 0; 580 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; 581 582 info = dev_get_platdata(&pdev->dev); 583 if (info) { 584 irq_base = info->irq_base; 585 if (irq_base <= 0) 586 return -EINVAL; 587 pxa_last_gpio = pxa_gpio_nums(pdev); 588 } else { 589 irq_base = 0; 590 use_of = 1; 591 ret = pxa_gpio_probe_dt(pdev); 592 if (ret < 0) 593 return -EINVAL; 594 } 595 596 if (!pxa_last_gpio) 597 return -EINVAL; 598 599 irq0 = platform_get_irq_byname(pdev, "gpio0"); 600 irq1 = platform_get_irq_byname(pdev, "gpio1"); 601 irq_mux = platform_get_irq_byname(pdev, "gpio_mux"); 602 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0) 603 || (irq_mux <= 0)) 604 return -EINVAL; 605 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 606 if (!res) 607 return -EINVAL; 608 gpio_reg_base = ioremap(res->start, resource_size(res)); 609 if (!gpio_reg_base) 610 return -EINVAL; 611 612 if (irq0 > 0) 613 gpio_offset = 2; 614 615 clk = clk_get(&pdev->dev, NULL); 616 if (IS_ERR(clk)) { 617 dev_err(&pdev->dev, "Error %ld to get gpio clock\n", 618 PTR_ERR(clk)); 619 iounmap(gpio_reg_base); 620 return PTR_ERR(clk); 621 } 622 ret = clk_prepare_enable(clk); 623 if (ret) { 624 clk_put(clk); 625 iounmap(gpio_reg_base); 626 return ret; 627 } 628 629 /* Initialize GPIO chips */ 630 pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL); 631 632 /* clear all GPIO edge detects */ 633 for_each_gpio_chip(gpio, c) { 634 writel_relaxed(0, c->regbase + GFER_OFFSET); 635 writel_relaxed(0, c->regbase + GRER_OFFSET); 636 writel_relaxed(~0, c->regbase + GEDR_OFFSET); 637 /* unmask GPIO edge detect for AP side */ 638 if (gpio_is_mmp_type(gpio_type)) 639 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); 640 } 641 642 if (!use_of) { 643 if (irq0 > 0) { 644 irq = gpio_to_irq(0); 645 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 646 handle_edge_irq); 647 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 648 } 649 if (irq1 > 0) { 650 irq = gpio_to_irq(1); 651 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 652 handle_edge_irq); 653 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 654 } 655 656 for (irq = gpio_to_irq(gpio_offset); 657 irq <= gpio_to_irq(pxa_last_gpio); irq++) { 658 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 659 handle_edge_irq); 660 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 661 } 662 } 663 664 if (irq0 > 0) 665 irq_set_chained_handler(irq0, pxa_gpio_demux_handler); 666 if (irq1 > 0) 667 irq_set_chained_handler(irq1, pxa_gpio_demux_handler); 668 669 irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler); 670 return 0; 671 } 672 673 static const struct platform_device_id gpio_id_table[] = { 674 { "pxa25x-gpio", (unsigned long)&pxa25x_id }, 675 { "pxa26x-gpio", (unsigned long)&pxa26x_id }, 676 { "pxa27x-gpio", (unsigned long)&pxa27x_id }, 677 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id }, 678 { "pxa93x-gpio", (unsigned long)&pxa93x_id }, 679 { "mmp-gpio", (unsigned long)&mmp_id }, 680 { "mmp2-gpio", (unsigned long)&mmp2_id }, 681 { "pxa1928-gpio", (unsigned long)&pxa1928_id }, 682 { }, 683 }; 684 685 static struct platform_driver pxa_gpio_driver = { 686 .probe = pxa_gpio_probe, 687 .driver = { 688 .name = "pxa-gpio", 689 .of_match_table = of_match_ptr(pxa_gpio_dt_ids), 690 }, 691 .id_table = gpio_id_table, 692 }; 693 694 static int __init pxa_gpio_init(void) 695 { 696 return platform_driver_register(&pxa_gpio_driver); 697 } 698 postcore_initcall(pxa_gpio_init); 699 700 #ifdef CONFIG_PM 701 static int pxa_gpio_suspend(void) 702 { 703 struct pxa_gpio_chip *c; 704 int gpio; 705 706 for_each_gpio_chip(gpio, c) { 707 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET); 708 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); 709 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET); 710 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET); 711 712 /* Clear GPIO transition detect bits */ 713 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET); 714 } 715 return 0; 716 } 717 718 static void pxa_gpio_resume(void) 719 { 720 struct pxa_gpio_chip *c; 721 int gpio; 722 723 for_each_gpio_chip(gpio, c) { 724 /* restore level with set/clear */ 725 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET); 726 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET); 727 728 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET); 729 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET); 730 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET); 731 } 732 } 733 #else 734 #define pxa_gpio_suspend NULL 735 #define pxa_gpio_resume NULL 736 #endif 737 738 struct syscore_ops pxa_gpio_syscore_ops = { 739 .suspend = pxa_gpio_suspend, 740 .resume = pxa_gpio_resume, 741 }; 742 743 static int __init pxa_gpio_sysinit(void) 744 { 745 register_syscore_ops(&pxa_gpio_syscore_ops); 746 return 0; 747 } 748 postcore_initcall(pxa_gpio_sysinit); 749