1 /* 2 * linux/arch/arm/plat-pxa/gpio.c 3 * 4 * Generic PXA GPIO handling 5 * 6 * Author: Nicolas Pitre 7 * Created: Jun 15, 2001 8 * Copyright: MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/module.h> 15 #include <linux/clk.h> 16 #include <linux/err.h> 17 #include <linux/gpio.h> 18 #include <linux/gpio-pxa.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/irq.h> 22 #include <linux/irqdomain.h> 23 #include <linux/irqchip/chained_irq.h> 24 #include <linux/io.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/platform_device.h> 29 #include <linux/syscore_ops.h> 30 #include <linux/slab.h> 31 32 /* 33 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with 34 * one set of registers. The register offsets are organized below: 35 * 36 * GPLR GPDR GPSR GPCR GRER GFER GEDR 37 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 38 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C 39 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 40 * 41 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 42 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C 43 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 44 * 45 * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248 46 * 47 * NOTE: 48 * BANK 3 is only available on PXA27x and later processors. 49 * BANK 4 and 5 are only available on PXA935, PXA1928 50 * BANK 6 is only available on PXA1928 51 */ 52 53 #define GPLR_OFFSET 0x00 54 #define GPDR_OFFSET 0x0C 55 #define GPSR_OFFSET 0x18 56 #define GPCR_OFFSET 0x24 57 #define GRER_OFFSET 0x30 58 #define GFER_OFFSET 0x3C 59 #define GEDR_OFFSET 0x48 60 #define GAFR_OFFSET 0x54 61 #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */ 62 63 #define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2) 64 65 int pxa_last_gpio; 66 static int irq_base; 67 68 struct pxa_gpio_bank { 69 void __iomem *regbase; 70 unsigned long irq_mask; 71 unsigned long irq_edge_rise; 72 unsigned long irq_edge_fall; 73 74 #ifdef CONFIG_PM 75 unsigned long saved_gplr; 76 unsigned long saved_gpdr; 77 unsigned long saved_grer; 78 unsigned long saved_gfer; 79 #endif 80 }; 81 82 struct pxa_gpio_chip { 83 struct device *dev; 84 struct gpio_chip chip; 85 struct pxa_gpio_bank *banks; 86 struct irq_domain *irqdomain; 87 88 int irq0; 89 int irq1; 90 int (*set_wake)(unsigned int gpio, unsigned int on); 91 }; 92 93 enum pxa_gpio_type { 94 PXA25X_GPIO = 0, 95 PXA26X_GPIO, 96 PXA27X_GPIO, 97 PXA3XX_GPIO, 98 PXA93X_GPIO, 99 MMP_GPIO = 0x10, 100 MMP2_GPIO, 101 PXA1928_GPIO, 102 }; 103 104 struct pxa_gpio_id { 105 enum pxa_gpio_type type; 106 int gpio_nums; 107 }; 108 109 static DEFINE_SPINLOCK(gpio_lock); 110 static struct pxa_gpio_chip *pxa_gpio_chip; 111 static enum pxa_gpio_type gpio_type; 112 113 static struct pxa_gpio_id pxa25x_id = { 114 .type = PXA25X_GPIO, 115 .gpio_nums = 85, 116 }; 117 118 static struct pxa_gpio_id pxa26x_id = { 119 .type = PXA26X_GPIO, 120 .gpio_nums = 90, 121 }; 122 123 static struct pxa_gpio_id pxa27x_id = { 124 .type = PXA27X_GPIO, 125 .gpio_nums = 121, 126 }; 127 128 static struct pxa_gpio_id pxa3xx_id = { 129 .type = PXA3XX_GPIO, 130 .gpio_nums = 128, 131 }; 132 133 static struct pxa_gpio_id pxa93x_id = { 134 .type = PXA93X_GPIO, 135 .gpio_nums = 192, 136 }; 137 138 static struct pxa_gpio_id mmp_id = { 139 .type = MMP_GPIO, 140 .gpio_nums = 128, 141 }; 142 143 static struct pxa_gpio_id mmp2_id = { 144 .type = MMP2_GPIO, 145 .gpio_nums = 192, 146 }; 147 148 static struct pxa_gpio_id pxa1928_id = { 149 .type = PXA1928_GPIO, 150 .gpio_nums = 224, 151 }; 152 153 #define for_each_gpio_bank(i, b, pc) \ 154 for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++) 155 156 static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c) 157 { 158 struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c); 159 160 return pxa_chip; 161 } 162 163 static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio) 164 { 165 struct pxa_gpio_chip *p = gpiochip_get_data(c); 166 struct pxa_gpio_bank *bank = p->banks + (gpio / 32); 167 168 return bank->regbase; 169 } 170 171 static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c, 172 unsigned gpio) 173 { 174 return chip_to_pxachip(c)->banks + gpio / 32; 175 } 176 177 static inline int gpio_is_pxa_type(int type) 178 { 179 return (type & MMP_GPIO) == 0; 180 } 181 182 static inline int gpio_is_mmp_type(int type) 183 { 184 return (type & MMP_GPIO) != 0; 185 } 186 187 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, 188 * as well as their Alternate Function value being '1' for GPIO in GAFRx. 189 */ 190 static inline int __gpio_is_inverted(int gpio) 191 { 192 if ((gpio_type == PXA26X_GPIO) && (gpio > 85)) 193 return 1; 194 return 0; 195 } 196 197 /* 198 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate 199 * function of a GPIO, and GPDRx cannot be altered once configured. It 200 * is attributed as "occupied" here (I know this terminology isn't 201 * accurate, you are welcome to propose a better one :-) 202 */ 203 static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio) 204 { 205 void __iomem *base; 206 unsigned long gafr = 0, gpdr = 0; 207 int ret, af = 0, dir = 0; 208 209 base = gpio_bank_base(&pchip->chip, gpio); 210 gpdr = readl_relaxed(base + GPDR_OFFSET); 211 212 switch (gpio_type) { 213 case PXA25X_GPIO: 214 case PXA26X_GPIO: 215 case PXA27X_GPIO: 216 gafr = readl_relaxed(base + GAFR_OFFSET); 217 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3; 218 dir = gpdr & GPIO_bit(gpio); 219 220 if (__gpio_is_inverted(gpio)) 221 ret = (af != 1) || (dir == 0); 222 else 223 ret = (af != 0) || (dir != 0); 224 break; 225 default: 226 ret = gpdr & GPIO_bit(gpio); 227 break; 228 } 229 return ret; 230 } 231 232 int pxa_irq_to_gpio(int irq) 233 { 234 struct pxa_gpio_chip *pchip = pxa_gpio_chip; 235 int irq_gpio0; 236 237 irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0); 238 if (irq_gpio0 > 0) 239 return irq - irq_gpio0; 240 241 return irq_gpio0; 242 } 243 244 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 245 { 246 struct pxa_gpio_chip *pchip = chip_to_pxachip(chip); 247 248 return irq_find_mapping(pchip->irqdomain, offset); 249 } 250 251 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 252 { 253 void __iomem *base = gpio_bank_base(chip, offset); 254 uint32_t value, mask = GPIO_bit(offset); 255 unsigned long flags; 256 int ret; 257 258 ret = pinctrl_gpio_direction_input(chip->base + offset); 259 if (!ret) 260 return 0; 261 262 spin_lock_irqsave(&gpio_lock, flags); 263 264 value = readl_relaxed(base + GPDR_OFFSET); 265 if (__gpio_is_inverted(chip->base + offset)) 266 value |= mask; 267 else 268 value &= ~mask; 269 writel_relaxed(value, base + GPDR_OFFSET); 270 271 spin_unlock_irqrestore(&gpio_lock, flags); 272 return 0; 273 } 274 275 static int pxa_gpio_direction_output(struct gpio_chip *chip, 276 unsigned offset, int value) 277 { 278 void __iomem *base = gpio_bank_base(chip, offset); 279 uint32_t tmp, mask = GPIO_bit(offset); 280 unsigned long flags; 281 int ret; 282 283 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); 284 285 ret = pinctrl_gpio_direction_output(chip->base + offset); 286 if (ret) 287 return ret; 288 289 spin_lock_irqsave(&gpio_lock, flags); 290 291 tmp = readl_relaxed(base + GPDR_OFFSET); 292 if (__gpio_is_inverted(chip->base + offset)) 293 tmp &= ~mask; 294 else 295 tmp |= mask; 296 writel_relaxed(tmp, base + GPDR_OFFSET); 297 298 spin_unlock_irqrestore(&gpio_lock, flags); 299 return 0; 300 } 301 302 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) 303 { 304 void __iomem *base = gpio_bank_base(chip, offset); 305 u32 gplr = readl_relaxed(base + GPLR_OFFSET); 306 307 return !!(gplr & GPIO_bit(offset)); 308 } 309 310 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 311 { 312 void __iomem *base = gpio_bank_base(chip, offset); 313 314 writel_relaxed(GPIO_bit(offset), 315 base + (value ? GPSR_OFFSET : GPCR_OFFSET)); 316 } 317 318 #ifdef CONFIG_OF_GPIO 319 static int pxa_gpio_of_xlate(struct gpio_chip *gc, 320 const struct of_phandle_args *gpiospec, 321 u32 *flags) 322 { 323 if (gpiospec->args[0] > pxa_last_gpio) 324 return -EINVAL; 325 326 if (flags) 327 *flags = gpiospec->args[1]; 328 329 return gpiospec->args[0]; 330 } 331 #endif 332 333 static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, 334 struct device_node *np, void __iomem *regbase) 335 { 336 int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32); 337 struct pxa_gpio_bank *bank; 338 339 pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks), 340 GFP_KERNEL); 341 if (!pchip->banks) 342 return -ENOMEM; 343 344 pchip->chip.label = "gpio-pxa"; 345 pchip->chip.direction_input = pxa_gpio_direction_input; 346 pchip->chip.direction_output = pxa_gpio_direction_output; 347 pchip->chip.get = pxa_gpio_get; 348 pchip->chip.set = pxa_gpio_set; 349 pchip->chip.to_irq = pxa_gpio_to_irq; 350 pchip->chip.ngpio = ngpio; 351 pchip->chip.request = gpiochip_generic_request; 352 pchip->chip.free = gpiochip_generic_free; 353 #ifdef CONFIG_OF_GPIO 354 pchip->chip.of_node = np; 355 pchip->chip.of_xlate = pxa_gpio_of_xlate; 356 pchip->chip.of_gpio_n_cells = 2; 357 #endif 358 359 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { 360 bank = pchip->banks + i; 361 bank->regbase = regbase + BANK_OFF(i); 362 } 363 364 return gpiochip_add_data(&pchip->chip, pchip); 365 } 366 367 /* Update only those GRERx and GFERx edge detection register bits if those 368 * bits are set in c->irq_mask 369 */ 370 static inline void update_edge_detect(struct pxa_gpio_bank *c) 371 { 372 uint32_t grer, gfer; 373 374 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; 375 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; 376 grer |= c->irq_edge_rise & c->irq_mask; 377 gfer |= c->irq_edge_fall & c->irq_mask; 378 writel_relaxed(grer, c->regbase + GRER_OFFSET); 379 writel_relaxed(gfer, c->regbase + GFER_OFFSET); 380 } 381 382 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) 383 { 384 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 385 unsigned int gpio = irqd_to_hwirq(d); 386 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); 387 unsigned long gpdr, mask = GPIO_bit(gpio); 388 389 if (type == IRQ_TYPE_PROBE) { 390 /* Don't mess with enabled GPIOs using preconfigured edges or 391 * GPIOs set to alternate function or to output during probe 392 */ 393 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) 394 return 0; 395 396 if (__gpio_is_occupied(pchip, gpio)) 397 return 0; 398 399 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 400 } 401 402 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); 403 404 if (__gpio_is_inverted(gpio)) 405 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); 406 else 407 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); 408 409 if (type & IRQ_TYPE_EDGE_RISING) 410 c->irq_edge_rise |= mask; 411 else 412 c->irq_edge_rise &= ~mask; 413 414 if (type & IRQ_TYPE_EDGE_FALLING) 415 c->irq_edge_fall |= mask; 416 else 417 c->irq_edge_fall &= ~mask; 418 419 update_edge_detect(c); 420 421 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, 422 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), 423 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); 424 return 0; 425 } 426 427 static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d) 428 { 429 int loop, gpio, n, handled = 0; 430 unsigned long gedr; 431 struct pxa_gpio_chip *pchip = d; 432 struct pxa_gpio_bank *c; 433 434 do { 435 loop = 0; 436 for_each_gpio_bank(gpio, c, pchip) { 437 gedr = readl_relaxed(c->regbase + GEDR_OFFSET); 438 gedr = gedr & c->irq_mask; 439 writel_relaxed(gedr, c->regbase + GEDR_OFFSET); 440 441 for_each_set_bit(n, &gedr, BITS_PER_LONG) { 442 loop = 1; 443 444 generic_handle_irq( 445 irq_find_mapping(pchip->irqdomain, 446 gpio + n)); 447 } 448 } 449 handled += loop; 450 } while (loop); 451 452 return handled ? IRQ_HANDLED : IRQ_NONE; 453 } 454 455 static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d) 456 { 457 struct pxa_gpio_chip *pchip = d; 458 459 if (in_irq == pchip->irq0) { 460 generic_handle_irq(irq_find_mapping(pchip->irqdomain, 0)); 461 } else if (in_irq == pchip->irq1) { 462 generic_handle_irq(irq_find_mapping(pchip->irqdomain, 1)); 463 } else { 464 pr_err("%s() unknown irq %d\n", __func__, in_irq); 465 return IRQ_NONE; 466 } 467 return IRQ_HANDLED; 468 } 469 470 static void pxa_ack_muxed_gpio(struct irq_data *d) 471 { 472 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 473 unsigned int gpio = irqd_to_hwirq(d); 474 void __iomem *base = gpio_bank_base(&pchip->chip, gpio); 475 476 writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET); 477 } 478 479 static void pxa_mask_muxed_gpio(struct irq_data *d) 480 { 481 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 482 unsigned int gpio = irqd_to_hwirq(d); 483 struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio); 484 void __iomem *base = gpio_bank_base(&pchip->chip, gpio); 485 uint32_t grer, gfer; 486 487 b->irq_mask &= ~GPIO_bit(gpio); 488 489 grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio); 490 gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio); 491 writel_relaxed(grer, base + GRER_OFFSET); 492 writel_relaxed(gfer, base + GFER_OFFSET); 493 } 494 495 static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) 496 { 497 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 498 unsigned int gpio = irqd_to_hwirq(d); 499 500 if (pchip->set_wake) 501 return pchip->set_wake(gpio, on); 502 else 503 return 0; 504 } 505 506 static void pxa_unmask_muxed_gpio(struct irq_data *d) 507 { 508 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 509 unsigned int gpio = irqd_to_hwirq(d); 510 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); 511 512 c->irq_mask |= GPIO_bit(gpio); 513 update_edge_detect(c); 514 } 515 516 static struct irq_chip pxa_muxed_gpio_chip = { 517 .name = "GPIO", 518 .irq_ack = pxa_ack_muxed_gpio, 519 .irq_mask = pxa_mask_muxed_gpio, 520 .irq_unmask = pxa_unmask_muxed_gpio, 521 .irq_set_type = pxa_gpio_irq_type, 522 .irq_set_wake = pxa_gpio_set_wake, 523 }; 524 525 static int pxa_gpio_nums(struct platform_device *pdev) 526 { 527 const struct platform_device_id *id = platform_get_device_id(pdev); 528 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data; 529 int count = 0; 530 531 switch (pxa_id->type) { 532 case PXA25X_GPIO: 533 case PXA26X_GPIO: 534 case PXA27X_GPIO: 535 case PXA3XX_GPIO: 536 case PXA93X_GPIO: 537 case MMP_GPIO: 538 case MMP2_GPIO: 539 case PXA1928_GPIO: 540 gpio_type = pxa_id->type; 541 count = pxa_id->gpio_nums - 1; 542 break; 543 default: 544 count = -EINVAL; 545 break; 546 } 547 return count; 548 } 549 550 static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, 551 irq_hw_number_t hw) 552 { 553 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 554 handle_edge_irq); 555 irq_set_chip_data(irq, d->host_data); 556 irq_set_noprobe(irq); 557 return 0; 558 } 559 560 const struct irq_domain_ops pxa_irq_domain_ops = { 561 .map = pxa_irq_domain_map, 562 .xlate = irq_domain_xlate_twocell, 563 }; 564 565 #ifdef CONFIG_OF 566 static const struct of_device_id pxa_gpio_dt_ids[] = { 567 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, }, 568 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, }, 569 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, }, 570 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, }, 571 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, }, 572 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, }, 573 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, }, 574 { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, }, 575 {} 576 }; 577 578 static int pxa_gpio_probe_dt(struct platform_device *pdev, 579 struct pxa_gpio_chip *pchip) 580 { 581 int nr_gpios; 582 const struct of_device_id *of_id = 583 of_match_device(pxa_gpio_dt_ids, &pdev->dev); 584 const struct pxa_gpio_id *gpio_id; 585 586 if (!of_id || !of_id->data) { 587 dev_err(&pdev->dev, "Failed to find gpio controller\n"); 588 return -EFAULT; 589 } 590 gpio_id = of_id->data; 591 gpio_type = gpio_id->type; 592 593 nr_gpios = gpio_id->gpio_nums; 594 pxa_last_gpio = nr_gpios - 1; 595 596 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, nr_gpios, 0); 597 if (irq_base < 0) { 598 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); 599 return irq_base; 600 } 601 return irq_base; 602 } 603 #else 604 #define pxa_gpio_probe_dt(pdev, pchip) (-1) 605 #endif 606 607 static int pxa_gpio_probe(struct platform_device *pdev) 608 { 609 struct pxa_gpio_chip *pchip; 610 struct pxa_gpio_bank *c; 611 struct resource *res; 612 struct clk *clk; 613 struct pxa_gpio_platform_data *info; 614 void __iomem *gpio_reg_base; 615 int gpio, ret; 616 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; 617 618 pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL); 619 if (!pchip) 620 return -ENOMEM; 621 pchip->dev = &pdev->dev; 622 623 info = dev_get_platdata(&pdev->dev); 624 if (info) { 625 irq_base = info->irq_base; 626 if (irq_base <= 0) 627 return -EINVAL; 628 pxa_last_gpio = pxa_gpio_nums(pdev); 629 pchip->set_wake = info->gpio_set_wake; 630 } else { 631 irq_base = pxa_gpio_probe_dt(pdev, pchip); 632 if (irq_base < 0) 633 return -EINVAL; 634 } 635 636 if (!pxa_last_gpio) 637 return -EINVAL; 638 639 pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node, 640 pxa_last_gpio + 1, irq_base, 641 0, &pxa_irq_domain_ops, pchip); 642 if (!pchip->irqdomain) 643 return -ENOMEM; 644 645 irq0 = platform_get_irq_byname(pdev, "gpio0"); 646 irq1 = platform_get_irq_byname(pdev, "gpio1"); 647 irq_mux = platform_get_irq_byname(pdev, "gpio_mux"); 648 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0) 649 || (irq_mux <= 0)) 650 return -EINVAL; 651 652 pchip->irq0 = irq0; 653 pchip->irq1 = irq1; 654 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 655 gpio_reg_base = devm_ioremap(&pdev->dev, res->start, 656 resource_size(res)); 657 if (!gpio_reg_base) 658 return -EINVAL; 659 660 if (irq0 > 0) 661 gpio_offset = 2; 662 663 clk = clk_get(&pdev->dev, NULL); 664 if (IS_ERR(clk)) { 665 dev_err(&pdev->dev, "Error %ld to get gpio clock\n", 666 PTR_ERR(clk)); 667 return PTR_ERR(clk); 668 } 669 ret = clk_prepare_enable(clk); 670 if (ret) { 671 clk_put(clk); 672 return ret; 673 } 674 675 /* Initialize GPIO chips */ 676 ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, pdev->dev.of_node, 677 gpio_reg_base); 678 if (ret) { 679 clk_put(clk); 680 return ret; 681 } 682 683 /* clear all GPIO edge detects */ 684 for_each_gpio_bank(gpio, c, pchip) { 685 writel_relaxed(0, c->regbase + GFER_OFFSET); 686 writel_relaxed(0, c->regbase + GRER_OFFSET); 687 writel_relaxed(~0, c->regbase + GEDR_OFFSET); 688 /* unmask GPIO edge detect for AP side */ 689 if (gpio_is_mmp_type(gpio_type)) 690 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); 691 } 692 693 if (irq0 > 0) { 694 ret = devm_request_irq(&pdev->dev, 695 irq0, pxa_gpio_direct_handler, 0, 696 "gpio-0", pchip); 697 if (ret) 698 dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n", 699 ret); 700 } 701 if (irq1 > 0) { 702 ret = devm_request_irq(&pdev->dev, 703 irq1, pxa_gpio_direct_handler, 0, 704 "gpio-1", pchip); 705 if (ret) 706 dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n", 707 ret); 708 } 709 ret = devm_request_irq(&pdev->dev, 710 irq_mux, pxa_gpio_demux_handler, 0, 711 "gpio-mux", pchip); 712 if (ret) 713 dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n", 714 ret); 715 716 pxa_gpio_chip = pchip; 717 718 return 0; 719 } 720 721 static const struct platform_device_id gpio_id_table[] = { 722 { "pxa25x-gpio", (unsigned long)&pxa25x_id }, 723 { "pxa26x-gpio", (unsigned long)&pxa26x_id }, 724 { "pxa27x-gpio", (unsigned long)&pxa27x_id }, 725 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id }, 726 { "pxa93x-gpio", (unsigned long)&pxa93x_id }, 727 { "mmp-gpio", (unsigned long)&mmp_id }, 728 { "mmp2-gpio", (unsigned long)&mmp2_id }, 729 { "pxa1928-gpio", (unsigned long)&pxa1928_id }, 730 { }, 731 }; 732 733 static struct platform_driver pxa_gpio_driver = { 734 .probe = pxa_gpio_probe, 735 .driver = { 736 .name = "pxa-gpio", 737 .of_match_table = of_match_ptr(pxa_gpio_dt_ids), 738 }, 739 .id_table = gpio_id_table, 740 }; 741 742 static int __init pxa_gpio_legacy_init(void) 743 { 744 if (of_have_populated_dt()) 745 return 0; 746 747 return platform_driver_register(&pxa_gpio_driver); 748 } 749 postcore_initcall(pxa_gpio_legacy_init); 750 751 static int __init pxa_gpio_dt_init(void) 752 { 753 if (of_have_populated_dt()) 754 return platform_driver_register(&pxa_gpio_driver); 755 756 return 0; 757 } 758 device_initcall(pxa_gpio_dt_init); 759 760 #ifdef CONFIG_PM 761 static int pxa_gpio_suspend(void) 762 { 763 struct pxa_gpio_chip *pchip = pxa_gpio_chip; 764 struct pxa_gpio_bank *c; 765 int gpio; 766 767 for_each_gpio_bank(gpio, c, pchip) { 768 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET); 769 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); 770 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET); 771 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET); 772 773 /* Clear GPIO transition detect bits */ 774 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET); 775 } 776 return 0; 777 } 778 779 static void pxa_gpio_resume(void) 780 { 781 struct pxa_gpio_chip *pchip = pxa_gpio_chip; 782 struct pxa_gpio_bank *c; 783 int gpio; 784 785 for_each_gpio_bank(gpio, c, pchip) { 786 /* restore level with set/clear */ 787 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET); 788 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET); 789 790 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET); 791 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET); 792 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET); 793 } 794 } 795 #else 796 #define pxa_gpio_suspend NULL 797 #define pxa_gpio_resume NULL 798 #endif 799 800 struct syscore_ops pxa_gpio_syscore_ops = { 801 .suspend = pxa_gpio_suspend, 802 .resume = pxa_gpio_resume, 803 }; 804 805 static int __init pxa_gpio_sysinit(void) 806 { 807 register_syscore_ops(&pxa_gpio_syscore_ops); 808 return 0; 809 } 810 postcore_initcall(pxa_gpio_sysinit); 811