1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2008, 2009 Provigent Ltd. 4 * 5 * Author: Baruch Siach <baruch@tkos.co.il> 6 * 7 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061) 8 * 9 * Data sheet: ARM DDI 0190B, September 2000 10 */ 11 #include <linux/spinlock.h> 12 #include <linux/errno.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/ioport.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/irqchip/chained_irq.h> 19 #include <linux/bitops.h> 20 #include <linux/gpio/driver.h> 21 #include <linux/device.h> 22 #include <linux/amba/bus.h> 23 #include <linux/slab.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/pm.h> 26 27 #define GPIODIR 0x400 28 #define GPIOIS 0x404 29 #define GPIOIBE 0x408 30 #define GPIOIEV 0x40C 31 #define GPIOIE 0x410 32 #define GPIORIS 0x414 33 #define GPIOMIS 0x418 34 #define GPIOIC 0x41C 35 36 #define PL061_GPIO_NR 8 37 38 #ifdef CONFIG_PM 39 struct pl061_context_save_regs { 40 u8 gpio_data; 41 u8 gpio_dir; 42 u8 gpio_is; 43 u8 gpio_ibe; 44 u8 gpio_iev; 45 u8 gpio_ie; 46 }; 47 #endif 48 49 struct pl061 { 50 raw_spinlock_t lock; 51 52 void __iomem *base; 53 struct gpio_chip gc; 54 struct irq_chip irq_chip; 55 int parent_irq; 56 57 #ifdef CONFIG_PM 58 struct pl061_context_save_regs csave_regs; 59 #endif 60 }; 61 62 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) 63 { 64 struct pl061 *pl061 = gpiochip_get_data(gc); 65 66 if (readb(pl061->base + GPIODIR) & BIT(offset)) 67 return GPIO_LINE_DIRECTION_OUT; 68 69 return GPIO_LINE_DIRECTION_IN; 70 } 71 72 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) 73 { 74 struct pl061 *pl061 = gpiochip_get_data(gc); 75 unsigned long flags; 76 unsigned char gpiodir; 77 78 raw_spin_lock_irqsave(&pl061->lock, flags); 79 gpiodir = readb(pl061->base + GPIODIR); 80 gpiodir &= ~(BIT(offset)); 81 writeb(gpiodir, pl061->base + GPIODIR); 82 raw_spin_unlock_irqrestore(&pl061->lock, flags); 83 84 return 0; 85 } 86 87 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, 88 int value) 89 { 90 struct pl061 *pl061 = gpiochip_get_data(gc); 91 unsigned long flags; 92 unsigned char gpiodir; 93 94 raw_spin_lock_irqsave(&pl061->lock, flags); 95 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 96 gpiodir = readb(pl061->base + GPIODIR); 97 gpiodir |= BIT(offset); 98 writeb(gpiodir, pl061->base + GPIODIR); 99 100 /* 101 * gpio value is set again, because pl061 doesn't allow to set value of 102 * a gpio pin before configuring it in OUT mode. 103 */ 104 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 105 raw_spin_unlock_irqrestore(&pl061->lock, flags); 106 107 return 0; 108 } 109 110 static int pl061_get_value(struct gpio_chip *gc, unsigned offset) 111 { 112 struct pl061 *pl061 = gpiochip_get_data(gc); 113 114 return !!readb(pl061->base + (BIT(offset + 2))); 115 } 116 117 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value) 118 { 119 struct pl061 *pl061 = gpiochip_get_data(gc); 120 121 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 122 } 123 124 static int pl061_irq_type(struct irq_data *d, unsigned trigger) 125 { 126 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 127 struct pl061 *pl061 = gpiochip_get_data(gc); 128 int offset = irqd_to_hwirq(d); 129 unsigned long flags; 130 u8 gpiois, gpioibe, gpioiev; 131 u8 bit = BIT(offset); 132 133 if (offset < 0 || offset >= PL061_GPIO_NR) 134 return -EINVAL; 135 136 if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) && 137 (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) 138 { 139 dev_err(gc->parent, 140 "trying to configure line %d for both level and edge " 141 "detection, choose one!\n", 142 offset); 143 return -EINVAL; 144 } 145 146 147 raw_spin_lock_irqsave(&pl061->lock, flags); 148 149 gpioiev = readb(pl061->base + GPIOIEV); 150 gpiois = readb(pl061->base + GPIOIS); 151 gpioibe = readb(pl061->base + GPIOIBE); 152 153 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 154 bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH; 155 156 /* Disable edge detection */ 157 gpioibe &= ~bit; 158 /* Enable level detection */ 159 gpiois |= bit; 160 /* Select polarity */ 161 if (polarity) 162 gpioiev |= bit; 163 else 164 gpioiev &= ~bit; 165 irq_set_handler_locked(d, handle_level_irq); 166 dev_dbg(gc->parent, "line %d: IRQ on %s level\n", 167 offset, 168 polarity ? "HIGH" : "LOW"); 169 } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 170 /* Disable level detection */ 171 gpiois &= ~bit; 172 /* Select both edges, setting this makes GPIOEV be ignored */ 173 gpioibe |= bit; 174 irq_set_handler_locked(d, handle_edge_irq); 175 dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset); 176 } else if ((trigger & IRQ_TYPE_EDGE_RISING) || 177 (trigger & IRQ_TYPE_EDGE_FALLING)) { 178 bool rising = trigger & IRQ_TYPE_EDGE_RISING; 179 180 /* Disable level detection */ 181 gpiois &= ~bit; 182 /* Clear detection on both edges */ 183 gpioibe &= ~bit; 184 /* Select edge */ 185 if (rising) 186 gpioiev |= bit; 187 else 188 gpioiev &= ~bit; 189 irq_set_handler_locked(d, handle_edge_irq); 190 dev_dbg(gc->parent, "line %d: IRQ on %s edge\n", 191 offset, 192 rising ? "RISING" : "FALLING"); 193 } else { 194 /* No trigger: disable everything */ 195 gpiois &= ~bit; 196 gpioibe &= ~bit; 197 gpioiev &= ~bit; 198 irq_set_handler_locked(d, handle_bad_irq); 199 dev_warn(gc->parent, "no trigger selected for line %d\n", 200 offset); 201 } 202 203 writeb(gpiois, pl061->base + GPIOIS); 204 writeb(gpioibe, pl061->base + GPIOIBE); 205 writeb(gpioiev, pl061->base + GPIOIEV); 206 207 raw_spin_unlock_irqrestore(&pl061->lock, flags); 208 209 return 0; 210 } 211 212 static void pl061_irq_handler(struct irq_desc *desc) 213 { 214 unsigned long pending; 215 int offset; 216 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 217 struct pl061 *pl061 = gpiochip_get_data(gc); 218 struct irq_chip *irqchip = irq_desc_get_chip(desc); 219 220 chained_irq_enter(irqchip, desc); 221 222 pending = readb(pl061->base + GPIOMIS); 223 if (pending) { 224 for_each_set_bit(offset, &pending, PL061_GPIO_NR) 225 generic_handle_irq(irq_find_mapping(gc->irq.domain, 226 offset)); 227 } 228 229 chained_irq_exit(irqchip, desc); 230 } 231 232 static void pl061_irq_mask(struct irq_data *d) 233 { 234 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 235 struct pl061 *pl061 = gpiochip_get_data(gc); 236 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 237 u8 gpioie; 238 239 raw_spin_lock(&pl061->lock); 240 gpioie = readb(pl061->base + GPIOIE) & ~mask; 241 writeb(gpioie, pl061->base + GPIOIE); 242 raw_spin_unlock(&pl061->lock); 243 } 244 245 static void pl061_irq_unmask(struct irq_data *d) 246 { 247 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 248 struct pl061 *pl061 = gpiochip_get_data(gc); 249 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 250 u8 gpioie; 251 252 raw_spin_lock(&pl061->lock); 253 gpioie = readb(pl061->base + GPIOIE) | mask; 254 writeb(gpioie, pl061->base + GPIOIE); 255 raw_spin_unlock(&pl061->lock); 256 } 257 258 /** 259 * pl061_irq_ack() - ACK an edge IRQ 260 * @d: IRQ data for this IRQ 261 * 262 * This gets called from the edge IRQ handler to ACK the edge IRQ 263 * in the GPIOIC (interrupt-clear) register. For level IRQs this is 264 * not needed: these go away when the level signal goes away. 265 */ 266 static void pl061_irq_ack(struct irq_data *d) 267 { 268 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 269 struct pl061 *pl061 = gpiochip_get_data(gc); 270 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 271 272 raw_spin_lock(&pl061->lock); 273 writeb(mask, pl061->base + GPIOIC); 274 raw_spin_unlock(&pl061->lock); 275 } 276 277 static int pl061_irq_set_wake(struct irq_data *d, unsigned int state) 278 { 279 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 280 struct pl061 *pl061 = gpiochip_get_data(gc); 281 282 return irq_set_irq_wake(pl061->parent_irq, state); 283 } 284 285 static int pl061_probe(struct amba_device *adev, const struct amba_id *id) 286 { 287 struct device *dev = &adev->dev; 288 struct pl061 *pl061; 289 struct gpio_irq_chip *girq; 290 int ret, irq; 291 292 pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); 293 if (pl061 == NULL) 294 return -ENOMEM; 295 296 pl061->base = devm_ioremap_resource(dev, &adev->res); 297 if (IS_ERR(pl061->base)) 298 return PTR_ERR(pl061->base); 299 300 raw_spin_lock_init(&pl061->lock); 301 pl061->gc.request = gpiochip_generic_request; 302 pl061->gc.free = gpiochip_generic_free; 303 pl061->gc.base = -1; 304 pl061->gc.get_direction = pl061_get_direction; 305 pl061->gc.direction_input = pl061_direction_input; 306 pl061->gc.direction_output = pl061_direction_output; 307 pl061->gc.get = pl061_get_value; 308 pl061->gc.set = pl061_set_value; 309 pl061->gc.ngpio = PL061_GPIO_NR; 310 pl061->gc.label = dev_name(dev); 311 pl061->gc.parent = dev; 312 pl061->gc.owner = THIS_MODULE; 313 314 /* 315 * irq_chip support 316 */ 317 pl061->irq_chip.name = dev_name(dev); 318 pl061->irq_chip.irq_ack = pl061_irq_ack; 319 pl061->irq_chip.irq_mask = pl061_irq_mask; 320 pl061->irq_chip.irq_unmask = pl061_irq_unmask; 321 pl061->irq_chip.irq_set_type = pl061_irq_type; 322 pl061->irq_chip.irq_set_wake = pl061_irq_set_wake; 323 324 writeb(0, pl061->base + GPIOIE); /* disable irqs */ 325 irq = adev->irq[0]; 326 if (!irq) 327 dev_warn(&adev->dev, "IRQ support disabled\n"); 328 pl061->parent_irq = irq; 329 330 girq = &pl061->gc.irq; 331 girq->chip = &pl061->irq_chip; 332 girq->parent_handler = pl061_irq_handler; 333 girq->num_parents = 1; 334 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 335 GFP_KERNEL); 336 if (!girq->parents) 337 return -ENOMEM; 338 girq->parents[0] = irq; 339 girq->default_type = IRQ_TYPE_NONE; 340 girq->handler = handle_bad_irq; 341 342 ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061); 343 if (ret) 344 return ret; 345 346 amba_set_drvdata(adev, pl061); 347 dev_info(dev, "PL061 GPIO chip registered\n"); 348 349 return 0; 350 } 351 352 #ifdef CONFIG_PM 353 static int pl061_suspend(struct device *dev) 354 { 355 struct pl061 *pl061 = dev_get_drvdata(dev); 356 int offset; 357 358 pl061->csave_regs.gpio_data = 0; 359 pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR); 360 pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS); 361 pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE); 362 pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV); 363 pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE); 364 365 for (offset = 0; offset < PL061_GPIO_NR; offset++) { 366 if (pl061->csave_regs.gpio_dir & (BIT(offset))) 367 pl061->csave_regs.gpio_data |= 368 pl061_get_value(&pl061->gc, offset) << offset; 369 } 370 371 return 0; 372 } 373 374 static int pl061_resume(struct device *dev) 375 { 376 struct pl061 *pl061 = dev_get_drvdata(dev); 377 int offset; 378 379 for (offset = 0; offset < PL061_GPIO_NR; offset++) { 380 if (pl061->csave_regs.gpio_dir & (BIT(offset))) 381 pl061_direction_output(&pl061->gc, offset, 382 pl061->csave_regs.gpio_data & 383 (BIT(offset))); 384 else 385 pl061_direction_input(&pl061->gc, offset); 386 } 387 388 writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); 389 writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); 390 writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); 391 writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); 392 393 return 0; 394 } 395 396 static const struct dev_pm_ops pl061_dev_pm_ops = { 397 .suspend = pl061_suspend, 398 .resume = pl061_resume, 399 .freeze = pl061_suspend, 400 .restore = pl061_resume, 401 }; 402 #endif 403 404 static const struct amba_id pl061_ids[] = { 405 { 406 .id = 0x00041061, 407 .mask = 0x000fffff, 408 }, 409 { 0, 0 }, 410 }; 411 412 static struct amba_driver pl061_gpio_driver = { 413 .drv = { 414 .name = "pl061_gpio", 415 #ifdef CONFIG_PM 416 .pm = &pl061_dev_pm_ops, 417 #endif 418 }, 419 .id_table = pl061_ids, 420 .probe = pl061_probe, 421 }; 422 423 static int __init pl061_gpio_init(void) 424 { 425 return amba_driver_register(&pl061_gpio_driver); 426 } 427 device_initcall(pl061_gpio_init); 428