1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2008, 2009 Provigent Ltd. 4 * 5 * Author: Baruch Siach <baruch@tkos.co.il> 6 * 7 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061) 8 * 9 * Data sheet: ARM DDI 0190B, September 2000 10 */ 11 #include <linux/spinlock.h> 12 #include <linux/errno.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/ioport.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/irqchip/chained_irq.h> 19 #include <linux/bitops.h> 20 #include <linux/gpio/driver.h> 21 #include <linux/device.h> 22 #include <linux/amba/bus.h> 23 #include <linux/slab.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/pm.h> 26 27 #define GPIODIR 0x400 28 #define GPIOIS 0x404 29 #define GPIOIBE 0x408 30 #define GPIOIEV 0x40C 31 #define GPIOIE 0x410 32 #define GPIORIS 0x414 33 #define GPIOMIS 0x418 34 #define GPIOIC 0x41C 35 36 #define PL061_GPIO_NR 8 37 38 #ifdef CONFIG_PM 39 struct pl061_context_save_regs { 40 u8 gpio_data; 41 u8 gpio_dir; 42 u8 gpio_is; 43 u8 gpio_ibe; 44 u8 gpio_iev; 45 u8 gpio_ie; 46 }; 47 #endif 48 49 struct pl061 { 50 raw_spinlock_t lock; 51 52 void __iomem *base; 53 struct gpio_chip gc; 54 struct irq_chip irq_chip; 55 int parent_irq; 56 57 #ifdef CONFIG_PM 58 struct pl061_context_save_regs csave_regs; 59 #endif 60 }; 61 62 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) 63 { 64 struct pl061 *pl061 = gpiochip_get_data(gc); 65 66 return !(readb(pl061->base + GPIODIR) & BIT(offset)); 67 } 68 69 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) 70 { 71 struct pl061 *pl061 = gpiochip_get_data(gc); 72 unsigned long flags; 73 unsigned char gpiodir; 74 75 raw_spin_lock_irqsave(&pl061->lock, flags); 76 gpiodir = readb(pl061->base + GPIODIR); 77 gpiodir &= ~(BIT(offset)); 78 writeb(gpiodir, pl061->base + GPIODIR); 79 raw_spin_unlock_irqrestore(&pl061->lock, flags); 80 81 return 0; 82 } 83 84 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, 85 int value) 86 { 87 struct pl061 *pl061 = gpiochip_get_data(gc); 88 unsigned long flags; 89 unsigned char gpiodir; 90 91 raw_spin_lock_irqsave(&pl061->lock, flags); 92 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 93 gpiodir = readb(pl061->base + GPIODIR); 94 gpiodir |= BIT(offset); 95 writeb(gpiodir, pl061->base + GPIODIR); 96 97 /* 98 * gpio value is set again, because pl061 doesn't allow to set value of 99 * a gpio pin before configuring it in OUT mode. 100 */ 101 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 102 raw_spin_unlock_irqrestore(&pl061->lock, flags); 103 104 return 0; 105 } 106 107 static int pl061_get_value(struct gpio_chip *gc, unsigned offset) 108 { 109 struct pl061 *pl061 = gpiochip_get_data(gc); 110 111 return !!readb(pl061->base + (BIT(offset + 2))); 112 } 113 114 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value) 115 { 116 struct pl061 *pl061 = gpiochip_get_data(gc); 117 118 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 119 } 120 121 static int pl061_irq_type(struct irq_data *d, unsigned trigger) 122 { 123 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 124 struct pl061 *pl061 = gpiochip_get_data(gc); 125 int offset = irqd_to_hwirq(d); 126 unsigned long flags; 127 u8 gpiois, gpioibe, gpioiev; 128 u8 bit = BIT(offset); 129 130 if (offset < 0 || offset >= PL061_GPIO_NR) 131 return -EINVAL; 132 133 if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) && 134 (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) 135 { 136 dev_err(gc->parent, 137 "trying to configure line %d for both level and edge " 138 "detection, choose one!\n", 139 offset); 140 return -EINVAL; 141 } 142 143 144 raw_spin_lock_irqsave(&pl061->lock, flags); 145 146 gpioiev = readb(pl061->base + GPIOIEV); 147 gpiois = readb(pl061->base + GPIOIS); 148 gpioibe = readb(pl061->base + GPIOIBE); 149 150 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 151 bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH; 152 153 /* Disable edge detection */ 154 gpioibe &= ~bit; 155 /* Enable level detection */ 156 gpiois |= bit; 157 /* Select polarity */ 158 if (polarity) 159 gpioiev |= bit; 160 else 161 gpioiev &= ~bit; 162 irq_set_handler_locked(d, handle_level_irq); 163 dev_dbg(gc->parent, "line %d: IRQ on %s level\n", 164 offset, 165 polarity ? "HIGH" : "LOW"); 166 } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 167 /* Disable level detection */ 168 gpiois &= ~bit; 169 /* Select both edges, setting this makes GPIOEV be ignored */ 170 gpioibe |= bit; 171 irq_set_handler_locked(d, handle_edge_irq); 172 dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset); 173 } else if ((trigger & IRQ_TYPE_EDGE_RISING) || 174 (trigger & IRQ_TYPE_EDGE_FALLING)) { 175 bool rising = trigger & IRQ_TYPE_EDGE_RISING; 176 177 /* Disable level detection */ 178 gpiois &= ~bit; 179 /* Clear detection on both edges */ 180 gpioibe &= ~bit; 181 /* Select edge */ 182 if (rising) 183 gpioiev |= bit; 184 else 185 gpioiev &= ~bit; 186 irq_set_handler_locked(d, handle_edge_irq); 187 dev_dbg(gc->parent, "line %d: IRQ on %s edge\n", 188 offset, 189 rising ? "RISING" : "FALLING"); 190 } else { 191 /* No trigger: disable everything */ 192 gpiois &= ~bit; 193 gpioibe &= ~bit; 194 gpioiev &= ~bit; 195 irq_set_handler_locked(d, handle_bad_irq); 196 dev_warn(gc->parent, "no trigger selected for line %d\n", 197 offset); 198 } 199 200 writeb(gpiois, pl061->base + GPIOIS); 201 writeb(gpioibe, pl061->base + GPIOIBE); 202 writeb(gpioiev, pl061->base + GPIOIEV); 203 204 raw_spin_unlock_irqrestore(&pl061->lock, flags); 205 206 return 0; 207 } 208 209 static void pl061_irq_handler(struct irq_desc *desc) 210 { 211 unsigned long pending; 212 int offset; 213 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 214 struct pl061 *pl061 = gpiochip_get_data(gc); 215 struct irq_chip *irqchip = irq_desc_get_chip(desc); 216 217 chained_irq_enter(irqchip, desc); 218 219 pending = readb(pl061->base + GPIOMIS); 220 if (pending) { 221 for_each_set_bit(offset, &pending, PL061_GPIO_NR) 222 generic_handle_irq(irq_find_mapping(gc->irq.domain, 223 offset)); 224 } 225 226 chained_irq_exit(irqchip, desc); 227 } 228 229 static void pl061_irq_mask(struct irq_data *d) 230 { 231 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 232 struct pl061 *pl061 = gpiochip_get_data(gc); 233 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 234 u8 gpioie; 235 236 raw_spin_lock(&pl061->lock); 237 gpioie = readb(pl061->base + GPIOIE) & ~mask; 238 writeb(gpioie, pl061->base + GPIOIE); 239 raw_spin_unlock(&pl061->lock); 240 } 241 242 static void pl061_irq_unmask(struct irq_data *d) 243 { 244 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 245 struct pl061 *pl061 = gpiochip_get_data(gc); 246 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 247 u8 gpioie; 248 249 raw_spin_lock(&pl061->lock); 250 gpioie = readb(pl061->base + GPIOIE) | mask; 251 writeb(gpioie, pl061->base + GPIOIE); 252 raw_spin_unlock(&pl061->lock); 253 } 254 255 /** 256 * pl061_irq_ack() - ACK an edge IRQ 257 * @d: IRQ data for this IRQ 258 * 259 * This gets called from the edge IRQ handler to ACK the edge IRQ 260 * in the GPIOIC (interrupt-clear) register. For level IRQs this is 261 * not needed: these go away when the level signal goes away. 262 */ 263 static void pl061_irq_ack(struct irq_data *d) 264 { 265 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 266 struct pl061 *pl061 = gpiochip_get_data(gc); 267 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 268 269 raw_spin_lock(&pl061->lock); 270 writeb(mask, pl061->base + GPIOIC); 271 raw_spin_unlock(&pl061->lock); 272 } 273 274 static int pl061_irq_set_wake(struct irq_data *d, unsigned int state) 275 { 276 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 277 struct pl061 *pl061 = gpiochip_get_data(gc); 278 279 return irq_set_irq_wake(pl061->parent_irq, state); 280 } 281 282 static int pl061_probe(struct amba_device *adev, const struct amba_id *id) 283 { 284 struct device *dev = &adev->dev; 285 struct pl061 *pl061; 286 struct gpio_irq_chip *girq; 287 int ret, irq; 288 289 pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); 290 if (pl061 == NULL) 291 return -ENOMEM; 292 293 pl061->base = devm_ioremap_resource(dev, &adev->res); 294 if (IS_ERR(pl061->base)) 295 return PTR_ERR(pl061->base); 296 297 raw_spin_lock_init(&pl061->lock); 298 if (of_property_read_bool(dev->of_node, "gpio-ranges")) { 299 pl061->gc.request = gpiochip_generic_request; 300 pl061->gc.free = gpiochip_generic_free; 301 } 302 303 pl061->gc.base = -1; 304 pl061->gc.get_direction = pl061_get_direction; 305 pl061->gc.direction_input = pl061_direction_input; 306 pl061->gc.direction_output = pl061_direction_output; 307 pl061->gc.get = pl061_get_value; 308 pl061->gc.set = pl061_set_value; 309 pl061->gc.ngpio = PL061_GPIO_NR; 310 pl061->gc.label = dev_name(dev); 311 pl061->gc.parent = dev; 312 pl061->gc.owner = THIS_MODULE; 313 314 /* 315 * irq_chip support 316 */ 317 pl061->irq_chip.name = dev_name(dev); 318 pl061->irq_chip.irq_ack = pl061_irq_ack; 319 pl061->irq_chip.irq_mask = pl061_irq_mask; 320 pl061->irq_chip.irq_unmask = pl061_irq_unmask; 321 pl061->irq_chip.irq_set_type = pl061_irq_type; 322 pl061->irq_chip.irq_set_wake = pl061_irq_set_wake; 323 324 writeb(0, pl061->base + GPIOIE); /* disable irqs */ 325 irq = adev->irq[0]; 326 if (irq < 0) { 327 dev_err(&adev->dev, "invalid IRQ\n"); 328 return -ENODEV; 329 } 330 pl061->parent_irq = irq; 331 332 girq = &pl061->gc.irq; 333 girq->chip = &pl061->irq_chip; 334 girq->parent_handler = pl061_irq_handler; 335 girq->num_parents = 1; 336 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 337 GFP_KERNEL); 338 if (!girq->parents) 339 return -ENOMEM; 340 girq->parents[0] = irq; 341 girq->default_type = IRQ_TYPE_NONE; 342 girq->handler = handle_bad_irq; 343 344 ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061); 345 if (ret) 346 return ret; 347 348 amba_set_drvdata(adev, pl061); 349 dev_info(dev, "PL061 GPIO chip registered\n"); 350 351 return 0; 352 } 353 354 #ifdef CONFIG_PM 355 static int pl061_suspend(struct device *dev) 356 { 357 struct pl061 *pl061 = dev_get_drvdata(dev); 358 int offset; 359 360 pl061->csave_regs.gpio_data = 0; 361 pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR); 362 pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS); 363 pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE); 364 pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV); 365 pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE); 366 367 for (offset = 0; offset < PL061_GPIO_NR; offset++) { 368 if (pl061->csave_regs.gpio_dir & (BIT(offset))) 369 pl061->csave_regs.gpio_data |= 370 pl061_get_value(&pl061->gc, offset) << offset; 371 } 372 373 return 0; 374 } 375 376 static int pl061_resume(struct device *dev) 377 { 378 struct pl061 *pl061 = dev_get_drvdata(dev); 379 int offset; 380 381 for (offset = 0; offset < PL061_GPIO_NR; offset++) { 382 if (pl061->csave_regs.gpio_dir & (BIT(offset))) 383 pl061_direction_output(&pl061->gc, offset, 384 pl061->csave_regs.gpio_data & 385 (BIT(offset))); 386 else 387 pl061_direction_input(&pl061->gc, offset); 388 } 389 390 writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); 391 writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); 392 writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); 393 writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); 394 395 return 0; 396 } 397 398 static const struct dev_pm_ops pl061_dev_pm_ops = { 399 .suspend = pl061_suspend, 400 .resume = pl061_resume, 401 .freeze = pl061_suspend, 402 .restore = pl061_resume, 403 }; 404 #endif 405 406 static const struct amba_id pl061_ids[] = { 407 { 408 .id = 0x00041061, 409 .mask = 0x000fffff, 410 }, 411 { 0, 0 }, 412 }; 413 414 static struct amba_driver pl061_gpio_driver = { 415 .drv = { 416 .name = "pl061_gpio", 417 #ifdef CONFIG_PM 418 .pm = &pl061_dev_pm_ops, 419 #endif 420 }, 421 .id_table = pl061_ids, 422 .probe = pl061_probe, 423 }; 424 425 static int __init pl061_gpio_init(void) 426 { 427 return amba_driver_register(&pl061_gpio_driver); 428 } 429 device_initcall(pl061_gpio_init); 430