1 /* 2 * Copyright (C) 2008, 2009 Provigent Ltd. 3 * 4 * Author: Baruch Siach <baruch@tkos.co.il> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061) 11 * 12 * Data sheet: ARM DDI 0190B, September 2000 13 */ 14 #include <linux/spinlock.h> 15 #include <linux/errno.h> 16 #include <linux/init.h> 17 #include <linux/io.h> 18 #include <linux/ioport.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqchip/chained_irq.h> 22 #include <linux/bitops.h> 23 #include <linux/gpio.h> 24 #include <linux/device.h> 25 #include <linux/amba/bus.h> 26 #include <linux/slab.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/pm.h> 29 30 #define GPIODIR 0x400 31 #define GPIOIS 0x404 32 #define GPIOIBE 0x408 33 #define GPIOIEV 0x40C 34 #define GPIOIE 0x410 35 #define GPIORIS 0x414 36 #define GPIOMIS 0x418 37 #define GPIOIC 0x41C 38 39 #define PL061_GPIO_NR 8 40 41 #ifdef CONFIG_PM 42 struct pl061_context_save_regs { 43 u8 gpio_data; 44 u8 gpio_dir; 45 u8 gpio_is; 46 u8 gpio_ibe; 47 u8 gpio_iev; 48 u8 gpio_ie; 49 }; 50 #endif 51 52 struct pl061 { 53 raw_spinlock_t lock; 54 55 void __iomem *base; 56 struct gpio_chip gc; 57 int parent_irq; 58 59 #ifdef CONFIG_PM 60 struct pl061_context_save_regs csave_regs; 61 #endif 62 }; 63 64 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) 65 { 66 struct pl061 *pl061 = gpiochip_get_data(gc); 67 68 return !(readb(pl061->base + GPIODIR) & BIT(offset)); 69 } 70 71 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) 72 { 73 struct pl061 *pl061 = gpiochip_get_data(gc); 74 unsigned long flags; 75 unsigned char gpiodir; 76 77 raw_spin_lock_irqsave(&pl061->lock, flags); 78 gpiodir = readb(pl061->base + GPIODIR); 79 gpiodir &= ~(BIT(offset)); 80 writeb(gpiodir, pl061->base + GPIODIR); 81 raw_spin_unlock_irqrestore(&pl061->lock, flags); 82 83 return 0; 84 } 85 86 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, 87 int value) 88 { 89 struct pl061 *pl061 = gpiochip_get_data(gc); 90 unsigned long flags; 91 unsigned char gpiodir; 92 93 raw_spin_lock_irqsave(&pl061->lock, flags); 94 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 95 gpiodir = readb(pl061->base + GPIODIR); 96 gpiodir |= BIT(offset); 97 writeb(gpiodir, pl061->base + GPIODIR); 98 99 /* 100 * gpio value is set again, because pl061 doesn't allow to set value of 101 * a gpio pin before configuring it in OUT mode. 102 */ 103 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 104 raw_spin_unlock_irqrestore(&pl061->lock, flags); 105 106 return 0; 107 } 108 109 static int pl061_get_value(struct gpio_chip *gc, unsigned offset) 110 { 111 struct pl061 *pl061 = gpiochip_get_data(gc); 112 113 return !!readb(pl061->base + (BIT(offset + 2))); 114 } 115 116 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value) 117 { 118 struct pl061 *pl061 = gpiochip_get_data(gc); 119 120 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 121 } 122 123 static int pl061_irq_type(struct irq_data *d, unsigned trigger) 124 { 125 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 126 struct pl061 *pl061 = gpiochip_get_data(gc); 127 int offset = irqd_to_hwirq(d); 128 unsigned long flags; 129 u8 gpiois, gpioibe, gpioiev; 130 u8 bit = BIT(offset); 131 132 if (offset < 0 || offset >= PL061_GPIO_NR) 133 return -EINVAL; 134 135 if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) && 136 (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) 137 { 138 dev_err(gc->parent, 139 "trying to configure line %d for both level and edge " 140 "detection, choose one!\n", 141 offset); 142 return -EINVAL; 143 } 144 145 146 raw_spin_lock_irqsave(&pl061->lock, flags); 147 148 gpioiev = readb(pl061->base + GPIOIEV); 149 gpiois = readb(pl061->base + GPIOIS); 150 gpioibe = readb(pl061->base + GPIOIBE); 151 152 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 153 bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH; 154 155 /* Disable edge detection */ 156 gpioibe &= ~bit; 157 /* Enable level detection */ 158 gpiois |= bit; 159 /* Select polarity */ 160 if (polarity) 161 gpioiev |= bit; 162 else 163 gpioiev &= ~bit; 164 irq_set_handler_locked(d, handle_level_irq); 165 dev_dbg(gc->parent, "line %d: IRQ on %s level\n", 166 offset, 167 polarity ? "HIGH" : "LOW"); 168 } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 169 /* Disable level detection */ 170 gpiois &= ~bit; 171 /* Select both edges, setting this makes GPIOEV be ignored */ 172 gpioibe |= bit; 173 irq_set_handler_locked(d, handle_edge_irq); 174 dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset); 175 } else if ((trigger & IRQ_TYPE_EDGE_RISING) || 176 (trigger & IRQ_TYPE_EDGE_FALLING)) { 177 bool rising = trigger & IRQ_TYPE_EDGE_RISING; 178 179 /* Disable level detection */ 180 gpiois &= ~bit; 181 /* Clear detection on both edges */ 182 gpioibe &= ~bit; 183 /* Select edge */ 184 if (rising) 185 gpioiev |= bit; 186 else 187 gpioiev &= ~bit; 188 irq_set_handler_locked(d, handle_edge_irq); 189 dev_dbg(gc->parent, "line %d: IRQ on %s edge\n", 190 offset, 191 rising ? "RISING" : "FALLING"); 192 } else { 193 /* No trigger: disable everything */ 194 gpiois &= ~bit; 195 gpioibe &= ~bit; 196 gpioiev &= ~bit; 197 irq_set_handler_locked(d, handle_bad_irq); 198 dev_warn(gc->parent, "no trigger selected for line %d\n", 199 offset); 200 } 201 202 writeb(gpiois, pl061->base + GPIOIS); 203 writeb(gpioibe, pl061->base + GPIOIBE); 204 writeb(gpioiev, pl061->base + GPIOIEV); 205 206 raw_spin_unlock_irqrestore(&pl061->lock, flags); 207 208 return 0; 209 } 210 211 static void pl061_irq_handler(struct irq_desc *desc) 212 { 213 unsigned long pending; 214 int offset; 215 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 216 struct pl061 *pl061 = gpiochip_get_data(gc); 217 struct irq_chip *irqchip = irq_desc_get_chip(desc); 218 219 chained_irq_enter(irqchip, desc); 220 221 pending = readb(pl061->base + GPIOMIS); 222 if (pending) { 223 for_each_set_bit(offset, &pending, PL061_GPIO_NR) 224 generic_handle_irq(irq_find_mapping(gc->irq.domain, 225 offset)); 226 } 227 228 chained_irq_exit(irqchip, desc); 229 } 230 231 static void pl061_irq_mask(struct irq_data *d) 232 { 233 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 234 struct pl061 *pl061 = gpiochip_get_data(gc); 235 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 236 u8 gpioie; 237 238 raw_spin_lock(&pl061->lock); 239 gpioie = readb(pl061->base + GPIOIE) & ~mask; 240 writeb(gpioie, pl061->base + GPIOIE); 241 raw_spin_unlock(&pl061->lock); 242 } 243 244 static void pl061_irq_unmask(struct irq_data *d) 245 { 246 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 247 struct pl061 *pl061 = gpiochip_get_data(gc); 248 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 249 u8 gpioie; 250 251 raw_spin_lock(&pl061->lock); 252 gpioie = readb(pl061->base + GPIOIE) | mask; 253 writeb(gpioie, pl061->base + GPIOIE); 254 raw_spin_unlock(&pl061->lock); 255 } 256 257 /** 258 * pl061_irq_ack() - ACK an edge IRQ 259 * @d: IRQ data for this IRQ 260 * 261 * This gets called from the edge IRQ handler to ACK the edge IRQ 262 * in the GPIOIC (interrupt-clear) register. For level IRQs this is 263 * not needed: these go away when the level signal goes away. 264 */ 265 static void pl061_irq_ack(struct irq_data *d) 266 { 267 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 268 struct pl061 *pl061 = gpiochip_get_data(gc); 269 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 270 271 raw_spin_lock(&pl061->lock); 272 writeb(mask, pl061->base + GPIOIC); 273 raw_spin_unlock(&pl061->lock); 274 } 275 276 static int pl061_irq_set_wake(struct irq_data *d, unsigned int state) 277 { 278 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 279 struct pl061 *pl061 = gpiochip_get_data(gc); 280 281 return irq_set_irq_wake(pl061->parent_irq, state); 282 } 283 284 static struct irq_chip pl061_irqchip = { 285 .name = "pl061", 286 .irq_ack = pl061_irq_ack, 287 .irq_mask = pl061_irq_mask, 288 .irq_unmask = pl061_irq_unmask, 289 .irq_set_type = pl061_irq_type, 290 .irq_set_wake = pl061_irq_set_wake, 291 }; 292 293 static int pl061_probe(struct amba_device *adev, const struct amba_id *id) 294 { 295 struct device *dev = &adev->dev; 296 struct pl061 *pl061; 297 int ret, irq; 298 299 pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); 300 if (pl061 == NULL) 301 return -ENOMEM; 302 303 pl061->base = devm_ioremap_resource(dev, &adev->res); 304 if (IS_ERR(pl061->base)) 305 return PTR_ERR(pl061->base); 306 307 raw_spin_lock_init(&pl061->lock); 308 if (of_property_read_bool(dev->of_node, "gpio-ranges")) { 309 pl061->gc.request = gpiochip_generic_request; 310 pl061->gc.free = gpiochip_generic_free; 311 } 312 313 pl061->gc.base = -1; 314 pl061->gc.get_direction = pl061_get_direction; 315 pl061->gc.direction_input = pl061_direction_input; 316 pl061->gc.direction_output = pl061_direction_output; 317 pl061->gc.get = pl061_get_value; 318 pl061->gc.set = pl061_set_value; 319 pl061->gc.ngpio = PL061_GPIO_NR; 320 pl061->gc.label = dev_name(dev); 321 pl061->gc.parent = dev; 322 pl061->gc.owner = THIS_MODULE; 323 324 ret = gpiochip_add_data(&pl061->gc, pl061); 325 if (ret) 326 return ret; 327 328 /* 329 * irq_chip support 330 */ 331 writeb(0, pl061->base + GPIOIE); /* disable irqs */ 332 irq = adev->irq[0]; 333 if (irq < 0) { 334 dev_err(&adev->dev, "invalid IRQ\n"); 335 return -ENODEV; 336 } 337 pl061->parent_irq = irq; 338 339 ret = gpiochip_irqchip_add(&pl061->gc, &pl061_irqchip, 340 0, handle_bad_irq, 341 IRQ_TYPE_NONE); 342 if (ret) { 343 dev_info(&adev->dev, "could not add irqchip\n"); 344 return ret; 345 } 346 gpiochip_set_chained_irqchip(&pl061->gc, &pl061_irqchip, 347 irq, pl061_irq_handler); 348 349 amba_set_drvdata(adev, pl061); 350 dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n", 351 &adev->res.start); 352 353 return 0; 354 } 355 356 #ifdef CONFIG_PM 357 static int pl061_suspend(struct device *dev) 358 { 359 struct pl061 *pl061 = dev_get_drvdata(dev); 360 int offset; 361 362 pl061->csave_regs.gpio_data = 0; 363 pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR); 364 pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS); 365 pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE); 366 pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV); 367 pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE); 368 369 for (offset = 0; offset < PL061_GPIO_NR; offset++) { 370 if (pl061->csave_regs.gpio_dir & (BIT(offset))) 371 pl061->csave_regs.gpio_data |= 372 pl061_get_value(&pl061->gc, offset) << offset; 373 } 374 375 return 0; 376 } 377 378 static int pl061_resume(struct device *dev) 379 { 380 struct pl061 *pl061 = dev_get_drvdata(dev); 381 int offset; 382 383 for (offset = 0; offset < PL061_GPIO_NR; offset++) { 384 if (pl061->csave_regs.gpio_dir & (BIT(offset))) 385 pl061_direction_output(&pl061->gc, offset, 386 pl061->csave_regs.gpio_data & 387 (BIT(offset))); 388 else 389 pl061_direction_input(&pl061->gc, offset); 390 } 391 392 writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); 393 writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); 394 writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); 395 writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); 396 397 return 0; 398 } 399 400 static const struct dev_pm_ops pl061_dev_pm_ops = { 401 .suspend = pl061_suspend, 402 .resume = pl061_resume, 403 .freeze = pl061_suspend, 404 .restore = pl061_resume, 405 }; 406 #endif 407 408 static const struct amba_id pl061_ids[] = { 409 { 410 .id = 0x00041061, 411 .mask = 0x000fffff, 412 }, 413 { 0, 0 }, 414 }; 415 416 static struct amba_driver pl061_gpio_driver = { 417 .drv = { 418 .name = "pl061_gpio", 419 #ifdef CONFIG_PM 420 .pm = &pl061_dev_pm_ops, 421 #endif 422 }, 423 .id_table = pl061_ids, 424 .probe = pl061_probe, 425 }; 426 427 static int __init pl061_gpio_init(void) 428 { 429 return amba_driver_register(&pl061_gpio_driver); 430 } 431 device_initcall(pl061_gpio_init); 432