1 /* 2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; version 2 of the License. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/pci.h> 20 #include <linux/gpio.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/slab.h> 24 25 #define PCH_EDGE_FALLING 0 26 #define PCH_EDGE_RISING BIT(0) 27 #define PCH_LEVEL_L BIT(1) 28 #define PCH_LEVEL_H (BIT(0) | BIT(1)) 29 #define PCH_EDGE_BOTH BIT(2) 30 #define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2)) 31 32 #define PCH_IRQ_BASE 24 33 34 struct pch_regs { 35 u32 ien; 36 u32 istatus; 37 u32 idisp; 38 u32 iclr; 39 u32 imask; 40 u32 imaskclr; 41 u32 po; 42 u32 pi; 43 u32 pm; 44 u32 im0; 45 u32 im1; 46 u32 reserved[3]; 47 u32 gpio_use_sel; 48 u32 reset; 49 }; 50 51 enum pch_type_t { 52 INTEL_EG20T_PCH, 53 OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */ 54 OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */ 55 }; 56 57 /* Specifies number of GPIO PINS */ 58 static int gpio_pins[] = { 59 [INTEL_EG20T_PCH] = 12, 60 [OKISEMI_ML7223m_IOH] = 8, 61 [OKISEMI_ML7223n_IOH] = 8, 62 }; 63 64 /** 65 * struct pch_gpio_reg_data - The register store data. 66 * @ien_reg: To store contents of IEN register. 67 * @imask_reg: To store contents of IMASK register. 68 * @po_reg: To store contents of PO register. 69 * @pm_reg: To store contents of PM register. 70 * @im0_reg: To store contents of IM0 register. 71 * @im1_reg: To store contents of IM1 register. 72 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register. 73 * (Only ML7223 Bus-n) 74 */ 75 struct pch_gpio_reg_data { 76 u32 ien_reg; 77 u32 imask_reg; 78 u32 po_reg; 79 u32 pm_reg; 80 u32 im0_reg; 81 u32 im1_reg; 82 u32 gpio_use_sel_reg; 83 }; 84 85 /** 86 * struct pch_gpio - GPIO private data structure. 87 * @base: PCI base address of Memory mapped I/O register. 88 * @reg: Memory mapped PCH GPIO register list. 89 * @dev: Pointer to device structure. 90 * @gpio: Data for GPIO infrastructure. 91 * @pch_gpio_reg: Memory mapped Register data is saved here 92 * when suspend. 93 * @lock: Used for register access protection 94 * @irq_base: Save base of IRQ number for interrupt 95 * @ioh: IOH ID 96 * @spinlock: Used for register access protection 97 */ 98 struct pch_gpio { 99 void __iomem *base; 100 struct pch_regs __iomem *reg; 101 struct device *dev; 102 struct gpio_chip gpio; 103 struct pch_gpio_reg_data pch_gpio_reg; 104 int irq_base; 105 enum pch_type_t ioh; 106 spinlock_t spinlock; 107 }; 108 109 static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val) 110 { 111 u32 reg_val; 112 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio); 113 unsigned long flags; 114 115 spin_lock_irqsave(&chip->spinlock, flags); 116 reg_val = ioread32(&chip->reg->po); 117 if (val) 118 reg_val |= (1 << nr); 119 else 120 reg_val &= ~(1 << nr); 121 122 iowrite32(reg_val, &chip->reg->po); 123 spin_unlock_irqrestore(&chip->spinlock, flags); 124 } 125 126 static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr) 127 { 128 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio); 129 130 return ioread32(&chip->reg->pi) & (1 << nr); 131 } 132 133 static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, 134 int val) 135 { 136 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio); 137 u32 pm; 138 u32 reg_val; 139 unsigned long flags; 140 141 spin_lock_irqsave(&chip->spinlock, flags); 142 143 reg_val = ioread32(&chip->reg->po); 144 if (val) 145 reg_val |= (1 << nr); 146 else 147 reg_val &= ~(1 << nr); 148 iowrite32(reg_val, &chip->reg->po); 149 150 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); 151 pm |= (1 << nr); 152 iowrite32(pm, &chip->reg->pm); 153 154 spin_unlock_irqrestore(&chip->spinlock, flags); 155 156 return 0; 157 } 158 159 static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) 160 { 161 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio); 162 u32 pm; 163 unsigned long flags; 164 165 spin_lock_irqsave(&chip->spinlock, flags); 166 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); 167 pm &= ~(1 << nr); 168 iowrite32(pm, &chip->reg->pm); 169 spin_unlock_irqrestore(&chip->spinlock, flags); 170 171 return 0; 172 } 173 174 /* 175 * Save register configuration and disable interrupts. 176 */ 177 static void pch_gpio_save_reg_conf(struct pch_gpio *chip) 178 { 179 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien); 180 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask); 181 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po); 182 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm); 183 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0); 184 if (chip->ioh == INTEL_EG20T_PCH) 185 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1); 186 if (chip->ioh == OKISEMI_ML7223n_IOH) 187 chip->pch_gpio_reg.gpio_use_sel_reg =\ 188 ioread32(&chip->reg->gpio_use_sel); 189 } 190 191 /* 192 * This function restores the register configuration of the GPIO device. 193 */ 194 static void pch_gpio_restore_reg_conf(struct pch_gpio *chip) 195 { 196 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien); 197 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask); 198 /* to store contents of PO register */ 199 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po); 200 /* to store contents of PM register */ 201 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm); 202 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0); 203 if (chip->ioh == INTEL_EG20T_PCH) 204 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1); 205 if (chip->ioh == OKISEMI_ML7223n_IOH) 206 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, 207 &chip->reg->gpio_use_sel); 208 } 209 210 static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset) 211 { 212 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio); 213 return chip->irq_base + offset; 214 } 215 216 static void pch_gpio_setup(struct pch_gpio *chip) 217 { 218 struct gpio_chip *gpio = &chip->gpio; 219 220 gpio->label = dev_name(chip->dev); 221 gpio->dev = chip->dev; 222 gpio->owner = THIS_MODULE; 223 gpio->direction_input = pch_gpio_direction_input; 224 gpio->get = pch_gpio_get; 225 gpio->direction_output = pch_gpio_direction_output; 226 gpio->set = pch_gpio_set; 227 gpio->dbg_show = NULL; 228 gpio->base = -1; 229 gpio->ngpio = gpio_pins[chip->ioh]; 230 gpio->can_sleep = false; 231 gpio->to_irq = pch_gpio_to_irq; 232 } 233 234 static int pch_irq_type(struct irq_data *d, unsigned int type) 235 { 236 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 237 struct pch_gpio *chip = gc->private; 238 u32 im, im_pos, val; 239 u32 __iomem *im_reg; 240 unsigned long flags; 241 int ch, irq = d->irq; 242 243 ch = irq - chip->irq_base; 244 if (irq <= chip->irq_base + 7) { 245 im_reg = &chip->reg->im0; 246 im_pos = ch; 247 } else { 248 im_reg = &chip->reg->im1; 249 im_pos = ch - 8; 250 } 251 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n", 252 __func__, irq, type, ch, im_pos); 253 254 spin_lock_irqsave(&chip->spinlock, flags); 255 256 switch (type) { 257 case IRQ_TYPE_EDGE_RISING: 258 val = PCH_EDGE_RISING; 259 break; 260 case IRQ_TYPE_EDGE_FALLING: 261 val = PCH_EDGE_FALLING; 262 break; 263 case IRQ_TYPE_EDGE_BOTH: 264 val = PCH_EDGE_BOTH; 265 break; 266 case IRQ_TYPE_LEVEL_HIGH: 267 val = PCH_LEVEL_H; 268 break; 269 case IRQ_TYPE_LEVEL_LOW: 270 val = PCH_LEVEL_L; 271 break; 272 default: 273 goto unlock; 274 } 275 276 /* Set interrupt mode */ 277 im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4)); 278 iowrite32(im | (val << (im_pos * 4)), im_reg); 279 280 /* And the handler */ 281 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 282 __irq_set_handler_locked(d->irq, handle_level_irq); 283 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 284 __irq_set_handler_locked(d->irq, handle_edge_irq); 285 286 unlock: 287 spin_unlock_irqrestore(&chip->spinlock, flags); 288 return 0; 289 } 290 291 static void pch_irq_unmask(struct irq_data *d) 292 { 293 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 294 struct pch_gpio *chip = gc->private; 295 296 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr); 297 } 298 299 static void pch_irq_mask(struct irq_data *d) 300 { 301 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 302 struct pch_gpio *chip = gc->private; 303 304 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask); 305 } 306 307 static void pch_irq_ack(struct irq_data *d) 308 { 309 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 310 struct pch_gpio *chip = gc->private; 311 312 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr); 313 } 314 315 static irqreturn_t pch_gpio_handler(int irq, void *dev_id) 316 { 317 struct pch_gpio *chip = dev_id; 318 u32 reg_val = ioread32(&chip->reg->istatus); 319 int i, ret = IRQ_NONE; 320 321 for (i = 0; i < gpio_pins[chip->ioh]; i++) { 322 if (reg_val & BIT(i)) { 323 dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n", 324 __func__, i, irq, reg_val); 325 generic_handle_irq(chip->irq_base + i); 326 ret = IRQ_HANDLED; 327 } 328 } 329 return ret; 330 } 331 332 static void pch_gpio_alloc_generic_chip(struct pch_gpio *chip, 333 unsigned int irq_start, unsigned int num) 334 { 335 struct irq_chip_generic *gc; 336 struct irq_chip_type *ct; 337 338 gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base, 339 handle_simple_irq); 340 gc->private = chip; 341 ct = gc->chip_types; 342 343 ct->chip.irq_ack = pch_irq_ack; 344 ct->chip.irq_mask = pch_irq_mask; 345 ct->chip.irq_unmask = pch_irq_unmask; 346 ct->chip.irq_set_type = pch_irq_type; 347 348 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, 349 IRQ_NOREQUEST | IRQ_NOPROBE, 0); 350 } 351 352 static int pch_gpio_probe(struct pci_dev *pdev, 353 const struct pci_device_id *id) 354 { 355 s32 ret; 356 struct pch_gpio *chip; 357 int irq_base; 358 u32 msk; 359 360 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 361 if (chip == NULL) 362 return -ENOMEM; 363 364 chip->dev = &pdev->dev; 365 ret = pci_enable_device(pdev); 366 if (ret) { 367 dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__); 368 goto err_pci_enable; 369 } 370 371 ret = pci_request_regions(pdev, KBUILD_MODNAME); 372 if (ret) { 373 dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret); 374 goto err_request_regions; 375 } 376 377 chip->base = pci_iomap(pdev, 1, 0); 378 if (!chip->base) { 379 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__); 380 ret = -ENOMEM; 381 goto err_iomap; 382 } 383 384 if (pdev->device == 0x8803) 385 chip->ioh = INTEL_EG20T_PCH; 386 else if (pdev->device == 0x8014) 387 chip->ioh = OKISEMI_ML7223m_IOH; 388 else if (pdev->device == 0x8043) 389 chip->ioh = OKISEMI_ML7223n_IOH; 390 391 chip->reg = chip->base; 392 pci_set_drvdata(pdev, chip); 393 spin_lock_init(&chip->spinlock); 394 pch_gpio_setup(chip); 395 ret = gpiochip_add(&chip->gpio); 396 if (ret) { 397 dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n"); 398 goto err_gpiochip_add; 399 } 400 401 irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE); 402 if (irq_base < 0) { 403 dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n"); 404 chip->irq_base = -1; 405 goto end; 406 } 407 chip->irq_base = irq_base; 408 409 /* Mask all interrupts, but enable them */ 410 msk = (1 << gpio_pins[chip->ioh]) - 1; 411 iowrite32(msk, &chip->reg->imask); 412 iowrite32(msk, &chip->reg->ien); 413 414 ret = request_irq(pdev->irq, pch_gpio_handler, 415 IRQF_SHARED, KBUILD_MODNAME, chip); 416 if (ret != 0) { 417 dev_err(&pdev->dev, 418 "%s request_irq failed\n", __func__); 419 goto err_request_irq; 420 } 421 422 pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]); 423 424 end: 425 return 0; 426 427 err_request_irq: 428 irq_free_descs(irq_base, gpio_pins[chip->ioh]); 429 gpiochip_remove(&chip->gpio); 430 431 err_gpiochip_add: 432 pci_iounmap(pdev, chip->base); 433 434 err_iomap: 435 pci_release_regions(pdev); 436 437 err_request_regions: 438 pci_disable_device(pdev); 439 440 err_pci_enable: 441 kfree(chip); 442 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret); 443 return ret; 444 } 445 446 static void pch_gpio_remove(struct pci_dev *pdev) 447 { 448 struct pch_gpio *chip = pci_get_drvdata(pdev); 449 450 if (chip->irq_base != -1) { 451 free_irq(pdev->irq, chip); 452 453 irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]); 454 } 455 456 gpiochip_remove(&chip->gpio); 457 pci_iounmap(pdev, chip->base); 458 pci_release_regions(pdev); 459 pci_disable_device(pdev); 460 kfree(chip); 461 } 462 463 #ifdef CONFIG_PM 464 static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state) 465 { 466 s32 ret; 467 struct pch_gpio *chip = pci_get_drvdata(pdev); 468 unsigned long flags; 469 470 spin_lock_irqsave(&chip->spinlock, flags); 471 pch_gpio_save_reg_conf(chip); 472 spin_unlock_irqrestore(&chip->spinlock, flags); 473 474 ret = pci_save_state(pdev); 475 if (ret) { 476 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret); 477 return ret; 478 } 479 pci_disable_device(pdev); 480 pci_set_power_state(pdev, PCI_D0); 481 ret = pci_enable_wake(pdev, PCI_D0, 1); 482 if (ret) 483 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret); 484 485 return 0; 486 } 487 488 static int pch_gpio_resume(struct pci_dev *pdev) 489 { 490 s32 ret; 491 struct pch_gpio *chip = pci_get_drvdata(pdev); 492 unsigned long flags; 493 494 ret = pci_enable_wake(pdev, PCI_D0, 0); 495 496 pci_set_power_state(pdev, PCI_D0); 497 ret = pci_enable_device(pdev); 498 if (ret) { 499 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret); 500 return ret; 501 } 502 pci_restore_state(pdev); 503 504 spin_lock_irqsave(&chip->spinlock, flags); 505 iowrite32(0x01, &chip->reg->reset); 506 iowrite32(0x00, &chip->reg->reset); 507 pch_gpio_restore_reg_conf(chip); 508 spin_unlock_irqrestore(&chip->spinlock, flags); 509 510 return 0; 511 } 512 #else 513 #define pch_gpio_suspend NULL 514 #define pch_gpio_resume NULL 515 #endif 516 517 #define PCI_VENDOR_ID_ROHM 0x10DB 518 static const struct pci_device_id pch_gpio_pcidev_id[] = { 519 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) }, 520 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) }, 521 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) }, 522 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) }, 523 { 0, } 524 }; 525 MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id); 526 527 static struct pci_driver pch_gpio_driver = { 528 .name = "pch_gpio", 529 .id_table = pch_gpio_pcidev_id, 530 .probe = pch_gpio_probe, 531 .remove = pch_gpio_remove, 532 .suspend = pch_gpio_suspend, 533 .resume = pch_gpio_resume 534 }; 535 536 module_pci_driver(pch_gpio_driver); 537 538 MODULE_DESCRIPTION("PCH GPIO PCI Driver"); 539 MODULE_LICENSE("GPL"); 540