1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCA953x 4/8/16/24/40 bit I/O ports 4 * 5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> 6 * Copyright (C) 2007 Marvell International Ltd. 7 * 8 * Derived from drivers/i2c/chips/pca9539.c 9 */ 10 11 #include <linux/acpi.h> 12 #include <linux/bitmap.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/i2c.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/module.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_data/pca953x.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/seq_file.h> 24 #include <linux/slab.h> 25 26 #include <asm/unaligned.h> 27 28 #define PCA953X_INPUT 0x00 29 #define PCA953X_OUTPUT 0x01 30 #define PCA953X_INVERT 0x02 31 #define PCA953X_DIRECTION 0x03 32 33 #define REG_ADDR_MASK GENMASK(5, 0) 34 #define REG_ADDR_EXT BIT(6) 35 #define REG_ADDR_AI BIT(7) 36 37 #define PCA957X_IN 0x00 38 #define PCA957X_INVRT 0x01 39 #define PCA957X_BKEN 0x02 40 #define PCA957X_PUPD 0x03 41 #define PCA957X_CFG 0x04 42 #define PCA957X_OUT 0x05 43 #define PCA957X_MSK 0x06 44 #define PCA957X_INTS 0x07 45 46 #define PCAL953X_OUT_STRENGTH 0x20 47 #define PCAL953X_IN_LATCH 0x22 48 #define PCAL953X_PULL_EN 0x23 49 #define PCAL953X_PULL_SEL 0x24 50 #define PCAL953X_INT_MASK 0x25 51 #define PCAL953X_INT_STAT 0x26 52 #define PCAL953X_OUT_CONF 0x27 53 54 #define PCAL6524_INT_EDGE 0x28 55 #define PCAL6524_INT_CLR 0x2a 56 #define PCAL6524_IN_STATUS 0x2b 57 #define PCAL6524_OUT_INDCONF 0x2c 58 #define PCAL6524_DEBOUNCE 0x2d 59 60 #define PCA_GPIO_MASK GENMASK(7, 0) 61 62 #define PCAL_GPIO_MASK GENMASK(4, 0) 63 #define PCAL_PINCTRL_MASK GENMASK(6, 5) 64 65 #define PCA_INT BIT(8) 66 #define PCA_PCAL BIT(9) 67 #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) 68 #define PCA953X_TYPE BIT(12) 69 #define PCA957X_TYPE BIT(13) 70 #define PCAL653X_TYPE BIT(14) 71 #define PCA_TYPE_MASK GENMASK(15, 12) 72 73 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) 74 75 static const struct i2c_device_id pca953x_id[] = { 76 { "pca6408", 8 | PCA953X_TYPE | PCA_INT, }, 77 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, 78 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, 79 { "pca9506", 40 | PCA953X_TYPE | PCA_INT, }, 80 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, 81 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, 82 { "pca9536", 4 | PCA953X_TYPE, }, 83 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, 84 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, 85 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, 86 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, 87 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, 88 { "pca9556", 8 | PCA953X_TYPE, }, 89 { "pca9557", 8 | PCA953X_TYPE, }, 90 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, 91 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, 92 { "pca9698", 40 | PCA953X_TYPE, }, 93 94 { "pcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 95 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 96 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, 97 { "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, }, 98 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 99 { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 100 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 101 102 { "max7310", 8 | PCA953X_TYPE, }, 103 { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, 104 { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, 105 { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, 106 { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, 107 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, 108 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, 109 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, 110 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, 111 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, 112 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, 113 { "xra1202", 8 | PCA953X_TYPE }, 114 { } 115 }; 116 MODULE_DEVICE_TABLE(i2c, pca953x_id); 117 118 #ifdef CONFIG_GPIO_PCA953X_IRQ 119 120 #include <linux/dmi.h> 121 122 static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true }; 123 124 static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = { 125 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, 126 { } 127 }; 128 129 static int pca953x_acpi_get_irq(struct device *dev) 130 { 131 int ret; 132 133 ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios); 134 if (ret) 135 dev_warn(dev, "can't add GPIO ACPI mapping\n"); 136 137 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0); 138 if (ret < 0) 139 return ret; 140 141 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); 142 return ret; 143 } 144 145 static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = { 146 { 147 /* 148 * On Intel Galileo Gen 2 board the IRQ pin of one of 149 * the I²C GPIO expanders, which has GpioInt() resource, 150 * is provided as an absolute number instead of being 151 * relative. Since first controller (gpio-sch.c) and 152 * second (gpio-dwapb.c) are at the fixed bases, we may 153 * safely refer to the number in the global space to get 154 * an IRQ out of it. 155 */ 156 .matches = { 157 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 158 }, 159 }, 160 {} 161 }; 162 #endif 163 164 static const struct acpi_device_id pca953x_acpi_ids[] = { 165 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 166 { } 167 }; 168 MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); 169 170 #define MAX_BANK 5 171 #define BANK_SZ 8 172 #define MAX_LINE (MAX_BANK * BANK_SZ) 173 174 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) 175 176 struct pca953x_reg_config { 177 int direction; 178 int output; 179 int input; 180 int invert; 181 }; 182 183 static const struct pca953x_reg_config pca953x_regs = { 184 .direction = PCA953X_DIRECTION, 185 .output = PCA953X_OUTPUT, 186 .input = PCA953X_INPUT, 187 .invert = PCA953X_INVERT, 188 }; 189 190 static const struct pca953x_reg_config pca957x_regs = { 191 .direction = PCA957X_CFG, 192 .output = PCA957X_OUT, 193 .input = PCA957X_IN, 194 .invert = PCA957X_INVRT, 195 }; 196 197 struct pca953x_chip { 198 unsigned gpio_start; 199 struct mutex i2c_lock; 200 struct regmap *regmap; 201 202 #ifdef CONFIG_GPIO_PCA953X_IRQ 203 struct mutex irq_lock; 204 DECLARE_BITMAP(irq_mask, MAX_LINE); 205 DECLARE_BITMAP(irq_stat, MAX_LINE); 206 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 207 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 208 #endif 209 atomic_t wakeup_path; 210 211 struct i2c_client *client; 212 struct gpio_chip gpio_chip; 213 const char *const *names; 214 unsigned long driver_data; 215 struct regulator *regulator; 216 217 const struct pca953x_reg_config *regs; 218 219 u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off); 220 bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg, 221 u32 checkbank); 222 }; 223 224 static int pca953x_bank_shift(struct pca953x_chip *chip) 225 { 226 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); 227 } 228 229 #define PCA953x_BANK_INPUT BIT(0) 230 #define PCA953x_BANK_OUTPUT BIT(1) 231 #define PCA953x_BANK_POLARITY BIT(2) 232 #define PCA953x_BANK_CONFIG BIT(3) 233 234 #define PCA957x_BANK_INPUT BIT(0) 235 #define PCA957x_BANK_POLARITY BIT(1) 236 #define PCA957x_BANK_BUSHOLD BIT(2) 237 #define PCA957x_BANK_CONFIG BIT(4) 238 #define PCA957x_BANK_OUTPUT BIT(5) 239 240 #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) 241 #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) 242 #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) 243 #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) 244 #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) 245 246 /* 247 * We care about the following registers: 248 * - Standard set, below 0x40, each port can be replicated up to 8 times 249 * - PCA953x standard 250 * Input port 0x00 + 0 * bank_size R 251 * Output port 0x00 + 1 * bank_size RW 252 * Polarity Inversion port 0x00 + 2 * bank_size RW 253 * Configuration port 0x00 + 3 * bank_size RW 254 * - PCA957x with mixed up registers 255 * Input port 0x00 + 0 * bank_size R 256 * Polarity Inversion port 0x00 + 1 * bank_size RW 257 * Bus hold port 0x00 + 2 * bank_size RW 258 * Configuration port 0x00 + 4 * bank_size RW 259 * Output port 0x00 + 5 * bank_size RW 260 * 261 * - Extended set, above 0x40, often chip specific. 262 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: 263 * Input latch register 0x40 + 2 * bank_size RW 264 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW 265 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW 266 * Interrupt mask register 0x40 + 5 * bank_size RW 267 * Interrupt status register 0x40 + 6 * bank_size R 268 * 269 * - Registers with bit 0x80 set, the AI bit 270 * The bit is cleared and the registers fall into one of the 271 * categories above. 272 */ 273 274 static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, 275 u32 checkbank) 276 { 277 int bank_shift = pca953x_bank_shift(chip); 278 int bank = (reg & REG_ADDR_MASK) >> bank_shift; 279 int offset = reg & (BIT(bank_shift) - 1); 280 281 /* Special PCAL extended register check. */ 282 if (reg & REG_ADDR_EXT) { 283 if (!(chip->driver_data & PCA_PCAL)) 284 return false; 285 bank += 8; 286 } 287 288 /* Register is not in the matching bank. */ 289 if (!(BIT(bank) & checkbank)) 290 return false; 291 292 /* Register is not within allowed range of bank. */ 293 if (offset >= NBANK(chip)) 294 return false; 295 296 return true; 297 } 298 299 /* 300 * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the 301 * same register layout as the PCAL6524, the spacing of the registers has been 302 * fundamentally altered by compacting them and thus does not obey the same 303 * rules, including being able to use bit shifting to determine bank. These 304 * chips hence need special handling here. 305 */ 306 static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg, 307 u32 checkbank) 308 { 309 int bank; 310 int offset; 311 312 if (reg >= 0x30) { 313 /* 314 * Reserved block between 14h and 2Fh does not align on 315 * expected bank boundaries like other devices. 316 */ 317 int temp = reg - 0x30; 318 319 bank = temp / NBANK(chip); 320 offset = temp - (bank * NBANK(chip)); 321 bank += 8; 322 } else if (reg >= 0x54) { 323 /* 324 * Handle lack of reserved registers after output port 325 * configuration register to form a bank. 326 */ 327 int temp = reg - 0x54; 328 329 bank = temp / NBANK(chip); 330 offset = temp - (bank * NBANK(chip)); 331 bank += 16; 332 } else { 333 bank = reg / NBANK(chip); 334 offset = reg - (bank * NBANK(chip)); 335 } 336 337 /* Register is not in the matching bank. */ 338 if (!(BIT(bank) & checkbank)) 339 return false; 340 341 /* Register is not within allowed range of bank. */ 342 if (offset >= NBANK(chip)) 343 return false; 344 345 return true; 346 } 347 348 static bool pca953x_readable_register(struct device *dev, unsigned int reg) 349 { 350 struct pca953x_chip *chip = dev_get_drvdata(dev); 351 u32 bank; 352 353 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 354 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | 355 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | 356 PCA957x_BANK_BUSHOLD; 357 } else { 358 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | 359 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; 360 } 361 362 if (chip->driver_data & PCA_PCAL) { 363 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 364 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | 365 PCAL9xxx_BANK_IRQ_STAT; 366 } 367 368 return chip->check_reg(chip, reg, bank); 369 } 370 371 static bool pca953x_writeable_register(struct device *dev, unsigned int reg) 372 { 373 struct pca953x_chip *chip = dev_get_drvdata(dev); 374 u32 bank; 375 376 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 377 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | 378 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; 379 } else { 380 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | 381 PCA953x_BANK_CONFIG; 382 } 383 384 if (chip->driver_data & PCA_PCAL) 385 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 386 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; 387 388 return chip->check_reg(chip, reg, bank); 389 } 390 391 static bool pca953x_volatile_register(struct device *dev, unsigned int reg) 392 { 393 struct pca953x_chip *chip = dev_get_drvdata(dev); 394 u32 bank; 395 396 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) 397 bank = PCA957x_BANK_INPUT; 398 else 399 bank = PCA953x_BANK_INPUT; 400 401 if (chip->driver_data & PCA_PCAL) 402 bank |= PCAL9xxx_BANK_IRQ_STAT; 403 404 return chip->check_reg(chip, reg, bank); 405 } 406 407 static const struct regmap_config pca953x_i2c_regmap = { 408 .reg_bits = 8, 409 .val_bits = 8, 410 411 .use_single_read = true, 412 .use_single_write = true, 413 414 .readable_reg = pca953x_readable_register, 415 .writeable_reg = pca953x_writeable_register, 416 .volatile_reg = pca953x_volatile_register, 417 418 .disable_locking = true, 419 .cache_type = REGCACHE_RBTREE, 420 .max_register = 0x7f, 421 }; 422 423 static const struct regmap_config pca953x_ai_i2c_regmap = { 424 .reg_bits = 8, 425 .val_bits = 8, 426 427 .read_flag_mask = REG_ADDR_AI, 428 .write_flag_mask = REG_ADDR_AI, 429 430 .readable_reg = pca953x_readable_register, 431 .writeable_reg = pca953x_writeable_register, 432 .volatile_reg = pca953x_volatile_register, 433 434 .disable_locking = true, 435 .cache_type = REGCACHE_RBTREE, 436 .max_register = 0x7f, 437 }; 438 439 static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off) 440 { 441 int bank_shift = pca953x_bank_shift(chip); 442 int addr = (reg & PCAL_GPIO_MASK) << bank_shift; 443 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; 444 u8 regaddr = pinctrl | addr | (off / BANK_SZ); 445 446 return regaddr; 447 } 448 449 /* 450 * The PCAL6534 and compatible chips have altered bank alignment that doesn't 451 * fit within the bit shifting scheme used for other devices. 452 */ 453 static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off) 454 { 455 int addr; 456 int pinctrl; 457 458 addr = (reg & PCAL_GPIO_MASK) * NBANK(chip); 459 460 switch (reg) { 461 case PCAL953X_OUT_STRENGTH: 462 case PCAL953X_IN_LATCH: 463 case PCAL953X_PULL_EN: 464 case PCAL953X_PULL_SEL: 465 case PCAL953X_INT_MASK: 466 case PCAL953X_INT_STAT: 467 case PCAL953X_OUT_CONF: 468 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20; 469 break; 470 case PCAL6524_INT_EDGE: 471 case PCAL6524_INT_CLR: 472 case PCAL6524_IN_STATUS: 473 case PCAL6524_OUT_INDCONF: 474 case PCAL6524_DEBOUNCE: 475 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c; 476 break; 477 } 478 479 return pinctrl + addr + (off / BANK_SZ); 480 } 481 482 static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 483 { 484 u8 regaddr = chip->recalc_addr(chip, reg, 0); 485 u8 value[MAX_BANK]; 486 int i, ret; 487 488 for (i = 0; i < NBANK(chip); i++) 489 value[i] = bitmap_get_value8(val, i * BANK_SZ); 490 491 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip)); 492 if (ret < 0) { 493 dev_err(&chip->client->dev, "failed writing register\n"); 494 return ret; 495 } 496 497 return 0; 498 } 499 500 static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 501 { 502 u8 regaddr = chip->recalc_addr(chip, reg, 0); 503 u8 value[MAX_BANK]; 504 int i, ret; 505 506 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip)); 507 if (ret < 0) { 508 dev_err(&chip->client->dev, "failed reading register\n"); 509 return ret; 510 } 511 512 for (i = 0; i < NBANK(chip); i++) 513 bitmap_set_value8(val, value[i], i * BANK_SZ); 514 515 return 0; 516 } 517 518 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) 519 { 520 struct pca953x_chip *chip = gpiochip_get_data(gc); 521 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 522 u8 bit = BIT(off % BANK_SZ); 523 int ret; 524 525 mutex_lock(&chip->i2c_lock); 526 ret = regmap_write_bits(chip->regmap, dirreg, bit, bit); 527 mutex_unlock(&chip->i2c_lock); 528 return ret; 529 } 530 531 static int pca953x_gpio_direction_output(struct gpio_chip *gc, 532 unsigned off, int val) 533 { 534 struct pca953x_chip *chip = gpiochip_get_data(gc); 535 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 536 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 537 u8 bit = BIT(off % BANK_SZ); 538 int ret; 539 540 mutex_lock(&chip->i2c_lock); 541 /* set output level */ 542 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 543 if (ret) 544 goto exit; 545 546 /* then direction */ 547 ret = regmap_write_bits(chip->regmap, dirreg, bit, 0); 548 exit: 549 mutex_unlock(&chip->i2c_lock); 550 return ret; 551 } 552 553 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) 554 { 555 struct pca953x_chip *chip = gpiochip_get_data(gc); 556 u8 inreg = chip->recalc_addr(chip, chip->regs->input, off); 557 u8 bit = BIT(off % BANK_SZ); 558 u32 reg_val; 559 int ret; 560 561 mutex_lock(&chip->i2c_lock); 562 ret = regmap_read(chip->regmap, inreg, ®_val); 563 mutex_unlock(&chip->i2c_lock); 564 if (ret < 0) 565 return ret; 566 567 return !!(reg_val & bit); 568 } 569 570 static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) 571 { 572 struct pca953x_chip *chip = gpiochip_get_data(gc); 573 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 574 u8 bit = BIT(off % BANK_SZ); 575 576 mutex_lock(&chip->i2c_lock); 577 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 578 mutex_unlock(&chip->i2c_lock); 579 } 580 581 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) 582 { 583 struct pca953x_chip *chip = gpiochip_get_data(gc); 584 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 585 u8 bit = BIT(off % BANK_SZ); 586 u32 reg_val; 587 int ret; 588 589 mutex_lock(&chip->i2c_lock); 590 ret = regmap_read(chip->regmap, dirreg, ®_val); 591 mutex_unlock(&chip->i2c_lock); 592 if (ret < 0) 593 return ret; 594 595 if (reg_val & bit) 596 return GPIO_LINE_DIRECTION_IN; 597 598 return GPIO_LINE_DIRECTION_OUT; 599 } 600 601 static int pca953x_gpio_get_multiple(struct gpio_chip *gc, 602 unsigned long *mask, unsigned long *bits) 603 { 604 struct pca953x_chip *chip = gpiochip_get_data(gc); 605 DECLARE_BITMAP(reg_val, MAX_LINE); 606 int ret; 607 608 mutex_lock(&chip->i2c_lock); 609 ret = pca953x_read_regs(chip, chip->regs->input, reg_val); 610 mutex_unlock(&chip->i2c_lock); 611 if (ret) 612 return ret; 613 614 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio); 615 return 0; 616 } 617 618 static void pca953x_gpio_set_multiple(struct gpio_chip *gc, 619 unsigned long *mask, unsigned long *bits) 620 { 621 struct pca953x_chip *chip = gpiochip_get_data(gc); 622 DECLARE_BITMAP(reg_val, MAX_LINE); 623 int ret; 624 625 mutex_lock(&chip->i2c_lock); 626 ret = pca953x_read_regs(chip, chip->regs->output, reg_val); 627 if (ret) 628 goto exit; 629 630 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio); 631 632 pca953x_write_regs(chip, chip->regs->output, reg_val); 633 exit: 634 mutex_unlock(&chip->i2c_lock); 635 } 636 637 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, 638 unsigned int offset, 639 unsigned long config) 640 { 641 enum pin_config_param param = pinconf_to_config_param(config); 642 643 u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset); 644 u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset); 645 u8 bit = BIT(offset % BANK_SZ); 646 int ret; 647 648 /* 649 * pull-up/pull-down configuration requires PCAL extended 650 * registers 651 */ 652 if (!(chip->driver_data & PCA_PCAL)) 653 return -ENOTSUPP; 654 655 mutex_lock(&chip->i2c_lock); 656 657 /* Configure pull-up/pull-down */ 658 if (param == PIN_CONFIG_BIAS_PULL_UP) 659 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit); 660 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 661 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0); 662 else 663 ret = 0; 664 if (ret) 665 goto exit; 666 667 /* Disable/Enable pull-up/pull-down */ 668 if (param == PIN_CONFIG_BIAS_DISABLE) 669 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0); 670 else 671 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit); 672 673 exit: 674 mutex_unlock(&chip->i2c_lock); 675 return ret; 676 } 677 678 static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 679 unsigned long config) 680 { 681 struct pca953x_chip *chip = gpiochip_get_data(gc); 682 683 switch (pinconf_to_config_param(config)) { 684 case PIN_CONFIG_BIAS_PULL_UP: 685 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 686 case PIN_CONFIG_BIAS_PULL_DOWN: 687 case PIN_CONFIG_BIAS_DISABLE: 688 return pca953x_gpio_set_pull_up_down(chip, offset, config); 689 default: 690 return -ENOTSUPP; 691 } 692 } 693 694 static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) 695 { 696 struct gpio_chip *gc; 697 698 gc = &chip->gpio_chip; 699 700 gc->direction_input = pca953x_gpio_direction_input; 701 gc->direction_output = pca953x_gpio_direction_output; 702 gc->get = pca953x_gpio_get_value; 703 gc->set = pca953x_gpio_set_value; 704 gc->get_direction = pca953x_gpio_get_direction; 705 gc->get_multiple = pca953x_gpio_get_multiple; 706 gc->set_multiple = pca953x_gpio_set_multiple; 707 gc->set_config = pca953x_gpio_set_config; 708 gc->can_sleep = true; 709 710 gc->base = chip->gpio_start; 711 gc->ngpio = gpios; 712 gc->label = dev_name(&chip->client->dev); 713 gc->parent = &chip->client->dev; 714 gc->owner = THIS_MODULE; 715 gc->names = chip->names; 716 } 717 718 #ifdef CONFIG_GPIO_PCA953X_IRQ 719 static void pca953x_irq_mask(struct irq_data *d) 720 { 721 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 722 struct pca953x_chip *chip = gpiochip_get_data(gc); 723 irq_hw_number_t hwirq = irqd_to_hwirq(d); 724 725 clear_bit(hwirq, chip->irq_mask); 726 gpiochip_disable_irq(gc, hwirq); 727 } 728 729 static void pca953x_irq_unmask(struct irq_data *d) 730 { 731 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 732 struct pca953x_chip *chip = gpiochip_get_data(gc); 733 irq_hw_number_t hwirq = irqd_to_hwirq(d); 734 735 gpiochip_enable_irq(gc, hwirq); 736 set_bit(hwirq, chip->irq_mask); 737 } 738 739 static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) 740 { 741 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 742 struct pca953x_chip *chip = gpiochip_get_data(gc); 743 744 if (on) 745 atomic_inc(&chip->wakeup_path); 746 else 747 atomic_dec(&chip->wakeup_path); 748 749 return irq_set_irq_wake(chip->client->irq, on); 750 } 751 752 static void pca953x_irq_bus_lock(struct irq_data *d) 753 { 754 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 755 struct pca953x_chip *chip = gpiochip_get_data(gc); 756 757 mutex_lock(&chip->irq_lock); 758 } 759 760 static void pca953x_irq_bus_sync_unlock(struct irq_data *d) 761 { 762 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 763 struct pca953x_chip *chip = gpiochip_get_data(gc); 764 DECLARE_BITMAP(irq_mask, MAX_LINE); 765 DECLARE_BITMAP(reg_direction, MAX_LINE); 766 int level; 767 768 if (chip->driver_data & PCA_PCAL) { 769 /* Enable latch on interrupt-enabled inputs */ 770 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); 771 772 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio); 773 774 /* Unmask enabled interrupts */ 775 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask); 776 } 777 778 /* Switch direction to input if needed */ 779 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 780 781 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio); 782 bitmap_complement(reg_direction, reg_direction, gc->ngpio); 783 bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio); 784 785 /* Look for any newly setup interrupt */ 786 for_each_set_bit(level, irq_mask, gc->ngpio) 787 pca953x_gpio_direction_input(&chip->gpio_chip, level); 788 789 mutex_unlock(&chip->irq_lock); 790 } 791 792 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) 793 { 794 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 795 struct pca953x_chip *chip = gpiochip_get_data(gc); 796 irq_hw_number_t hwirq = irqd_to_hwirq(d); 797 798 if (!(type & IRQ_TYPE_EDGE_BOTH)) { 799 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", 800 d->irq, type); 801 return -EINVAL; 802 } 803 804 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING); 805 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING); 806 807 return 0; 808 } 809 810 static void pca953x_irq_shutdown(struct irq_data *d) 811 { 812 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 813 struct pca953x_chip *chip = gpiochip_get_data(gc); 814 irq_hw_number_t hwirq = irqd_to_hwirq(d); 815 816 clear_bit(hwirq, chip->irq_trig_raise); 817 clear_bit(hwirq, chip->irq_trig_fall); 818 } 819 820 static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p) 821 { 822 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 823 824 seq_printf(p, dev_name(gc->parent)); 825 } 826 827 static const struct irq_chip pca953x_irq_chip = { 828 .irq_mask = pca953x_irq_mask, 829 .irq_unmask = pca953x_irq_unmask, 830 .irq_set_wake = pca953x_irq_set_wake, 831 .irq_bus_lock = pca953x_irq_bus_lock, 832 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, 833 .irq_set_type = pca953x_irq_set_type, 834 .irq_shutdown = pca953x_irq_shutdown, 835 .irq_print_chip = pca953x_irq_print_chip, 836 .flags = IRQCHIP_IMMUTABLE, 837 GPIOCHIP_IRQ_RESOURCE_HELPERS, 838 }; 839 840 static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending) 841 { 842 struct gpio_chip *gc = &chip->gpio_chip; 843 DECLARE_BITMAP(reg_direction, MAX_LINE); 844 DECLARE_BITMAP(old_stat, MAX_LINE); 845 DECLARE_BITMAP(cur_stat, MAX_LINE); 846 DECLARE_BITMAP(new_stat, MAX_LINE); 847 DECLARE_BITMAP(trigger, MAX_LINE); 848 int ret; 849 850 if (chip->driver_data & PCA_PCAL) { 851 /* Read the current interrupt status from the device */ 852 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); 853 if (ret) 854 return false; 855 856 /* Check latched inputs and clear interrupt status */ 857 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 858 if (ret) 859 return false; 860 861 /* Apply filter for rising/falling edge selection */ 862 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio); 863 864 bitmap_and(pending, new_stat, trigger, gc->ngpio); 865 866 return !bitmap_empty(pending, gc->ngpio); 867 } 868 869 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 870 if (ret) 871 return false; 872 873 /* Remove output pins from the equation */ 874 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 875 876 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio); 877 878 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio); 879 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio); 880 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio); 881 882 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio); 883 884 if (bitmap_empty(trigger, gc->ngpio)) 885 return false; 886 887 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio); 888 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio); 889 bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio); 890 bitmap_and(pending, new_stat, trigger, gc->ngpio); 891 892 return !bitmap_empty(pending, gc->ngpio); 893 } 894 895 static irqreturn_t pca953x_irq_handler(int irq, void *devid) 896 { 897 struct pca953x_chip *chip = devid; 898 struct gpio_chip *gc = &chip->gpio_chip; 899 DECLARE_BITMAP(pending, MAX_LINE); 900 int level; 901 bool ret; 902 903 bitmap_zero(pending, MAX_LINE); 904 905 mutex_lock(&chip->i2c_lock); 906 ret = pca953x_irq_pending(chip, pending); 907 mutex_unlock(&chip->i2c_lock); 908 909 if (ret) { 910 ret = 0; 911 912 for_each_set_bit(level, pending, gc->ngpio) { 913 int nested_irq = irq_find_mapping(gc->irq.domain, level); 914 915 if (unlikely(nested_irq <= 0)) { 916 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); 917 continue; 918 } 919 920 handle_nested_irq(nested_irq); 921 ret = 1; 922 } 923 } 924 925 return IRQ_RETVAL(ret); 926 } 927 928 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 929 { 930 struct i2c_client *client = chip->client; 931 DECLARE_BITMAP(reg_direction, MAX_LINE); 932 DECLARE_BITMAP(irq_stat, MAX_LINE); 933 struct gpio_irq_chip *girq; 934 int ret; 935 936 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) { 937 ret = pca953x_acpi_get_irq(&client->dev); 938 if (ret > 0) 939 client->irq = ret; 940 } 941 942 if (!client->irq) 943 return 0; 944 945 if (irq_base == -1) 946 return 0; 947 948 if (!(chip->driver_data & PCA_INT)) 949 return 0; 950 951 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat); 952 if (ret) 953 return ret; 954 955 /* 956 * There is no way to know which GPIO line generated the 957 * interrupt. We have to rely on the previous read for 958 * this purpose. 959 */ 960 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 961 bitmap_and(chip->irq_stat, irq_stat, reg_direction, chip->gpio_chip.ngpio); 962 mutex_init(&chip->irq_lock); 963 964 girq = &chip->gpio_chip.irq; 965 gpio_irq_chip_set_chip(girq, &pca953x_irq_chip); 966 /* This will let us handle the parent IRQ in the driver */ 967 girq->parent_handler = NULL; 968 girq->num_parents = 0; 969 girq->parents = NULL; 970 girq->default_type = IRQ_TYPE_NONE; 971 girq->handler = handle_simple_irq; 972 girq->threaded = true; 973 girq->first = irq_base; /* FIXME: get rid of this */ 974 975 ret = devm_request_threaded_irq(&client->dev, client->irq, 976 NULL, pca953x_irq_handler, 977 IRQF_ONESHOT | IRQF_SHARED, 978 dev_name(&client->dev), chip); 979 if (ret) { 980 dev_err(&client->dev, "failed to request irq %d\n", 981 client->irq); 982 return ret; 983 } 984 985 return 0; 986 } 987 988 #else /* CONFIG_GPIO_PCA953X_IRQ */ 989 static int pca953x_irq_setup(struct pca953x_chip *chip, 990 int irq_base) 991 { 992 struct i2c_client *client = chip->client; 993 994 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) 995 dev_warn(&client->dev, "interrupt support not compiled in\n"); 996 997 return 0; 998 } 999 #endif 1000 1001 static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert) 1002 { 1003 DECLARE_BITMAP(val, MAX_LINE); 1004 u8 regaddr; 1005 int ret; 1006 1007 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1008 ret = regcache_sync_region(chip->regmap, regaddr, 1009 regaddr + NBANK(chip) - 1); 1010 if (ret) 1011 goto out; 1012 1013 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1014 ret = regcache_sync_region(chip->regmap, regaddr, 1015 regaddr + NBANK(chip) - 1); 1016 if (ret) 1017 goto out; 1018 1019 /* set platform specific polarity inversion */ 1020 if (invert) 1021 bitmap_fill(val, MAX_LINE); 1022 else 1023 bitmap_zero(val, MAX_LINE); 1024 1025 ret = pca953x_write_regs(chip, chip->regs->invert, val); 1026 out: 1027 return ret; 1028 } 1029 1030 static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) 1031 { 1032 DECLARE_BITMAP(val, MAX_LINE); 1033 unsigned int i; 1034 int ret; 1035 1036 ret = device_pca95xx_init(chip, invert); 1037 if (ret) 1038 goto out; 1039 1040 /* To enable register 6, 7 to control pull up and pull down */ 1041 for (i = 0; i < NBANK(chip); i++) 1042 bitmap_set_value8(val, 0x02, i * BANK_SZ); 1043 1044 ret = pca953x_write_regs(chip, PCA957X_BKEN, val); 1045 if (ret) 1046 goto out; 1047 1048 return 0; 1049 out: 1050 return ret; 1051 } 1052 1053 static int pca953x_probe(struct i2c_client *client) 1054 { 1055 const struct i2c_device_id *i2c_id = i2c_client_get_device_id(client); 1056 struct pca953x_platform_data *pdata; 1057 struct pca953x_chip *chip; 1058 int irq_base = 0; 1059 int ret; 1060 u32 invert = 0; 1061 struct regulator *reg; 1062 const struct regmap_config *regmap_config; 1063 1064 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); 1065 if (chip == NULL) 1066 return -ENOMEM; 1067 1068 pdata = dev_get_platdata(&client->dev); 1069 if (pdata) { 1070 irq_base = pdata->irq_base; 1071 chip->gpio_start = pdata->gpio_base; 1072 invert = pdata->invert; 1073 chip->names = pdata->names; 1074 } else { 1075 struct gpio_desc *reset_gpio; 1076 1077 chip->gpio_start = -1; 1078 irq_base = 0; 1079 1080 /* 1081 * See if we need to de-assert a reset pin. 1082 * 1083 * There is no known ACPI-enabled platforms that are 1084 * using "reset" GPIO. Otherwise any of those platform 1085 * must use _DSD method with corresponding property. 1086 */ 1087 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1088 GPIOD_OUT_LOW); 1089 if (IS_ERR(reset_gpio)) 1090 return PTR_ERR(reset_gpio); 1091 } 1092 1093 chip->client = client; 1094 1095 reg = devm_regulator_get(&client->dev, "vcc"); 1096 if (IS_ERR(reg)) 1097 return dev_err_probe(&client->dev, PTR_ERR(reg), "reg get err\n"); 1098 1099 ret = regulator_enable(reg); 1100 if (ret) { 1101 dev_err(&client->dev, "reg en err: %d\n", ret); 1102 return ret; 1103 } 1104 chip->regulator = reg; 1105 1106 if (i2c_id) { 1107 chip->driver_data = i2c_id->driver_data; 1108 } else { 1109 const void *match; 1110 1111 match = device_get_match_data(&client->dev); 1112 if (!match) { 1113 ret = -ENODEV; 1114 goto err_exit; 1115 } 1116 1117 chip->driver_data = (uintptr_t)match; 1118 } 1119 1120 i2c_set_clientdata(client, chip); 1121 1122 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); 1123 1124 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 1125 dev_info(&client->dev, "using AI\n"); 1126 regmap_config = &pca953x_ai_i2c_regmap; 1127 } else { 1128 dev_info(&client->dev, "using no AI\n"); 1129 regmap_config = &pca953x_i2c_regmap; 1130 } 1131 1132 if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) { 1133 chip->recalc_addr = pcal6534_recalc_addr; 1134 chip->check_reg = pcal6534_check_register; 1135 } else { 1136 chip->recalc_addr = pca953x_recalc_addr; 1137 chip->check_reg = pca953x_check_register; 1138 } 1139 1140 chip->regmap = devm_regmap_init_i2c(client, regmap_config); 1141 if (IS_ERR(chip->regmap)) { 1142 ret = PTR_ERR(chip->regmap); 1143 goto err_exit; 1144 } 1145 1146 regcache_mark_dirty(chip->regmap); 1147 1148 mutex_init(&chip->i2c_lock); 1149 /* 1150 * In case we have an i2c-mux controlled by a GPIO provided by an 1151 * expander using the same driver higher on the device tree, read the 1152 * i2c adapter nesting depth and use the retrieved value as lockdep 1153 * subclass for chip->i2c_lock. 1154 * 1155 * REVISIT: This solution is not complete. It protects us from lockdep 1156 * false positives when the expander controlling the i2c-mux is on 1157 * a different level on the device tree, but not when it's on the same 1158 * level on a different branch (in which case the subclass number 1159 * would be the same). 1160 * 1161 * TODO: Once a correct solution is developed, a similar fix should be 1162 * applied to all other i2c-controlled GPIO expanders (and potentially 1163 * regmap-i2c). 1164 */ 1165 lockdep_set_subclass(&chip->i2c_lock, 1166 i2c_adapter_depth(client->adapter)); 1167 1168 /* initialize cached registers from their original values. 1169 * we can't share this chip with another i2c master. 1170 */ 1171 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 1172 chip->regs = &pca957x_regs; 1173 ret = device_pca957x_init(chip, invert); 1174 } else { 1175 chip->regs = &pca953x_regs; 1176 ret = device_pca95xx_init(chip, invert); 1177 } 1178 if (ret) 1179 goto err_exit; 1180 1181 ret = pca953x_irq_setup(chip, irq_base); 1182 if (ret) 1183 goto err_exit; 1184 1185 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); 1186 if (ret) 1187 goto err_exit; 1188 1189 if (pdata && pdata->setup) { 1190 ret = pdata->setup(client, chip->gpio_chip.base, 1191 chip->gpio_chip.ngpio, pdata->context); 1192 if (ret < 0) 1193 dev_warn(&client->dev, "setup failed, %d\n", ret); 1194 } 1195 1196 return 0; 1197 1198 err_exit: 1199 regulator_disable(chip->regulator); 1200 return ret; 1201 } 1202 1203 static void pca953x_remove(struct i2c_client *client) 1204 { 1205 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); 1206 struct pca953x_chip *chip = i2c_get_clientdata(client); 1207 1208 if (pdata && pdata->teardown) { 1209 pdata->teardown(client, chip->gpio_chip.base, 1210 chip->gpio_chip.ngpio, pdata->context); 1211 } 1212 1213 regulator_disable(chip->regulator); 1214 } 1215 1216 #ifdef CONFIG_PM_SLEEP 1217 static int pca953x_regcache_sync(struct device *dev) 1218 { 1219 struct pca953x_chip *chip = dev_get_drvdata(dev); 1220 int ret; 1221 u8 regaddr; 1222 1223 /* 1224 * The ordering between direction and output is important, 1225 * sync these registers first and only then sync the rest. 1226 */ 1227 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1228 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1229 if (ret) { 1230 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); 1231 return ret; 1232 } 1233 1234 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1235 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1236 if (ret) { 1237 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); 1238 return ret; 1239 } 1240 1241 #ifdef CONFIG_GPIO_PCA953X_IRQ 1242 if (chip->driver_data & PCA_PCAL) { 1243 regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0); 1244 ret = regcache_sync_region(chip->regmap, regaddr, 1245 regaddr + NBANK(chip) - 1); 1246 if (ret) { 1247 dev_err(dev, "Failed to sync INT latch registers: %d\n", 1248 ret); 1249 return ret; 1250 } 1251 1252 regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0); 1253 ret = regcache_sync_region(chip->regmap, regaddr, 1254 regaddr + NBANK(chip) - 1); 1255 if (ret) { 1256 dev_err(dev, "Failed to sync INT mask registers: %d\n", 1257 ret); 1258 return ret; 1259 } 1260 } 1261 #endif 1262 1263 return 0; 1264 } 1265 1266 static int pca953x_suspend(struct device *dev) 1267 { 1268 struct pca953x_chip *chip = dev_get_drvdata(dev); 1269 1270 mutex_lock(&chip->i2c_lock); 1271 regcache_cache_only(chip->regmap, true); 1272 mutex_unlock(&chip->i2c_lock); 1273 1274 if (atomic_read(&chip->wakeup_path)) 1275 device_set_wakeup_path(dev); 1276 else 1277 regulator_disable(chip->regulator); 1278 1279 return 0; 1280 } 1281 1282 static int pca953x_resume(struct device *dev) 1283 { 1284 struct pca953x_chip *chip = dev_get_drvdata(dev); 1285 int ret; 1286 1287 if (!atomic_read(&chip->wakeup_path)) { 1288 ret = regulator_enable(chip->regulator); 1289 if (ret) { 1290 dev_err(dev, "Failed to enable regulator: %d\n", ret); 1291 return 0; 1292 } 1293 } 1294 1295 mutex_lock(&chip->i2c_lock); 1296 regcache_cache_only(chip->regmap, false); 1297 regcache_mark_dirty(chip->regmap); 1298 ret = pca953x_regcache_sync(dev); 1299 if (ret) { 1300 mutex_unlock(&chip->i2c_lock); 1301 return ret; 1302 } 1303 1304 ret = regcache_sync(chip->regmap); 1305 mutex_unlock(&chip->i2c_lock); 1306 if (ret) { 1307 dev_err(dev, "Failed to restore register map: %d\n", ret); 1308 return ret; 1309 } 1310 1311 return 0; 1312 } 1313 #endif 1314 1315 /* convenience to stop overlong match-table lines */ 1316 #define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int)) 1317 #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) 1318 #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) 1319 1320 static const struct of_device_id pca953x_dt_ids[] = { 1321 { .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), }, 1322 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, 1323 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, 1324 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), }, 1325 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, 1326 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, 1327 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, 1328 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, 1329 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, 1330 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, 1331 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, 1332 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, 1333 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, 1334 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, 1335 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, 1336 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, 1337 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, 1338 1339 { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), }, 1340 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1341 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, 1342 { .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), }, 1343 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), }, 1344 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), }, 1345 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, 1346 1347 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, 1348 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, 1349 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, 1350 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, 1351 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, 1352 1353 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, 1354 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, 1355 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, 1356 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, 1357 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, 1358 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, 1359 1360 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, 1361 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, 1362 { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), }, 1363 1364 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, 1365 { } 1366 }; 1367 1368 MODULE_DEVICE_TABLE(of, pca953x_dt_ids); 1369 1370 static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); 1371 1372 static struct i2c_driver pca953x_driver = { 1373 .driver = { 1374 .name = "pca953x", 1375 .pm = &pca953x_pm_ops, 1376 .of_match_table = pca953x_dt_ids, 1377 .acpi_match_table = pca953x_acpi_ids, 1378 }, 1379 .probe_new = pca953x_probe, 1380 .remove = pca953x_remove, 1381 .id_table = pca953x_id, 1382 }; 1383 1384 static int __init pca953x_init(void) 1385 { 1386 return i2c_add_driver(&pca953x_driver); 1387 } 1388 /* register after i2c postcore initcall and before 1389 * subsys initcalls that may rely on these GPIOs 1390 */ 1391 subsys_initcall(pca953x_init); 1392 1393 static void __exit pca953x_exit(void) 1394 { 1395 i2c_del_driver(&pca953x_driver); 1396 } 1397 module_exit(pca953x_exit); 1398 1399 MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); 1400 MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); 1401 MODULE_LICENSE("GPL"); 1402