1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCA953x 4/8/16/24/40 bit I/O ports 4 * 5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> 6 * Copyright (C) 2007 Marvell International Ltd. 7 * 8 * Derived from drivers/i2c/chips/pca9539.c 9 */ 10 11 #include <linux/acpi.h> 12 #include <linux/bitmap.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/i2c.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/module.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_data/pca953x.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/seq_file.h> 24 #include <linux/slab.h> 25 26 #include <asm/unaligned.h> 27 28 #define PCA953X_INPUT 0x00 29 #define PCA953X_OUTPUT 0x01 30 #define PCA953X_INVERT 0x02 31 #define PCA953X_DIRECTION 0x03 32 33 #define REG_ADDR_MASK GENMASK(5, 0) 34 #define REG_ADDR_EXT BIT(6) 35 #define REG_ADDR_AI BIT(7) 36 37 #define PCA957X_IN 0x00 38 #define PCA957X_INVRT 0x01 39 #define PCA957X_BKEN 0x02 40 #define PCA957X_PUPD 0x03 41 #define PCA957X_CFG 0x04 42 #define PCA957X_OUT 0x05 43 #define PCA957X_MSK 0x06 44 #define PCA957X_INTS 0x07 45 46 #define PCAL953X_OUT_STRENGTH 0x20 47 #define PCAL953X_IN_LATCH 0x22 48 #define PCAL953X_PULL_EN 0x23 49 #define PCAL953X_PULL_SEL 0x24 50 #define PCAL953X_INT_MASK 0x25 51 #define PCAL953X_INT_STAT 0x26 52 #define PCAL953X_OUT_CONF 0x27 53 54 #define PCAL6524_INT_EDGE 0x28 55 #define PCAL6524_INT_CLR 0x2a 56 #define PCAL6524_IN_STATUS 0x2b 57 #define PCAL6524_OUT_INDCONF 0x2c 58 #define PCAL6524_DEBOUNCE 0x2d 59 60 #define PCA_GPIO_MASK GENMASK(7, 0) 61 62 #define PCAL_GPIO_MASK GENMASK(4, 0) 63 #define PCAL_PINCTRL_MASK GENMASK(6, 5) 64 65 #define PCA_INT BIT(8) 66 #define PCA_PCAL BIT(9) 67 #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) 68 #define PCA953X_TYPE BIT(12) 69 #define PCA957X_TYPE BIT(13) 70 #define PCAL653X_TYPE BIT(14) 71 #define PCA_TYPE_MASK GENMASK(15, 12) 72 73 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) 74 75 static const struct i2c_device_id pca953x_id[] = { 76 { "pca6408", 8 | PCA953X_TYPE | PCA_INT, }, 77 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, 78 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, 79 { "pca9506", 40 | PCA953X_TYPE | PCA_INT, }, 80 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, 81 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, 82 { "pca9536", 4 | PCA953X_TYPE, }, 83 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, 84 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, 85 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, 86 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, 87 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, 88 { "pca9556", 8 | PCA953X_TYPE, }, 89 { "pca9557", 8 | PCA953X_TYPE, }, 90 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, 91 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, 92 { "pca9698", 40 | PCA953X_TYPE, }, 93 94 { "pcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 95 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 96 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, 97 { "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, }, 98 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 99 { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 100 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 101 102 { "max7310", 8 | PCA953X_TYPE, }, 103 { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, 104 { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, 105 { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, 106 { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, 107 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, 108 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, 109 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, 110 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, 111 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, 112 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, 113 { "xra1202", 8 | PCA953X_TYPE }, 114 { } 115 }; 116 MODULE_DEVICE_TABLE(i2c, pca953x_id); 117 118 #ifdef CONFIG_GPIO_PCA953X_IRQ 119 120 #include <linux/dmi.h> 121 122 static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true }; 123 124 static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = { 125 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, 126 { } 127 }; 128 129 static int pca953x_acpi_get_irq(struct device *dev) 130 { 131 int ret; 132 133 ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios); 134 if (ret) 135 dev_warn(dev, "can't add GPIO ACPI mapping\n"); 136 137 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq-gpios", 0); 138 if (ret < 0) 139 return ret; 140 141 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); 142 return ret; 143 } 144 145 static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = { 146 { 147 /* 148 * On Intel Galileo Gen 2 board the IRQ pin of one of 149 * the I²C GPIO expanders, which has GpioInt() resource, 150 * is provided as an absolute number instead of being 151 * relative. Since first controller (gpio-sch.c) and 152 * second (gpio-dwapb.c) are at the fixed bases, we may 153 * safely refer to the number in the global space to get 154 * an IRQ out of it. 155 */ 156 .matches = { 157 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 158 }, 159 }, 160 {} 161 }; 162 #endif 163 164 static const struct acpi_device_id pca953x_acpi_ids[] = { 165 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 166 { } 167 }; 168 MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); 169 170 #define MAX_BANK 5 171 #define BANK_SZ 8 172 #define MAX_LINE (MAX_BANK * BANK_SZ) 173 174 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) 175 176 struct pca953x_reg_config { 177 int direction; 178 int output; 179 int input; 180 int invert; 181 }; 182 183 static const struct pca953x_reg_config pca953x_regs = { 184 .direction = PCA953X_DIRECTION, 185 .output = PCA953X_OUTPUT, 186 .input = PCA953X_INPUT, 187 .invert = PCA953X_INVERT, 188 }; 189 190 static const struct pca953x_reg_config pca957x_regs = { 191 .direction = PCA957X_CFG, 192 .output = PCA957X_OUT, 193 .input = PCA957X_IN, 194 .invert = PCA957X_INVRT, 195 }; 196 197 struct pca953x_chip { 198 unsigned gpio_start; 199 struct mutex i2c_lock; 200 struct regmap *regmap; 201 202 #ifdef CONFIG_GPIO_PCA953X_IRQ 203 struct mutex irq_lock; 204 DECLARE_BITMAP(irq_mask, MAX_LINE); 205 DECLARE_BITMAP(irq_stat, MAX_LINE); 206 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 207 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 208 #endif 209 atomic_t wakeup_path; 210 211 struct i2c_client *client; 212 struct gpio_chip gpio_chip; 213 const char *const *names; 214 unsigned long driver_data; 215 struct regulator *regulator; 216 217 const struct pca953x_reg_config *regs; 218 219 u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off); 220 bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg, 221 u32 checkbank); 222 }; 223 224 static int pca953x_bank_shift(struct pca953x_chip *chip) 225 { 226 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); 227 } 228 229 #define PCA953x_BANK_INPUT BIT(0) 230 #define PCA953x_BANK_OUTPUT BIT(1) 231 #define PCA953x_BANK_POLARITY BIT(2) 232 #define PCA953x_BANK_CONFIG BIT(3) 233 234 #define PCA957x_BANK_INPUT BIT(0) 235 #define PCA957x_BANK_POLARITY BIT(1) 236 #define PCA957x_BANK_BUSHOLD BIT(2) 237 #define PCA957x_BANK_CONFIG BIT(4) 238 #define PCA957x_BANK_OUTPUT BIT(5) 239 240 #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) 241 #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) 242 #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) 243 #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) 244 #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) 245 246 /* 247 * We care about the following registers: 248 * - Standard set, below 0x40, each port can be replicated up to 8 times 249 * - PCA953x standard 250 * Input port 0x00 + 0 * bank_size R 251 * Output port 0x00 + 1 * bank_size RW 252 * Polarity Inversion port 0x00 + 2 * bank_size RW 253 * Configuration port 0x00 + 3 * bank_size RW 254 * - PCA957x with mixed up registers 255 * Input port 0x00 + 0 * bank_size R 256 * Polarity Inversion port 0x00 + 1 * bank_size RW 257 * Bus hold port 0x00 + 2 * bank_size RW 258 * Configuration port 0x00 + 4 * bank_size RW 259 * Output port 0x00 + 5 * bank_size RW 260 * 261 * - Extended set, above 0x40, often chip specific. 262 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: 263 * Input latch register 0x40 + 2 * bank_size RW 264 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW 265 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW 266 * Interrupt mask register 0x40 + 5 * bank_size RW 267 * Interrupt status register 0x40 + 6 * bank_size R 268 * 269 * - Registers with bit 0x80 set, the AI bit 270 * The bit is cleared and the registers fall into one of the 271 * categories above. 272 */ 273 274 static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, 275 u32 checkbank) 276 { 277 int bank_shift = pca953x_bank_shift(chip); 278 int bank = (reg & REG_ADDR_MASK) >> bank_shift; 279 int offset = reg & (BIT(bank_shift) - 1); 280 281 /* Special PCAL extended register check. */ 282 if (reg & REG_ADDR_EXT) { 283 if (!(chip->driver_data & PCA_PCAL)) 284 return false; 285 bank += 8; 286 } 287 288 /* Register is not in the matching bank. */ 289 if (!(BIT(bank) & checkbank)) 290 return false; 291 292 /* Register is not within allowed range of bank. */ 293 if (offset >= NBANK(chip)) 294 return false; 295 296 return true; 297 } 298 299 /* 300 * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the 301 * same register layout as the PCAL6524, the spacing of the registers has been 302 * fundamentally altered by compacting them and thus does not obey the same 303 * rules, including being able to use bit shifting to determine bank. These 304 * chips hence need special handling here. 305 */ 306 static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg, 307 u32 checkbank) 308 { 309 int bank_shift; 310 int bank; 311 int offset; 312 313 if (reg >= 0x54) { 314 /* 315 * Handle lack of reserved registers after output port 316 * configuration register to form a bank. 317 */ 318 reg -= 0x54; 319 bank_shift = 16; 320 } else if (reg >= 0x30) { 321 /* 322 * Reserved block between 14h and 2Fh does not align on 323 * expected bank boundaries like other devices. 324 */ 325 reg -= 0x30; 326 bank_shift = 8; 327 } else { 328 bank_shift = 0; 329 } 330 331 bank = bank_shift + reg / NBANK(chip); 332 offset = reg % NBANK(chip); 333 334 /* Register is not in the matching bank. */ 335 if (!(BIT(bank) & checkbank)) 336 return false; 337 338 /* Register is not within allowed range of bank. */ 339 if (offset >= NBANK(chip)) 340 return false; 341 342 return true; 343 } 344 345 static bool pca953x_readable_register(struct device *dev, unsigned int reg) 346 { 347 struct pca953x_chip *chip = dev_get_drvdata(dev); 348 u32 bank; 349 350 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 351 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | 352 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | 353 PCA957x_BANK_BUSHOLD; 354 } else { 355 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | 356 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; 357 } 358 359 if (chip->driver_data & PCA_PCAL) { 360 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 361 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | 362 PCAL9xxx_BANK_IRQ_STAT; 363 } 364 365 return chip->check_reg(chip, reg, bank); 366 } 367 368 static bool pca953x_writeable_register(struct device *dev, unsigned int reg) 369 { 370 struct pca953x_chip *chip = dev_get_drvdata(dev); 371 u32 bank; 372 373 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 374 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | 375 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; 376 } else { 377 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | 378 PCA953x_BANK_CONFIG; 379 } 380 381 if (chip->driver_data & PCA_PCAL) 382 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 383 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; 384 385 return chip->check_reg(chip, reg, bank); 386 } 387 388 static bool pca953x_volatile_register(struct device *dev, unsigned int reg) 389 { 390 struct pca953x_chip *chip = dev_get_drvdata(dev); 391 u32 bank; 392 393 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) 394 bank = PCA957x_BANK_INPUT; 395 else 396 bank = PCA953x_BANK_INPUT; 397 398 if (chip->driver_data & PCA_PCAL) 399 bank |= PCAL9xxx_BANK_IRQ_STAT; 400 401 return chip->check_reg(chip, reg, bank); 402 } 403 404 static const struct regmap_config pca953x_i2c_regmap = { 405 .reg_bits = 8, 406 .val_bits = 8, 407 408 .use_single_read = true, 409 .use_single_write = true, 410 411 .readable_reg = pca953x_readable_register, 412 .writeable_reg = pca953x_writeable_register, 413 .volatile_reg = pca953x_volatile_register, 414 415 .disable_locking = true, 416 .cache_type = REGCACHE_RBTREE, 417 .max_register = 0x7f, 418 }; 419 420 static const struct regmap_config pca953x_ai_i2c_regmap = { 421 .reg_bits = 8, 422 .val_bits = 8, 423 424 .read_flag_mask = REG_ADDR_AI, 425 .write_flag_mask = REG_ADDR_AI, 426 427 .readable_reg = pca953x_readable_register, 428 .writeable_reg = pca953x_writeable_register, 429 .volatile_reg = pca953x_volatile_register, 430 431 .disable_locking = true, 432 .cache_type = REGCACHE_RBTREE, 433 .max_register = 0x7f, 434 }; 435 436 static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off) 437 { 438 int bank_shift = pca953x_bank_shift(chip); 439 int addr = (reg & PCAL_GPIO_MASK) << bank_shift; 440 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; 441 u8 regaddr = pinctrl | addr | (off / BANK_SZ); 442 443 return regaddr; 444 } 445 446 /* 447 * The PCAL6534 and compatible chips have altered bank alignment that doesn't 448 * fit within the bit shifting scheme used for other devices. 449 */ 450 static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off) 451 { 452 int addr; 453 int pinctrl; 454 455 addr = (reg & PCAL_GPIO_MASK) * NBANK(chip); 456 457 switch (reg) { 458 case PCAL953X_OUT_STRENGTH: 459 case PCAL953X_IN_LATCH: 460 case PCAL953X_PULL_EN: 461 case PCAL953X_PULL_SEL: 462 case PCAL953X_INT_MASK: 463 case PCAL953X_INT_STAT: 464 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20; 465 break; 466 case PCAL6524_INT_EDGE: 467 case PCAL6524_INT_CLR: 468 case PCAL6524_IN_STATUS: 469 case PCAL6524_OUT_INDCONF: 470 case PCAL6524_DEBOUNCE: 471 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c; 472 break; 473 default: 474 pinctrl = 0; 475 break; 476 } 477 478 return pinctrl + addr + (off / BANK_SZ); 479 } 480 481 static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 482 { 483 u8 regaddr = chip->recalc_addr(chip, reg, 0); 484 u8 value[MAX_BANK]; 485 int i, ret; 486 487 for (i = 0; i < NBANK(chip); i++) 488 value[i] = bitmap_get_value8(val, i * BANK_SZ); 489 490 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip)); 491 if (ret < 0) { 492 dev_err(&chip->client->dev, "failed writing register\n"); 493 return ret; 494 } 495 496 return 0; 497 } 498 499 static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 500 { 501 u8 regaddr = chip->recalc_addr(chip, reg, 0); 502 u8 value[MAX_BANK]; 503 int i, ret; 504 505 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip)); 506 if (ret < 0) { 507 dev_err(&chip->client->dev, "failed reading register\n"); 508 return ret; 509 } 510 511 for (i = 0; i < NBANK(chip); i++) 512 bitmap_set_value8(val, value[i], i * BANK_SZ); 513 514 return 0; 515 } 516 517 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) 518 { 519 struct pca953x_chip *chip = gpiochip_get_data(gc); 520 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 521 u8 bit = BIT(off % BANK_SZ); 522 int ret; 523 524 mutex_lock(&chip->i2c_lock); 525 ret = regmap_write_bits(chip->regmap, dirreg, bit, bit); 526 mutex_unlock(&chip->i2c_lock); 527 return ret; 528 } 529 530 static int pca953x_gpio_direction_output(struct gpio_chip *gc, 531 unsigned off, int val) 532 { 533 struct pca953x_chip *chip = gpiochip_get_data(gc); 534 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 535 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 536 u8 bit = BIT(off % BANK_SZ); 537 int ret; 538 539 mutex_lock(&chip->i2c_lock); 540 /* set output level */ 541 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 542 if (ret) 543 goto exit; 544 545 /* then direction */ 546 ret = regmap_write_bits(chip->regmap, dirreg, bit, 0); 547 exit: 548 mutex_unlock(&chip->i2c_lock); 549 return ret; 550 } 551 552 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) 553 { 554 struct pca953x_chip *chip = gpiochip_get_data(gc); 555 u8 inreg = chip->recalc_addr(chip, chip->regs->input, off); 556 u8 bit = BIT(off % BANK_SZ); 557 u32 reg_val; 558 int ret; 559 560 mutex_lock(&chip->i2c_lock); 561 ret = regmap_read(chip->regmap, inreg, ®_val); 562 mutex_unlock(&chip->i2c_lock); 563 if (ret < 0) 564 return ret; 565 566 return !!(reg_val & bit); 567 } 568 569 static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) 570 { 571 struct pca953x_chip *chip = gpiochip_get_data(gc); 572 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 573 u8 bit = BIT(off % BANK_SZ); 574 575 mutex_lock(&chip->i2c_lock); 576 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 577 mutex_unlock(&chip->i2c_lock); 578 } 579 580 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) 581 { 582 struct pca953x_chip *chip = gpiochip_get_data(gc); 583 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 584 u8 bit = BIT(off % BANK_SZ); 585 u32 reg_val; 586 int ret; 587 588 mutex_lock(&chip->i2c_lock); 589 ret = regmap_read(chip->regmap, dirreg, ®_val); 590 mutex_unlock(&chip->i2c_lock); 591 if (ret < 0) 592 return ret; 593 594 if (reg_val & bit) 595 return GPIO_LINE_DIRECTION_IN; 596 597 return GPIO_LINE_DIRECTION_OUT; 598 } 599 600 static int pca953x_gpio_get_multiple(struct gpio_chip *gc, 601 unsigned long *mask, unsigned long *bits) 602 { 603 struct pca953x_chip *chip = gpiochip_get_data(gc); 604 DECLARE_BITMAP(reg_val, MAX_LINE); 605 int ret; 606 607 mutex_lock(&chip->i2c_lock); 608 ret = pca953x_read_regs(chip, chip->regs->input, reg_val); 609 mutex_unlock(&chip->i2c_lock); 610 if (ret) 611 return ret; 612 613 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio); 614 return 0; 615 } 616 617 static void pca953x_gpio_set_multiple(struct gpio_chip *gc, 618 unsigned long *mask, unsigned long *bits) 619 { 620 struct pca953x_chip *chip = gpiochip_get_data(gc); 621 DECLARE_BITMAP(reg_val, MAX_LINE); 622 int ret; 623 624 mutex_lock(&chip->i2c_lock); 625 ret = pca953x_read_regs(chip, chip->regs->output, reg_val); 626 if (ret) 627 goto exit; 628 629 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio); 630 631 pca953x_write_regs(chip, chip->regs->output, reg_val); 632 exit: 633 mutex_unlock(&chip->i2c_lock); 634 } 635 636 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, 637 unsigned int offset, 638 unsigned long config) 639 { 640 enum pin_config_param param = pinconf_to_config_param(config); 641 642 u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset); 643 u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset); 644 u8 bit = BIT(offset % BANK_SZ); 645 int ret; 646 647 /* 648 * pull-up/pull-down configuration requires PCAL extended 649 * registers 650 */ 651 if (!(chip->driver_data & PCA_PCAL)) 652 return -ENOTSUPP; 653 654 mutex_lock(&chip->i2c_lock); 655 656 /* Configure pull-up/pull-down */ 657 if (param == PIN_CONFIG_BIAS_PULL_UP) 658 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit); 659 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 660 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0); 661 else 662 ret = 0; 663 if (ret) 664 goto exit; 665 666 /* Disable/Enable pull-up/pull-down */ 667 if (param == PIN_CONFIG_BIAS_DISABLE) 668 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0); 669 else 670 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit); 671 672 exit: 673 mutex_unlock(&chip->i2c_lock); 674 return ret; 675 } 676 677 static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 678 unsigned long config) 679 { 680 struct pca953x_chip *chip = gpiochip_get_data(gc); 681 682 switch (pinconf_to_config_param(config)) { 683 case PIN_CONFIG_BIAS_PULL_UP: 684 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 685 case PIN_CONFIG_BIAS_PULL_DOWN: 686 case PIN_CONFIG_BIAS_DISABLE: 687 return pca953x_gpio_set_pull_up_down(chip, offset, config); 688 default: 689 return -ENOTSUPP; 690 } 691 } 692 693 static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) 694 { 695 struct gpio_chip *gc; 696 697 gc = &chip->gpio_chip; 698 699 gc->direction_input = pca953x_gpio_direction_input; 700 gc->direction_output = pca953x_gpio_direction_output; 701 gc->get = pca953x_gpio_get_value; 702 gc->set = pca953x_gpio_set_value; 703 gc->get_direction = pca953x_gpio_get_direction; 704 gc->get_multiple = pca953x_gpio_get_multiple; 705 gc->set_multiple = pca953x_gpio_set_multiple; 706 gc->set_config = pca953x_gpio_set_config; 707 gc->can_sleep = true; 708 709 gc->base = chip->gpio_start; 710 gc->ngpio = gpios; 711 gc->label = dev_name(&chip->client->dev); 712 gc->parent = &chip->client->dev; 713 gc->owner = THIS_MODULE; 714 gc->names = chip->names; 715 } 716 717 #ifdef CONFIG_GPIO_PCA953X_IRQ 718 static void pca953x_irq_mask(struct irq_data *d) 719 { 720 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 721 struct pca953x_chip *chip = gpiochip_get_data(gc); 722 irq_hw_number_t hwirq = irqd_to_hwirq(d); 723 724 clear_bit(hwirq, chip->irq_mask); 725 gpiochip_disable_irq(gc, hwirq); 726 } 727 728 static void pca953x_irq_unmask(struct irq_data *d) 729 { 730 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 731 struct pca953x_chip *chip = gpiochip_get_data(gc); 732 irq_hw_number_t hwirq = irqd_to_hwirq(d); 733 734 gpiochip_enable_irq(gc, hwirq); 735 set_bit(hwirq, chip->irq_mask); 736 } 737 738 static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) 739 { 740 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 741 struct pca953x_chip *chip = gpiochip_get_data(gc); 742 743 if (on) 744 atomic_inc(&chip->wakeup_path); 745 else 746 atomic_dec(&chip->wakeup_path); 747 748 return irq_set_irq_wake(chip->client->irq, on); 749 } 750 751 static void pca953x_irq_bus_lock(struct irq_data *d) 752 { 753 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 754 struct pca953x_chip *chip = gpiochip_get_data(gc); 755 756 mutex_lock(&chip->irq_lock); 757 } 758 759 static void pca953x_irq_bus_sync_unlock(struct irq_data *d) 760 { 761 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 762 struct pca953x_chip *chip = gpiochip_get_data(gc); 763 DECLARE_BITMAP(irq_mask, MAX_LINE); 764 DECLARE_BITMAP(reg_direction, MAX_LINE); 765 int level; 766 767 if (chip->driver_data & PCA_PCAL) { 768 /* Enable latch on interrupt-enabled inputs */ 769 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); 770 771 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio); 772 773 /* Unmask enabled interrupts */ 774 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask); 775 } 776 777 /* Switch direction to input if needed */ 778 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 779 780 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio); 781 bitmap_complement(reg_direction, reg_direction, gc->ngpio); 782 bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio); 783 784 /* Look for any newly setup interrupt */ 785 for_each_set_bit(level, irq_mask, gc->ngpio) 786 pca953x_gpio_direction_input(&chip->gpio_chip, level); 787 788 mutex_unlock(&chip->irq_lock); 789 } 790 791 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) 792 { 793 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 794 struct pca953x_chip *chip = gpiochip_get_data(gc); 795 irq_hw_number_t hwirq = irqd_to_hwirq(d); 796 797 if (!(type & IRQ_TYPE_EDGE_BOTH)) { 798 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", 799 d->irq, type); 800 return -EINVAL; 801 } 802 803 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING); 804 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING); 805 806 return 0; 807 } 808 809 static void pca953x_irq_shutdown(struct irq_data *d) 810 { 811 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 812 struct pca953x_chip *chip = gpiochip_get_data(gc); 813 irq_hw_number_t hwirq = irqd_to_hwirq(d); 814 815 clear_bit(hwirq, chip->irq_trig_raise); 816 clear_bit(hwirq, chip->irq_trig_fall); 817 } 818 819 static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p) 820 { 821 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 822 823 seq_printf(p, dev_name(gc->parent)); 824 } 825 826 static const struct irq_chip pca953x_irq_chip = { 827 .irq_mask = pca953x_irq_mask, 828 .irq_unmask = pca953x_irq_unmask, 829 .irq_set_wake = pca953x_irq_set_wake, 830 .irq_bus_lock = pca953x_irq_bus_lock, 831 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, 832 .irq_set_type = pca953x_irq_set_type, 833 .irq_shutdown = pca953x_irq_shutdown, 834 .irq_print_chip = pca953x_irq_print_chip, 835 .flags = IRQCHIP_IMMUTABLE, 836 GPIOCHIP_IRQ_RESOURCE_HELPERS, 837 }; 838 839 static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending) 840 { 841 struct gpio_chip *gc = &chip->gpio_chip; 842 DECLARE_BITMAP(reg_direction, MAX_LINE); 843 DECLARE_BITMAP(old_stat, MAX_LINE); 844 DECLARE_BITMAP(cur_stat, MAX_LINE); 845 DECLARE_BITMAP(new_stat, MAX_LINE); 846 DECLARE_BITMAP(trigger, MAX_LINE); 847 int ret; 848 849 if (chip->driver_data & PCA_PCAL) { 850 /* Read the current interrupt status from the device */ 851 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); 852 if (ret) 853 return false; 854 855 /* Check latched inputs and clear interrupt status */ 856 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 857 if (ret) 858 return false; 859 860 /* Apply filter for rising/falling edge selection */ 861 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio); 862 863 bitmap_and(pending, new_stat, trigger, gc->ngpio); 864 865 return !bitmap_empty(pending, gc->ngpio); 866 } 867 868 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 869 if (ret) 870 return false; 871 872 /* Remove output pins from the equation */ 873 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 874 875 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio); 876 877 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio); 878 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio); 879 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio); 880 881 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio); 882 883 if (bitmap_empty(trigger, gc->ngpio)) 884 return false; 885 886 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio); 887 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio); 888 bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio); 889 bitmap_and(pending, new_stat, trigger, gc->ngpio); 890 891 return !bitmap_empty(pending, gc->ngpio); 892 } 893 894 static irqreturn_t pca953x_irq_handler(int irq, void *devid) 895 { 896 struct pca953x_chip *chip = devid; 897 struct gpio_chip *gc = &chip->gpio_chip; 898 DECLARE_BITMAP(pending, MAX_LINE); 899 int level; 900 bool ret; 901 902 bitmap_zero(pending, MAX_LINE); 903 904 mutex_lock(&chip->i2c_lock); 905 ret = pca953x_irq_pending(chip, pending); 906 mutex_unlock(&chip->i2c_lock); 907 908 if (ret) { 909 ret = 0; 910 911 for_each_set_bit(level, pending, gc->ngpio) { 912 int nested_irq = irq_find_mapping(gc->irq.domain, level); 913 914 if (unlikely(nested_irq <= 0)) { 915 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); 916 continue; 917 } 918 919 handle_nested_irq(nested_irq); 920 ret = 1; 921 } 922 } 923 924 return IRQ_RETVAL(ret); 925 } 926 927 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 928 { 929 struct i2c_client *client = chip->client; 930 DECLARE_BITMAP(reg_direction, MAX_LINE); 931 DECLARE_BITMAP(irq_stat, MAX_LINE); 932 struct gpio_irq_chip *girq; 933 int ret; 934 935 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) { 936 ret = pca953x_acpi_get_irq(&client->dev); 937 if (ret > 0) 938 client->irq = ret; 939 } 940 941 if (!client->irq) 942 return 0; 943 944 if (irq_base == -1) 945 return 0; 946 947 if (!(chip->driver_data & PCA_INT)) 948 return 0; 949 950 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat); 951 if (ret) 952 return ret; 953 954 /* 955 * There is no way to know which GPIO line generated the 956 * interrupt. We have to rely on the previous read for 957 * this purpose. 958 */ 959 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 960 bitmap_and(chip->irq_stat, irq_stat, reg_direction, chip->gpio_chip.ngpio); 961 mutex_init(&chip->irq_lock); 962 963 girq = &chip->gpio_chip.irq; 964 gpio_irq_chip_set_chip(girq, &pca953x_irq_chip); 965 /* This will let us handle the parent IRQ in the driver */ 966 girq->parent_handler = NULL; 967 girq->num_parents = 0; 968 girq->parents = NULL; 969 girq->default_type = IRQ_TYPE_NONE; 970 girq->handler = handle_simple_irq; 971 girq->threaded = true; 972 girq->first = irq_base; /* FIXME: get rid of this */ 973 974 ret = devm_request_threaded_irq(&client->dev, client->irq, 975 NULL, pca953x_irq_handler, 976 IRQF_ONESHOT | IRQF_SHARED, 977 dev_name(&client->dev), chip); 978 if (ret) { 979 dev_err(&client->dev, "failed to request irq %d\n", 980 client->irq); 981 return ret; 982 } 983 984 return 0; 985 } 986 987 #else /* CONFIG_GPIO_PCA953X_IRQ */ 988 static int pca953x_irq_setup(struct pca953x_chip *chip, 989 int irq_base) 990 { 991 struct i2c_client *client = chip->client; 992 993 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) 994 dev_warn(&client->dev, "interrupt support not compiled in\n"); 995 996 return 0; 997 } 998 #endif 999 1000 static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert) 1001 { 1002 DECLARE_BITMAP(val, MAX_LINE); 1003 u8 regaddr; 1004 int ret; 1005 1006 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1007 ret = regcache_sync_region(chip->regmap, regaddr, 1008 regaddr + NBANK(chip) - 1); 1009 if (ret) 1010 goto out; 1011 1012 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1013 ret = regcache_sync_region(chip->regmap, regaddr, 1014 regaddr + NBANK(chip) - 1); 1015 if (ret) 1016 goto out; 1017 1018 /* set platform specific polarity inversion */ 1019 if (invert) 1020 bitmap_fill(val, MAX_LINE); 1021 else 1022 bitmap_zero(val, MAX_LINE); 1023 1024 ret = pca953x_write_regs(chip, chip->regs->invert, val); 1025 out: 1026 return ret; 1027 } 1028 1029 static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) 1030 { 1031 DECLARE_BITMAP(val, MAX_LINE); 1032 unsigned int i; 1033 int ret; 1034 1035 ret = device_pca95xx_init(chip, invert); 1036 if (ret) 1037 goto out; 1038 1039 /* To enable register 6, 7 to control pull up and pull down */ 1040 for (i = 0; i < NBANK(chip); i++) 1041 bitmap_set_value8(val, 0x02, i * BANK_SZ); 1042 1043 ret = pca953x_write_regs(chip, PCA957X_BKEN, val); 1044 if (ret) 1045 goto out; 1046 1047 return 0; 1048 out: 1049 return ret; 1050 } 1051 1052 static int pca953x_probe(struct i2c_client *client) 1053 { 1054 const struct i2c_device_id *i2c_id = i2c_client_get_device_id(client); 1055 struct pca953x_platform_data *pdata; 1056 struct pca953x_chip *chip; 1057 int irq_base = 0; 1058 int ret; 1059 u32 invert = 0; 1060 struct regulator *reg; 1061 const struct regmap_config *regmap_config; 1062 1063 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); 1064 if (chip == NULL) 1065 return -ENOMEM; 1066 1067 pdata = dev_get_platdata(&client->dev); 1068 if (pdata) { 1069 irq_base = pdata->irq_base; 1070 chip->gpio_start = pdata->gpio_base; 1071 invert = pdata->invert; 1072 chip->names = pdata->names; 1073 } else { 1074 struct gpio_desc *reset_gpio; 1075 1076 chip->gpio_start = -1; 1077 irq_base = 0; 1078 1079 /* 1080 * See if we need to de-assert a reset pin. 1081 * 1082 * There is no known ACPI-enabled platforms that are 1083 * using "reset" GPIO. Otherwise any of those platform 1084 * must use _DSD method with corresponding property. 1085 */ 1086 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1087 GPIOD_OUT_LOW); 1088 if (IS_ERR(reset_gpio)) 1089 return PTR_ERR(reset_gpio); 1090 } 1091 1092 chip->client = client; 1093 1094 reg = devm_regulator_get(&client->dev, "vcc"); 1095 if (IS_ERR(reg)) 1096 return dev_err_probe(&client->dev, PTR_ERR(reg), "reg get err\n"); 1097 1098 ret = regulator_enable(reg); 1099 if (ret) { 1100 dev_err(&client->dev, "reg en err: %d\n", ret); 1101 return ret; 1102 } 1103 chip->regulator = reg; 1104 1105 if (i2c_id) { 1106 chip->driver_data = i2c_id->driver_data; 1107 } else { 1108 const void *match; 1109 1110 match = device_get_match_data(&client->dev); 1111 if (!match) { 1112 ret = -ENODEV; 1113 goto err_exit; 1114 } 1115 1116 chip->driver_data = (uintptr_t)match; 1117 } 1118 1119 i2c_set_clientdata(client, chip); 1120 1121 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); 1122 1123 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 1124 dev_info(&client->dev, "using AI\n"); 1125 regmap_config = &pca953x_ai_i2c_regmap; 1126 } else { 1127 dev_info(&client->dev, "using no AI\n"); 1128 regmap_config = &pca953x_i2c_regmap; 1129 } 1130 1131 if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) { 1132 chip->recalc_addr = pcal6534_recalc_addr; 1133 chip->check_reg = pcal6534_check_register; 1134 } else { 1135 chip->recalc_addr = pca953x_recalc_addr; 1136 chip->check_reg = pca953x_check_register; 1137 } 1138 1139 chip->regmap = devm_regmap_init_i2c(client, regmap_config); 1140 if (IS_ERR(chip->regmap)) { 1141 ret = PTR_ERR(chip->regmap); 1142 goto err_exit; 1143 } 1144 1145 regcache_mark_dirty(chip->regmap); 1146 1147 mutex_init(&chip->i2c_lock); 1148 /* 1149 * In case we have an i2c-mux controlled by a GPIO provided by an 1150 * expander using the same driver higher on the device tree, read the 1151 * i2c adapter nesting depth and use the retrieved value as lockdep 1152 * subclass for chip->i2c_lock. 1153 * 1154 * REVISIT: This solution is not complete. It protects us from lockdep 1155 * false positives when the expander controlling the i2c-mux is on 1156 * a different level on the device tree, but not when it's on the same 1157 * level on a different branch (in which case the subclass number 1158 * would be the same). 1159 * 1160 * TODO: Once a correct solution is developed, a similar fix should be 1161 * applied to all other i2c-controlled GPIO expanders (and potentially 1162 * regmap-i2c). 1163 */ 1164 lockdep_set_subclass(&chip->i2c_lock, 1165 i2c_adapter_depth(client->adapter)); 1166 1167 /* initialize cached registers from their original values. 1168 * we can't share this chip with another i2c master. 1169 */ 1170 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 1171 chip->regs = &pca957x_regs; 1172 ret = device_pca957x_init(chip, invert); 1173 } else { 1174 chip->regs = &pca953x_regs; 1175 ret = device_pca95xx_init(chip, invert); 1176 } 1177 if (ret) 1178 goto err_exit; 1179 1180 ret = pca953x_irq_setup(chip, irq_base); 1181 if (ret) 1182 goto err_exit; 1183 1184 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); 1185 if (ret) 1186 goto err_exit; 1187 1188 if (pdata && pdata->setup) { 1189 ret = pdata->setup(client, chip->gpio_chip.base, 1190 chip->gpio_chip.ngpio, pdata->context); 1191 if (ret < 0) 1192 dev_warn(&client->dev, "setup failed, %d\n", ret); 1193 } 1194 1195 return 0; 1196 1197 err_exit: 1198 regulator_disable(chip->regulator); 1199 return ret; 1200 } 1201 1202 static void pca953x_remove(struct i2c_client *client) 1203 { 1204 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); 1205 struct pca953x_chip *chip = i2c_get_clientdata(client); 1206 1207 if (pdata && pdata->teardown) { 1208 pdata->teardown(client, chip->gpio_chip.base, 1209 chip->gpio_chip.ngpio, pdata->context); 1210 } 1211 1212 regulator_disable(chip->regulator); 1213 } 1214 1215 #ifdef CONFIG_PM_SLEEP 1216 static int pca953x_regcache_sync(struct device *dev) 1217 { 1218 struct pca953x_chip *chip = dev_get_drvdata(dev); 1219 int ret; 1220 u8 regaddr; 1221 1222 /* 1223 * The ordering between direction and output is important, 1224 * sync these registers first and only then sync the rest. 1225 */ 1226 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1227 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1228 if (ret) { 1229 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); 1230 return ret; 1231 } 1232 1233 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1234 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1235 if (ret) { 1236 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); 1237 return ret; 1238 } 1239 1240 #ifdef CONFIG_GPIO_PCA953X_IRQ 1241 if (chip->driver_data & PCA_PCAL) { 1242 regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0); 1243 ret = regcache_sync_region(chip->regmap, regaddr, 1244 regaddr + NBANK(chip) - 1); 1245 if (ret) { 1246 dev_err(dev, "Failed to sync INT latch registers: %d\n", 1247 ret); 1248 return ret; 1249 } 1250 1251 regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0); 1252 ret = regcache_sync_region(chip->regmap, regaddr, 1253 regaddr + NBANK(chip) - 1); 1254 if (ret) { 1255 dev_err(dev, "Failed to sync INT mask registers: %d\n", 1256 ret); 1257 return ret; 1258 } 1259 } 1260 #endif 1261 1262 return 0; 1263 } 1264 1265 static int pca953x_suspend(struct device *dev) 1266 { 1267 struct pca953x_chip *chip = dev_get_drvdata(dev); 1268 1269 mutex_lock(&chip->i2c_lock); 1270 regcache_cache_only(chip->regmap, true); 1271 mutex_unlock(&chip->i2c_lock); 1272 1273 if (atomic_read(&chip->wakeup_path)) 1274 device_set_wakeup_path(dev); 1275 else 1276 regulator_disable(chip->regulator); 1277 1278 return 0; 1279 } 1280 1281 static int pca953x_resume(struct device *dev) 1282 { 1283 struct pca953x_chip *chip = dev_get_drvdata(dev); 1284 int ret; 1285 1286 if (!atomic_read(&chip->wakeup_path)) { 1287 ret = regulator_enable(chip->regulator); 1288 if (ret) { 1289 dev_err(dev, "Failed to enable regulator: %d\n", ret); 1290 return 0; 1291 } 1292 } 1293 1294 mutex_lock(&chip->i2c_lock); 1295 regcache_cache_only(chip->regmap, false); 1296 regcache_mark_dirty(chip->regmap); 1297 ret = pca953x_regcache_sync(dev); 1298 if (ret) { 1299 mutex_unlock(&chip->i2c_lock); 1300 return ret; 1301 } 1302 1303 ret = regcache_sync(chip->regmap); 1304 mutex_unlock(&chip->i2c_lock); 1305 if (ret) { 1306 dev_err(dev, "Failed to restore register map: %d\n", ret); 1307 return ret; 1308 } 1309 1310 return 0; 1311 } 1312 #endif 1313 1314 /* convenience to stop overlong match-table lines */ 1315 #define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int)) 1316 #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) 1317 #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) 1318 1319 static const struct of_device_id pca953x_dt_ids[] = { 1320 { .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), }, 1321 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, 1322 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, 1323 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), }, 1324 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, 1325 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, 1326 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, 1327 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, 1328 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, 1329 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, 1330 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, 1331 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, 1332 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, 1333 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, 1334 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, 1335 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, 1336 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, 1337 1338 { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), }, 1339 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1340 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, 1341 { .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), }, 1342 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), }, 1343 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), }, 1344 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, 1345 1346 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, 1347 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, 1348 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, 1349 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, 1350 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, 1351 1352 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, 1353 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, 1354 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, 1355 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, 1356 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, 1357 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, 1358 1359 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, 1360 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, 1361 { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), }, 1362 1363 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, 1364 { } 1365 }; 1366 1367 MODULE_DEVICE_TABLE(of, pca953x_dt_ids); 1368 1369 static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); 1370 1371 static struct i2c_driver pca953x_driver = { 1372 .driver = { 1373 .name = "pca953x", 1374 .pm = &pca953x_pm_ops, 1375 .of_match_table = pca953x_dt_ids, 1376 .acpi_match_table = pca953x_acpi_ids, 1377 }, 1378 .probe = pca953x_probe, 1379 .remove = pca953x_remove, 1380 .id_table = pca953x_id, 1381 }; 1382 1383 static int __init pca953x_init(void) 1384 { 1385 return i2c_add_driver(&pca953x_driver); 1386 } 1387 /* register after i2c postcore initcall and before 1388 * subsys initcalls that may rely on these GPIOs 1389 */ 1390 subsys_initcall(pca953x_init); 1391 1392 static void __exit pca953x_exit(void) 1393 { 1394 i2c_del_driver(&pca953x_driver); 1395 } 1396 module_exit(pca953x_exit); 1397 1398 MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); 1399 MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); 1400 MODULE_LICENSE("GPL"); 1401