1 /* 2 * PCA953x 4/8/16/24/40 bit I/O ports 3 * 4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> 5 * Copyright (C) 2007 Marvell International Ltd. 6 * 7 * Derived from drivers/i2c/chips/pca9539.c 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; version 2 of the License. 12 */ 13 14 #include <linux/acpi.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/i2c.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/module.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_data/pca953x.h> 23 #include <linux/regmap.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/slab.h> 26 27 #include <asm/unaligned.h> 28 29 #define PCA953X_INPUT 0x00 30 #define PCA953X_OUTPUT 0x01 31 #define PCA953X_INVERT 0x02 32 #define PCA953X_DIRECTION 0x03 33 34 #define REG_ADDR_MASK 0x3f 35 #define REG_ADDR_EXT 0x40 36 #define REG_ADDR_AI 0x80 37 38 #define PCA957X_IN 0x00 39 #define PCA957X_INVRT 0x01 40 #define PCA957X_BKEN 0x02 41 #define PCA957X_PUPD 0x03 42 #define PCA957X_CFG 0x04 43 #define PCA957X_OUT 0x05 44 #define PCA957X_MSK 0x06 45 #define PCA957X_INTS 0x07 46 47 #define PCAL953X_OUT_STRENGTH 0x20 48 #define PCAL953X_IN_LATCH 0x22 49 #define PCAL953X_PULL_EN 0x23 50 #define PCAL953X_PULL_SEL 0x24 51 #define PCAL953X_INT_MASK 0x25 52 #define PCAL953X_INT_STAT 0x26 53 #define PCAL953X_OUT_CONF 0x27 54 55 #define PCAL6524_INT_EDGE 0x28 56 #define PCAL6524_INT_CLR 0x2a 57 #define PCAL6524_IN_STATUS 0x2b 58 #define PCAL6524_OUT_INDCONF 0x2c 59 #define PCAL6524_DEBOUNCE 0x2d 60 61 #define PCA_GPIO_MASK 0x00FF 62 63 #define PCAL_GPIO_MASK 0x1f 64 #define PCAL_PINCTRL_MASK 0x60 65 66 #define PCA_INT 0x0100 67 #define PCA_PCAL 0x0200 68 #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) 69 #define PCA953X_TYPE 0x1000 70 #define PCA957X_TYPE 0x2000 71 #define PCA_TYPE_MASK 0xF000 72 73 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) 74 75 static const struct i2c_device_id pca953x_id[] = { 76 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, 77 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, 78 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, 79 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, 80 { "pca9536", 4 | PCA953X_TYPE, }, 81 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, 82 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, 83 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, 84 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, 85 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, 86 { "pca9556", 8 | PCA953X_TYPE, }, 87 { "pca9557", 8 | PCA953X_TYPE, }, 88 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, 89 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, 90 { "pca9698", 40 | PCA953X_TYPE, }, 91 92 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 93 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, 94 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 95 96 { "max7310", 8 | PCA953X_TYPE, }, 97 { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, 98 { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, 99 { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, 100 { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, 101 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, 102 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, 103 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, 104 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, 105 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, 106 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, 107 { "xra1202", 8 | PCA953X_TYPE }, 108 { } 109 }; 110 MODULE_DEVICE_TABLE(i2c, pca953x_id); 111 112 static const struct acpi_device_id pca953x_acpi_ids[] = { 113 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 114 { } 115 }; 116 MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); 117 118 #define MAX_BANK 5 119 #define BANK_SZ 8 120 121 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) 122 123 struct pca953x_reg_config { 124 int direction; 125 int output; 126 int input; 127 int invert; 128 }; 129 130 static const struct pca953x_reg_config pca953x_regs = { 131 .direction = PCA953X_DIRECTION, 132 .output = PCA953X_OUTPUT, 133 .input = PCA953X_INPUT, 134 .invert = PCA953X_INVERT, 135 }; 136 137 static const struct pca953x_reg_config pca957x_regs = { 138 .direction = PCA957X_CFG, 139 .output = PCA957X_OUT, 140 .input = PCA957X_IN, 141 .invert = PCA957X_INVRT, 142 }; 143 144 struct pca953x_chip { 145 unsigned gpio_start; 146 struct mutex i2c_lock; 147 struct regmap *regmap; 148 149 #ifdef CONFIG_GPIO_PCA953X_IRQ 150 struct mutex irq_lock; 151 u8 irq_mask[MAX_BANK]; 152 u8 irq_stat[MAX_BANK]; 153 u8 irq_trig_raise[MAX_BANK]; 154 u8 irq_trig_fall[MAX_BANK]; 155 struct irq_chip irq_chip; 156 #endif 157 atomic_t wakeup_path; 158 159 struct i2c_client *client; 160 struct gpio_chip gpio_chip; 161 const char *const *names; 162 unsigned long driver_data; 163 struct regulator *regulator; 164 165 const struct pca953x_reg_config *regs; 166 }; 167 168 static int pca953x_bank_shift(struct pca953x_chip *chip) 169 { 170 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); 171 } 172 173 #define PCA953x_BANK_INPUT BIT(0) 174 #define PCA953x_BANK_OUTPUT BIT(1) 175 #define PCA953x_BANK_POLARITY BIT(2) 176 #define PCA953x_BANK_CONFIG BIT(3) 177 178 #define PCA957x_BANK_INPUT BIT(0) 179 #define PCA957x_BANK_POLARITY BIT(1) 180 #define PCA957x_BANK_BUSHOLD BIT(2) 181 #define PCA957x_BANK_CONFIG BIT(4) 182 #define PCA957x_BANK_OUTPUT BIT(5) 183 184 #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) 185 #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) 186 #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) 187 #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) 188 #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) 189 190 /* 191 * We care about the following registers: 192 * - Standard set, below 0x40, each port can be replicated up to 8 times 193 * - PCA953x standard 194 * Input port 0x00 + 0 * bank_size R 195 * Output port 0x00 + 1 * bank_size RW 196 * Polarity Inversion port 0x00 + 2 * bank_size RW 197 * Configuration port 0x00 + 3 * bank_size RW 198 * - PCA957x with mixed up registers 199 * Input port 0x00 + 0 * bank_size R 200 * Polarity Inversion port 0x00 + 1 * bank_size RW 201 * Bus hold port 0x00 + 2 * bank_size RW 202 * Configuration port 0x00 + 4 * bank_size RW 203 * Output port 0x00 + 5 * bank_size RW 204 * 205 * - Extended set, above 0x40, often chip specific. 206 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: 207 * Input latch register 0x40 + 2 * bank_size RW 208 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW 209 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW 210 * Interrupt mask register 0x40 + 5 * bank_size RW 211 * Interrupt status register 0x40 + 6 * bank_size R 212 * 213 * - Registers with bit 0x80 set, the AI bit 214 * The bit is cleared and the registers fall into one of the 215 * categories above. 216 */ 217 218 static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, 219 u32 checkbank) 220 { 221 int bank_shift = pca953x_bank_shift(chip); 222 int bank = (reg & REG_ADDR_MASK) >> bank_shift; 223 int offset = reg & (BIT(bank_shift) - 1); 224 225 /* Special PCAL extended register check. */ 226 if (reg & REG_ADDR_EXT) { 227 if (!(chip->driver_data & PCA_PCAL)) 228 return false; 229 bank += 8; 230 } 231 232 /* Register is not in the matching bank. */ 233 if (!(BIT(bank) & checkbank)) 234 return false; 235 236 /* Register is not within allowed range of bank. */ 237 if (offset >= NBANK(chip)) 238 return false; 239 240 return true; 241 } 242 243 static bool pca953x_readable_register(struct device *dev, unsigned int reg) 244 { 245 struct pca953x_chip *chip = dev_get_drvdata(dev); 246 u32 bank; 247 248 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { 249 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | 250 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; 251 } else { 252 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | 253 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | 254 PCA957x_BANK_BUSHOLD; 255 } 256 257 if (chip->driver_data & PCA_PCAL) { 258 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 259 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | 260 PCAL9xxx_BANK_IRQ_STAT; 261 } 262 263 return pca953x_check_register(chip, reg, bank); 264 } 265 266 static bool pca953x_writeable_register(struct device *dev, unsigned int reg) 267 { 268 struct pca953x_chip *chip = dev_get_drvdata(dev); 269 u32 bank; 270 271 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { 272 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | 273 PCA953x_BANK_CONFIG; 274 } else { 275 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | 276 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; 277 } 278 279 if (chip->driver_data & PCA_PCAL) 280 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 281 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; 282 283 return pca953x_check_register(chip, reg, bank); 284 } 285 286 static bool pca953x_volatile_register(struct device *dev, unsigned int reg) 287 { 288 struct pca953x_chip *chip = dev_get_drvdata(dev); 289 u32 bank; 290 291 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) 292 bank = PCA953x_BANK_INPUT; 293 else 294 bank = PCA957x_BANK_INPUT; 295 296 if (chip->driver_data & PCA_PCAL) 297 bank |= PCAL9xxx_BANK_IRQ_STAT; 298 299 return pca953x_check_register(chip, reg, bank); 300 } 301 302 static const struct regmap_config pca953x_i2c_regmap = { 303 .reg_bits = 8, 304 .val_bits = 8, 305 306 .readable_reg = pca953x_readable_register, 307 .writeable_reg = pca953x_writeable_register, 308 .volatile_reg = pca953x_volatile_register, 309 310 .cache_type = REGCACHE_RBTREE, 311 .max_register = 0x7f, 312 }; 313 314 static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off, 315 bool write, bool addrinc) 316 { 317 int bank_shift = pca953x_bank_shift(chip); 318 int addr = (reg & PCAL_GPIO_MASK) << bank_shift; 319 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; 320 u8 regaddr = pinctrl | addr | (off / BANK_SZ); 321 322 /* Single byte read doesn't need AI bit set. */ 323 if (!addrinc) 324 return regaddr; 325 326 /* Chips with 24 and more GPIOs always support Auto Increment */ 327 if (write && NBANK(chip) > 2) 328 regaddr |= REG_ADDR_AI; 329 330 /* PCA9575 needs address-increment on multi-byte writes */ 331 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) 332 regaddr |= REG_ADDR_AI; 333 334 return regaddr; 335 } 336 337 static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) 338 { 339 u8 regaddr = pca953x_recalc_addr(chip, reg, 0, true, true); 340 int ret; 341 342 ret = regmap_bulk_write(chip->regmap, regaddr, val, NBANK(chip)); 343 if (ret < 0) { 344 dev_err(&chip->client->dev, "failed writing register\n"); 345 return ret; 346 } 347 348 return 0; 349 } 350 351 static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) 352 { 353 u8 regaddr = pca953x_recalc_addr(chip, reg, 0, false, true); 354 int ret; 355 356 ret = regmap_bulk_read(chip->regmap, regaddr, val, NBANK(chip)); 357 if (ret < 0) { 358 dev_err(&chip->client->dev, "failed reading register\n"); 359 return ret; 360 } 361 362 return 0; 363 } 364 365 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) 366 { 367 struct pca953x_chip *chip = gpiochip_get_data(gc); 368 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, 369 true, false); 370 u8 bit = BIT(off % BANK_SZ); 371 int ret; 372 373 mutex_lock(&chip->i2c_lock); 374 ret = regmap_write_bits(chip->regmap, dirreg, bit, bit); 375 mutex_unlock(&chip->i2c_lock); 376 return ret; 377 } 378 379 static int pca953x_gpio_direction_output(struct gpio_chip *gc, 380 unsigned off, int val) 381 { 382 struct pca953x_chip *chip = gpiochip_get_data(gc); 383 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, 384 true, false); 385 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, 386 true, false); 387 u8 bit = BIT(off % BANK_SZ); 388 int ret; 389 390 mutex_lock(&chip->i2c_lock); 391 /* set output level */ 392 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 393 if (ret) 394 goto exit; 395 396 /* then direction */ 397 ret = regmap_write_bits(chip->regmap, dirreg, bit, 0); 398 exit: 399 mutex_unlock(&chip->i2c_lock); 400 return ret; 401 } 402 403 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) 404 { 405 struct pca953x_chip *chip = gpiochip_get_data(gc); 406 u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off, 407 true, false); 408 u8 bit = BIT(off % BANK_SZ); 409 u32 reg_val; 410 int ret; 411 412 mutex_lock(&chip->i2c_lock); 413 ret = regmap_read(chip->regmap, inreg, ®_val); 414 mutex_unlock(&chip->i2c_lock); 415 if (ret < 0) { 416 /* NOTE: diagnostic already emitted; that's all we should 417 * do unless gpio_*_value_cansleep() calls become different 418 * from their nonsleeping siblings (and report faults). 419 */ 420 return 0; 421 } 422 423 return !!(reg_val & bit); 424 } 425 426 static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) 427 { 428 struct pca953x_chip *chip = gpiochip_get_data(gc); 429 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, 430 true, false); 431 u8 bit = BIT(off % BANK_SZ); 432 433 mutex_lock(&chip->i2c_lock); 434 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 435 mutex_unlock(&chip->i2c_lock); 436 } 437 438 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) 439 { 440 struct pca953x_chip *chip = gpiochip_get_data(gc); 441 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, 442 true, false); 443 u8 bit = BIT(off % BANK_SZ); 444 u32 reg_val; 445 int ret; 446 447 mutex_lock(&chip->i2c_lock); 448 ret = regmap_read(chip->regmap, dirreg, ®_val); 449 mutex_unlock(&chip->i2c_lock); 450 if (ret < 0) 451 return ret; 452 453 return !!(reg_val & bit); 454 } 455 456 static void pca953x_gpio_set_multiple(struct gpio_chip *gc, 457 unsigned long *mask, unsigned long *bits) 458 { 459 struct pca953x_chip *chip = gpiochip_get_data(gc); 460 unsigned int bank_mask, bank_val; 461 int bank; 462 u8 reg_val[MAX_BANK]; 463 int ret; 464 465 mutex_lock(&chip->i2c_lock); 466 ret = pca953x_read_regs(chip, chip->regs->output, reg_val); 467 if (ret) 468 goto exit; 469 470 for (bank = 0; bank < NBANK(chip); bank++) { 471 bank_mask = mask[bank / sizeof(*mask)] >> 472 ((bank % sizeof(*mask)) * 8); 473 if (bank_mask) { 474 bank_val = bits[bank / sizeof(*bits)] >> 475 ((bank % sizeof(*bits)) * 8); 476 bank_val &= bank_mask; 477 reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val; 478 } 479 } 480 481 pca953x_write_regs(chip, chip->regs->output, reg_val); 482 exit: 483 mutex_unlock(&chip->i2c_lock); 484 } 485 486 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, 487 unsigned int offset, 488 unsigned long config) 489 { 490 u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset, 491 true, false); 492 u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset, 493 true, false); 494 u8 bit = BIT(offset % BANK_SZ); 495 int ret; 496 497 /* 498 * pull-up/pull-down configuration requires PCAL extended 499 * registers 500 */ 501 if (!(chip->driver_data & PCA_PCAL)) 502 return -ENOTSUPP; 503 504 mutex_lock(&chip->i2c_lock); 505 506 /* Disable pull-up/pull-down */ 507 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0); 508 if (ret) 509 goto exit; 510 511 /* Configure pull-up/pull-down */ 512 if (config == PIN_CONFIG_BIAS_PULL_UP) 513 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit); 514 else if (config == PIN_CONFIG_BIAS_PULL_DOWN) 515 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0); 516 if (ret) 517 goto exit; 518 519 /* Enable pull-up/pull-down */ 520 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit); 521 522 exit: 523 mutex_unlock(&chip->i2c_lock); 524 return ret; 525 } 526 527 static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 528 unsigned long config) 529 { 530 struct pca953x_chip *chip = gpiochip_get_data(gc); 531 532 switch (config) { 533 case PIN_CONFIG_BIAS_PULL_UP: 534 case PIN_CONFIG_BIAS_PULL_DOWN: 535 return pca953x_gpio_set_pull_up_down(chip, offset, config); 536 default: 537 return -ENOTSUPP; 538 } 539 } 540 541 static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) 542 { 543 struct gpio_chip *gc; 544 545 gc = &chip->gpio_chip; 546 547 gc->direction_input = pca953x_gpio_direction_input; 548 gc->direction_output = pca953x_gpio_direction_output; 549 gc->get = pca953x_gpio_get_value; 550 gc->set = pca953x_gpio_set_value; 551 gc->get_direction = pca953x_gpio_get_direction; 552 gc->set_multiple = pca953x_gpio_set_multiple; 553 gc->set_config = pca953x_gpio_set_config; 554 gc->can_sleep = true; 555 556 gc->base = chip->gpio_start; 557 gc->ngpio = gpios; 558 gc->label = dev_name(&chip->client->dev); 559 gc->parent = &chip->client->dev; 560 gc->owner = THIS_MODULE; 561 gc->names = chip->names; 562 } 563 564 #ifdef CONFIG_GPIO_PCA953X_IRQ 565 static void pca953x_irq_mask(struct irq_data *d) 566 { 567 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 568 struct pca953x_chip *chip = gpiochip_get_data(gc); 569 570 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); 571 } 572 573 static void pca953x_irq_unmask(struct irq_data *d) 574 { 575 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 576 struct pca953x_chip *chip = gpiochip_get_data(gc); 577 578 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); 579 } 580 581 static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) 582 { 583 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 584 struct pca953x_chip *chip = gpiochip_get_data(gc); 585 586 if (on) 587 atomic_inc(&chip->wakeup_path); 588 else 589 atomic_dec(&chip->wakeup_path); 590 591 return irq_set_irq_wake(chip->client->irq, on); 592 } 593 594 static void pca953x_irq_bus_lock(struct irq_data *d) 595 { 596 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 597 struct pca953x_chip *chip = gpiochip_get_data(gc); 598 599 mutex_lock(&chip->irq_lock); 600 } 601 602 static void pca953x_irq_bus_sync_unlock(struct irq_data *d) 603 { 604 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 605 struct pca953x_chip *chip = gpiochip_get_data(gc); 606 u8 new_irqs; 607 int level, i; 608 u8 invert_irq_mask[MAX_BANK]; 609 int reg_direction[MAX_BANK]; 610 611 regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction, 612 NBANK(chip)); 613 614 if (chip->driver_data & PCA_PCAL) { 615 /* Enable latch on interrupt-enabled inputs */ 616 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); 617 618 for (i = 0; i < NBANK(chip); i++) 619 invert_irq_mask[i] = ~chip->irq_mask[i]; 620 621 /* Unmask enabled interrupts */ 622 pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask); 623 } 624 625 /* Look for any newly setup interrupt */ 626 for (i = 0; i < NBANK(chip); i++) { 627 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; 628 new_irqs &= reg_direction[i]; 629 630 while (new_irqs) { 631 level = __ffs(new_irqs); 632 pca953x_gpio_direction_input(&chip->gpio_chip, 633 level + (BANK_SZ * i)); 634 new_irqs &= ~(1 << level); 635 } 636 } 637 638 mutex_unlock(&chip->irq_lock); 639 } 640 641 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) 642 { 643 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 644 struct pca953x_chip *chip = gpiochip_get_data(gc); 645 int bank_nb = d->hwirq / BANK_SZ; 646 u8 mask = 1 << (d->hwirq % BANK_SZ); 647 648 if (!(type & IRQ_TYPE_EDGE_BOTH)) { 649 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", 650 d->irq, type); 651 return -EINVAL; 652 } 653 654 if (type & IRQ_TYPE_EDGE_FALLING) 655 chip->irq_trig_fall[bank_nb] |= mask; 656 else 657 chip->irq_trig_fall[bank_nb] &= ~mask; 658 659 if (type & IRQ_TYPE_EDGE_RISING) 660 chip->irq_trig_raise[bank_nb] |= mask; 661 else 662 chip->irq_trig_raise[bank_nb] &= ~mask; 663 664 return 0; 665 } 666 667 static void pca953x_irq_shutdown(struct irq_data *d) 668 { 669 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 670 struct pca953x_chip *chip = gpiochip_get_data(gc); 671 u8 mask = 1 << (d->hwirq % BANK_SZ); 672 673 chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask; 674 chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask; 675 } 676 677 static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) 678 { 679 u8 cur_stat[MAX_BANK]; 680 u8 old_stat[MAX_BANK]; 681 bool pending_seen = false; 682 bool trigger_seen = false; 683 u8 trigger[MAX_BANK]; 684 int reg_direction[MAX_BANK]; 685 int ret, i; 686 687 if (chip->driver_data & PCA_PCAL) { 688 /* Read the current interrupt status from the device */ 689 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); 690 if (ret) 691 return false; 692 693 /* Check latched inputs and clear interrupt status */ 694 ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat); 695 if (ret) 696 return false; 697 698 for (i = 0; i < NBANK(chip); i++) { 699 /* Apply filter for rising/falling edge selection */ 700 pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) | 701 (cur_stat[i] & chip->irq_trig_raise[i]); 702 pending[i] &= trigger[i]; 703 if (pending[i]) 704 pending_seen = true; 705 } 706 707 return pending_seen; 708 } 709 710 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 711 if (ret) 712 return false; 713 714 /* Remove output pins from the equation */ 715 regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction, 716 NBANK(chip)); 717 for (i = 0; i < NBANK(chip); i++) 718 cur_stat[i] &= reg_direction[i]; 719 720 memcpy(old_stat, chip->irq_stat, NBANK(chip)); 721 722 for (i = 0; i < NBANK(chip); i++) { 723 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; 724 if (trigger[i]) 725 trigger_seen = true; 726 } 727 728 if (!trigger_seen) 729 return false; 730 731 memcpy(chip->irq_stat, cur_stat, NBANK(chip)); 732 733 for (i = 0; i < NBANK(chip); i++) { 734 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | 735 (cur_stat[i] & chip->irq_trig_raise[i]); 736 pending[i] &= trigger[i]; 737 if (pending[i]) 738 pending_seen = true; 739 } 740 741 return pending_seen; 742 } 743 744 static irqreturn_t pca953x_irq_handler(int irq, void *devid) 745 { 746 struct pca953x_chip *chip = devid; 747 u8 pending[MAX_BANK]; 748 u8 level; 749 unsigned nhandled = 0; 750 int i; 751 752 if (!pca953x_irq_pending(chip, pending)) 753 return IRQ_NONE; 754 755 for (i = 0; i < NBANK(chip); i++) { 756 while (pending[i]) { 757 level = __ffs(pending[i]); 758 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain, 759 level + (BANK_SZ * i))); 760 pending[i] &= ~(1 << level); 761 nhandled++; 762 } 763 } 764 765 return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; 766 } 767 768 static int pca953x_irq_setup(struct pca953x_chip *chip, 769 int irq_base) 770 { 771 struct i2c_client *client = chip->client; 772 struct irq_chip *irq_chip = &chip->irq_chip; 773 int reg_direction[MAX_BANK]; 774 int ret, i; 775 776 if (!client->irq) 777 return 0; 778 779 if (irq_base == -1) 780 return 0; 781 782 if (!(chip->driver_data & PCA_INT)) 783 return 0; 784 785 ret = pca953x_read_regs(chip, chip->regs->input, chip->irq_stat); 786 if (ret) 787 return ret; 788 789 /* 790 * There is no way to know which GPIO line generated the 791 * interrupt. We have to rely on the previous read for 792 * this purpose. 793 */ 794 regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction, 795 NBANK(chip)); 796 for (i = 0; i < NBANK(chip); i++) 797 chip->irq_stat[i] &= reg_direction[i]; 798 mutex_init(&chip->irq_lock); 799 800 ret = devm_request_threaded_irq(&client->dev, client->irq, 801 NULL, pca953x_irq_handler, 802 IRQF_TRIGGER_LOW | IRQF_ONESHOT | 803 IRQF_SHARED, 804 dev_name(&client->dev), chip); 805 if (ret) { 806 dev_err(&client->dev, "failed to request irq %d\n", 807 client->irq); 808 return ret; 809 } 810 811 irq_chip->name = dev_name(&chip->client->dev); 812 irq_chip->irq_mask = pca953x_irq_mask; 813 irq_chip->irq_unmask = pca953x_irq_unmask; 814 irq_chip->irq_set_wake = pca953x_irq_set_wake; 815 irq_chip->irq_bus_lock = pca953x_irq_bus_lock; 816 irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock; 817 irq_chip->irq_set_type = pca953x_irq_set_type; 818 irq_chip->irq_shutdown = pca953x_irq_shutdown; 819 820 ret = gpiochip_irqchip_add_nested(&chip->gpio_chip, irq_chip, 821 irq_base, handle_simple_irq, 822 IRQ_TYPE_NONE); 823 if (ret) { 824 dev_err(&client->dev, 825 "could not connect irqchip to gpiochip\n"); 826 return ret; 827 } 828 829 gpiochip_set_nested_irqchip(&chip->gpio_chip, irq_chip, client->irq); 830 831 return 0; 832 } 833 834 #else /* CONFIG_GPIO_PCA953X_IRQ */ 835 static int pca953x_irq_setup(struct pca953x_chip *chip, 836 int irq_base) 837 { 838 struct i2c_client *client = chip->client; 839 840 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) 841 dev_warn(&client->dev, "interrupt support not compiled in\n"); 842 843 return 0; 844 } 845 #endif 846 847 static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert) 848 { 849 int ret; 850 u8 val[MAX_BANK]; 851 852 ret = regcache_sync_region(chip->regmap, chip->regs->output, 853 chip->regs->output + NBANK(chip)); 854 if (ret != 0) 855 goto out; 856 857 ret = regcache_sync_region(chip->regmap, chip->regs->direction, 858 chip->regs->direction + NBANK(chip)); 859 if (ret != 0) 860 goto out; 861 862 /* set platform specific polarity inversion */ 863 if (invert) 864 memset(val, 0xFF, NBANK(chip)); 865 else 866 memset(val, 0, NBANK(chip)); 867 868 ret = pca953x_write_regs(chip, chip->regs->invert, val); 869 out: 870 return ret; 871 } 872 873 static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) 874 { 875 int ret; 876 u8 val[MAX_BANK]; 877 878 ret = device_pca95xx_init(chip, invert); 879 if (ret) 880 goto out; 881 882 /* To enable register 6, 7 to control pull up and pull down */ 883 memset(val, 0x02, NBANK(chip)); 884 ret = pca953x_write_regs(chip, PCA957X_BKEN, val); 885 if (ret) 886 goto out; 887 888 return 0; 889 out: 890 return ret; 891 } 892 893 static const struct of_device_id pca953x_dt_ids[]; 894 895 static int pca953x_probe(struct i2c_client *client, 896 const struct i2c_device_id *i2c_id) 897 { 898 struct pca953x_platform_data *pdata; 899 struct pca953x_chip *chip; 900 int irq_base = 0; 901 int ret; 902 u32 invert = 0; 903 struct regulator *reg; 904 905 chip = devm_kzalloc(&client->dev, 906 sizeof(struct pca953x_chip), GFP_KERNEL); 907 if (chip == NULL) 908 return -ENOMEM; 909 910 pdata = dev_get_platdata(&client->dev); 911 if (pdata) { 912 irq_base = pdata->irq_base; 913 chip->gpio_start = pdata->gpio_base; 914 invert = pdata->invert; 915 chip->names = pdata->names; 916 } else { 917 struct gpio_desc *reset_gpio; 918 919 chip->gpio_start = -1; 920 irq_base = 0; 921 922 /* 923 * See if we need to de-assert a reset pin. 924 * 925 * There is no known ACPI-enabled platforms that are 926 * using "reset" GPIO. Otherwise any of those platform 927 * must use _DSD method with corresponding property. 928 */ 929 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 930 GPIOD_OUT_LOW); 931 if (IS_ERR(reset_gpio)) 932 return PTR_ERR(reset_gpio); 933 } 934 935 chip->client = client; 936 937 reg = devm_regulator_get(&client->dev, "vcc"); 938 if (IS_ERR(reg)) { 939 ret = PTR_ERR(reg); 940 if (ret != -EPROBE_DEFER) 941 dev_err(&client->dev, "reg get err: %d\n", ret); 942 return ret; 943 } 944 ret = regulator_enable(reg); 945 if (ret) { 946 dev_err(&client->dev, "reg en err: %d\n", ret); 947 return ret; 948 } 949 chip->regulator = reg; 950 951 if (i2c_id) { 952 chip->driver_data = i2c_id->driver_data; 953 } else { 954 const struct acpi_device_id *acpi_id; 955 struct device *dev = &client->dev; 956 957 chip->driver_data = (uintptr_t)of_device_get_match_data(dev); 958 if (!chip->driver_data) { 959 acpi_id = acpi_match_device(pca953x_acpi_ids, dev); 960 if (!acpi_id) { 961 ret = -ENODEV; 962 goto err_exit; 963 } 964 965 chip->driver_data = acpi_id->driver_data; 966 } 967 } 968 969 i2c_set_clientdata(client, chip); 970 971 chip->regmap = devm_regmap_init_i2c(client, &pca953x_i2c_regmap); 972 if (IS_ERR(chip->regmap)) { 973 ret = PTR_ERR(chip->regmap); 974 goto err_exit; 975 } 976 977 regcache_mark_dirty(chip->regmap); 978 979 mutex_init(&chip->i2c_lock); 980 /* 981 * In case we have an i2c-mux controlled by a GPIO provided by an 982 * expander using the same driver higher on the device tree, read the 983 * i2c adapter nesting depth and use the retrieved value as lockdep 984 * subclass for chip->i2c_lock. 985 * 986 * REVISIT: This solution is not complete. It protects us from lockdep 987 * false positives when the expander controlling the i2c-mux is on 988 * a different level on the device tree, but not when it's on the same 989 * level on a different branch (in which case the subclass number 990 * would be the same). 991 * 992 * TODO: Once a correct solution is developed, a similar fix should be 993 * applied to all other i2c-controlled GPIO expanders (and potentially 994 * regmap-i2c). 995 */ 996 lockdep_set_subclass(&chip->i2c_lock, 997 i2c_adapter_depth(client->adapter)); 998 999 /* initialize cached registers from their original values. 1000 * we can't share this chip with another i2c master. 1001 */ 1002 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); 1003 1004 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { 1005 chip->regs = &pca953x_regs; 1006 ret = device_pca95xx_init(chip, invert); 1007 } else { 1008 chip->regs = &pca957x_regs; 1009 ret = device_pca957x_init(chip, invert); 1010 } 1011 if (ret) 1012 goto err_exit; 1013 1014 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); 1015 if (ret) 1016 goto err_exit; 1017 1018 ret = pca953x_irq_setup(chip, irq_base); 1019 if (ret) 1020 goto err_exit; 1021 1022 if (pdata && pdata->setup) { 1023 ret = pdata->setup(client, chip->gpio_chip.base, 1024 chip->gpio_chip.ngpio, pdata->context); 1025 if (ret < 0) 1026 dev_warn(&client->dev, "setup failed, %d\n", ret); 1027 } 1028 1029 return 0; 1030 1031 err_exit: 1032 regulator_disable(chip->regulator); 1033 return ret; 1034 } 1035 1036 static int pca953x_remove(struct i2c_client *client) 1037 { 1038 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); 1039 struct pca953x_chip *chip = i2c_get_clientdata(client); 1040 int ret; 1041 1042 if (pdata && pdata->teardown) { 1043 ret = pdata->teardown(client, chip->gpio_chip.base, 1044 chip->gpio_chip.ngpio, pdata->context); 1045 if (ret < 0) 1046 dev_err(&client->dev, "%s failed, %d\n", 1047 "teardown", ret); 1048 } else { 1049 ret = 0; 1050 } 1051 1052 regulator_disable(chip->regulator); 1053 1054 return ret; 1055 } 1056 1057 #ifdef CONFIG_PM_SLEEP 1058 static int pca953x_regcache_sync(struct device *dev) 1059 { 1060 struct pca953x_chip *chip = dev_get_drvdata(dev); 1061 int ret; 1062 1063 /* 1064 * The ordering between direction and output is important, 1065 * sync these registers first and only then sync the rest. 1066 */ 1067 ret = regcache_sync_region(chip->regmap, chip->regs->direction, 1068 chip->regs->direction + NBANK(chip)); 1069 if (ret != 0) { 1070 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); 1071 return ret; 1072 } 1073 1074 ret = regcache_sync_region(chip->regmap, chip->regs->output, 1075 chip->regs->output + NBANK(chip)); 1076 if (ret != 0) { 1077 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); 1078 return ret; 1079 } 1080 1081 #ifdef CONFIG_GPIO_PCA953X_IRQ 1082 if (chip->driver_data & PCA_PCAL) { 1083 ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH, 1084 PCAL953X_IN_LATCH + NBANK(chip)); 1085 if (ret != 0) { 1086 dev_err(dev, "Failed to sync INT latch registers: %d\n", 1087 ret); 1088 return ret; 1089 } 1090 1091 ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK, 1092 PCAL953X_INT_MASK + NBANK(chip)); 1093 if (ret != 0) { 1094 dev_err(dev, "Failed to sync INT mask registers: %d\n", 1095 ret); 1096 return ret; 1097 } 1098 } 1099 #endif 1100 1101 return 0; 1102 } 1103 1104 static int pca953x_suspend(struct device *dev) 1105 { 1106 struct pca953x_chip *chip = dev_get_drvdata(dev); 1107 1108 regcache_cache_only(chip->regmap, true); 1109 1110 if (atomic_read(&chip->wakeup_path)) 1111 device_set_wakeup_path(dev); 1112 else 1113 regulator_disable(chip->regulator); 1114 1115 return 0; 1116 } 1117 1118 static int pca953x_resume(struct device *dev) 1119 { 1120 struct pca953x_chip *chip = dev_get_drvdata(dev); 1121 int ret; 1122 1123 if (!atomic_read(&chip->wakeup_path)) { 1124 ret = regulator_enable(chip->regulator); 1125 if (ret != 0) { 1126 dev_err(dev, "Failed to enable regulator: %d\n", ret); 1127 return 0; 1128 } 1129 } 1130 1131 regcache_cache_only(chip->regmap, false); 1132 regcache_mark_dirty(chip->regmap); 1133 ret = pca953x_regcache_sync(dev); 1134 if (ret) 1135 return ret; 1136 1137 ret = regcache_sync(chip->regmap); 1138 if (ret != 0) { 1139 dev_err(dev, "Failed to restore register map: %d\n", ret); 1140 return ret; 1141 } 1142 1143 return 0; 1144 } 1145 #endif 1146 1147 /* convenience to stop overlong match-table lines */ 1148 #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) 1149 #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) 1150 1151 static const struct of_device_id pca953x_dt_ids[] = { 1152 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, 1153 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, 1154 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, 1155 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, 1156 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, 1157 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, 1158 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, 1159 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, 1160 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, 1161 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, 1162 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, 1163 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, 1164 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, 1165 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, 1166 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, 1167 1168 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1169 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, 1170 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, 1171 1172 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, 1173 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, 1174 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, 1175 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, 1176 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, 1177 1178 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, 1179 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, 1180 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, 1181 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, 1182 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, 1183 1184 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, 1185 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, 1186 1187 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, 1188 { } 1189 }; 1190 1191 MODULE_DEVICE_TABLE(of, pca953x_dt_ids); 1192 1193 static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); 1194 1195 static struct i2c_driver pca953x_driver = { 1196 .driver = { 1197 .name = "pca953x", 1198 .pm = &pca953x_pm_ops, 1199 .of_match_table = pca953x_dt_ids, 1200 .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), 1201 }, 1202 .probe = pca953x_probe, 1203 .remove = pca953x_remove, 1204 .id_table = pca953x_id, 1205 }; 1206 1207 static int __init pca953x_init(void) 1208 { 1209 return i2c_add_driver(&pca953x_driver); 1210 } 1211 /* register after i2c postcore initcall and before 1212 * subsys initcalls that may rely on these GPIOs 1213 */ 1214 subsys_initcall(pca953x_init); 1215 1216 static void __exit pca953x_exit(void) 1217 { 1218 i2c_del_driver(&pca953x_driver); 1219 } 1220 module_exit(pca953x_exit); 1221 1222 MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); 1223 MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); 1224 MODULE_LICENSE("GPL"); 1225