1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCA953x 4/8/16/24/40 bit I/O ports 4 * 5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> 6 * Copyright (C) 2007 Marvell International Ltd. 7 * 8 * Derived from drivers/i2c/chips/pca9539.c 9 */ 10 11 #include <linux/acpi.h> 12 #include <linux/bitmap.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/i2c.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/module.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_data/pca953x.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 25 #include <asm/unaligned.h> 26 27 #define PCA953X_INPUT 0x00 28 #define PCA953X_OUTPUT 0x01 29 #define PCA953X_INVERT 0x02 30 #define PCA953X_DIRECTION 0x03 31 32 #define REG_ADDR_MASK GENMASK(5, 0) 33 #define REG_ADDR_EXT BIT(6) 34 #define REG_ADDR_AI BIT(7) 35 36 #define PCA957X_IN 0x00 37 #define PCA957X_INVRT 0x01 38 #define PCA957X_BKEN 0x02 39 #define PCA957X_PUPD 0x03 40 #define PCA957X_CFG 0x04 41 #define PCA957X_OUT 0x05 42 #define PCA957X_MSK 0x06 43 #define PCA957X_INTS 0x07 44 45 #define PCAL953X_OUT_STRENGTH 0x20 46 #define PCAL953X_IN_LATCH 0x22 47 #define PCAL953X_PULL_EN 0x23 48 #define PCAL953X_PULL_SEL 0x24 49 #define PCAL953X_INT_MASK 0x25 50 #define PCAL953X_INT_STAT 0x26 51 #define PCAL953X_OUT_CONF 0x27 52 53 #define PCAL6524_INT_EDGE 0x28 54 #define PCAL6524_INT_CLR 0x2a 55 #define PCAL6524_IN_STATUS 0x2b 56 #define PCAL6524_OUT_INDCONF 0x2c 57 #define PCAL6524_DEBOUNCE 0x2d 58 59 #define PCA_GPIO_MASK GENMASK(7, 0) 60 61 #define PCAL_GPIO_MASK GENMASK(4, 0) 62 #define PCAL_PINCTRL_MASK GENMASK(6, 5) 63 64 #define PCA_INT BIT(8) 65 #define PCA_PCAL BIT(9) 66 #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) 67 #define PCA953X_TYPE BIT(12) 68 #define PCA957X_TYPE BIT(13) 69 #define PCA_TYPE_MASK GENMASK(15, 12) 70 71 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) 72 73 static const struct i2c_device_id pca953x_id[] = { 74 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, 75 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, 76 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, 77 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, 78 { "pca9536", 4 | PCA953X_TYPE, }, 79 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, 80 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, 81 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, 82 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, 83 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, 84 { "pca9556", 8 | PCA953X_TYPE, }, 85 { "pca9557", 8 | PCA953X_TYPE, }, 86 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, 87 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, 88 { "pca9698", 40 | PCA953X_TYPE, }, 89 90 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 91 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, 92 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 93 94 { "max7310", 8 | PCA953X_TYPE, }, 95 { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, 96 { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, 97 { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, 98 { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, 99 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, 100 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, 101 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, 102 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, 103 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, 104 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, 105 { "xra1202", 8 | PCA953X_TYPE }, 106 { } 107 }; 108 MODULE_DEVICE_TABLE(i2c, pca953x_id); 109 110 static const struct acpi_device_id pca953x_acpi_ids[] = { 111 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 112 { } 113 }; 114 MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); 115 116 #define MAX_BANK 5 117 #define BANK_SZ 8 118 #define MAX_LINE (MAX_BANK * BANK_SZ) 119 120 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) 121 122 struct pca953x_reg_config { 123 int direction; 124 int output; 125 int input; 126 int invert; 127 }; 128 129 static const struct pca953x_reg_config pca953x_regs = { 130 .direction = PCA953X_DIRECTION, 131 .output = PCA953X_OUTPUT, 132 .input = PCA953X_INPUT, 133 .invert = PCA953X_INVERT, 134 }; 135 136 static const struct pca953x_reg_config pca957x_regs = { 137 .direction = PCA957X_CFG, 138 .output = PCA957X_OUT, 139 .input = PCA957X_IN, 140 .invert = PCA957X_INVRT, 141 }; 142 143 struct pca953x_chip { 144 unsigned gpio_start; 145 struct mutex i2c_lock; 146 struct regmap *regmap; 147 148 #ifdef CONFIG_GPIO_PCA953X_IRQ 149 struct mutex irq_lock; 150 DECLARE_BITMAP(irq_mask, MAX_LINE); 151 DECLARE_BITMAP(irq_stat, MAX_LINE); 152 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 153 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 154 struct irq_chip irq_chip; 155 #endif 156 atomic_t wakeup_path; 157 158 struct i2c_client *client; 159 struct gpio_chip gpio_chip; 160 const char *const *names; 161 unsigned long driver_data; 162 struct regulator *regulator; 163 164 const struct pca953x_reg_config *regs; 165 }; 166 167 static int pca953x_bank_shift(struct pca953x_chip *chip) 168 { 169 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); 170 } 171 172 #define PCA953x_BANK_INPUT BIT(0) 173 #define PCA953x_BANK_OUTPUT BIT(1) 174 #define PCA953x_BANK_POLARITY BIT(2) 175 #define PCA953x_BANK_CONFIG BIT(3) 176 177 #define PCA957x_BANK_INPUT BIT(0) 178 #define PCA957x_BANK_POLARITY BIT(1) 179 #define PCA957x_BANK_BUSHOLD BIT(2) 180 #define PCA957x_BANK_CONFIG BIT(4) 181 #define PCA957x_BANK_OUTPUT BIT(5) 182 183 #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) 184 #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) 185 #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) 186 #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) 187 #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) 188 189 /* 190 * We care about the following registers: 191 * - Standard set, below 0x40, each port can be replicated up to 8 times 192 * - PCA953x standard 193 * Input port 0x00 + 0 * bank_size R 194 * Output port 0x00 + 1 * bank_size RW 195 * Polarity Inversion port 0x00 + 2 * bank_size RW 196 * Configuration port 0x00 + 3 * bank_size RW 197 * - PCA957x with mixed up registers 198 * Input port 0x00 + 0 * bank_size R 199 * Polarity Inversion port 0x00 + 1 * bank_size RW 200 * Bus hold port 0x00 + 2 * bank_size RW 201 * Configuration port 0x00 + 4 * bank_size RW 202 * Output port 0x00 + 5 * bank_size RW 203 * 204 * - Extended set, above 0x40, often chip specific. 205 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: 206 * Input latch register 0x40 + 2 * bank_size RW 207 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW 208 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW 209 * Interrupt mask register 0x40 + 5 * bank_size RW 210 * Interrupt status register 0x40 + 6 * bank_size R 211 * 212 * - Registers with bit 0x80 set, the AI bit 213 * The bit is cleared and the registers fall into one of the 214 * categories above. 215 */ 216 217 static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, 218 u32 checkbank) 219 { 220 int bank_shift = pca953x_bank_shift(chip); 221 int bank = (reg & REG_ADDR_MASK) >> bank_shift; 222 int offset = reg & (BIT(bank_shift) - 1); 223 224 /* Special PCAL extended register check. */ 225 if (reg & REG_ADDR_EXT) { 226 if (!(chip->driver_data & PCA_PCAL)) 227 return false; 228 bank += 8; 229 } 230 231 /* Register is not in the matching bank. */ 232 if (!(BIT(bank) & checkbank)) 233 return false; 234 235 /* Register is not within allowed range of bank. */ 236 if (offset >= NBANK(chip)) 237 return false; 238 239 return true; 240 } 241 242 static bool pca953x_readable_register(struct device *dev, unsigned int reg) 243 { 244 struct pca953x_chip *chip = dev_get_drvdata(dev); 245 u32 bank; 246 247 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { 248 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | 249 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; 250 } else { 251 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | 252 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | 253 PCA957x_BANK_BUSHOLD; 254 } 255 256 if (chip->driver_data & PCA_PCAL) { 257 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 258 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | 259 PCAL9xxx_BANK_IRQ_STAT; 260 } 261 262 return pca953x_check_register(chip, reg, bank); 263 } 264 265 static bool pca953x_writeable_register(struct device *dev, unsigned int reg) 266 { 267 struct pca953x_chip *chip = dev_get_drvdata(dev); 268 u32 bank; 269 270 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { 271 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | 272 PCA953x_BANK_CONFIG; 273 } else { 274 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | 275 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; 276 } 277 278 if (chip->driver_data & PCA_PCAL) 279 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 280 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; 281 282 return pca953x_check_register(chip, reg, bank); 283 } 284 285 static bool pca953x_volatile_register(struct device *dev, unsigned int reg) 286 { 287 struct pca953x_chip *chip = dev_get_drvdata(dev); 288 u32 bank; 289 290 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) 291 bank = PCA953x_BANK_INPUT; 292 else 293 bank = PCA957x_BANK_INPUT; 294 295 if (chip->driver_data & PCA_PCAL) 296 bank |= PCAL9xxx_BANK_IRQ_STAT; 297 298 return pca953x_check_register(chip, reg, bank); 299 } 300 301 static const struct regmap_config pca953x_i2c_regmap = { 302 .reg_bits = 8, 303 .val_bits = 8, 304 305 .readable_reg = pca953x_readable_register, 306 .writeable_reg = pca953x_writeable_register, 307 .volatile_reg = pca953x_volatile_register, 308 309 .cache_type = REGCACHE_RBTREE, 310 /* REVISIT: should be 0x7f but some 24 bit chips use REG_ADDR_AI */ 311 .max_register = 0xff, 312 }; 313 314 static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off, 315 bool write, bool addrinc) 316 { 317 int bank_shift = pca953x_bank_shift(chip); 318 int addr = (reg & PCAL_GPIO_MASK) << bank_shift; 319 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; 320 u8 regaddr = pinctrl | addr | (off / BANK_SZ); 321 322 /* Single byte read doesn't need AI bit set. */ 323 if (!addrinc) 324 return regaddr; 325 326 /* Chips with 24 and more GPIOs always support Auto Increment */ 327 if (write && NBANK(chip) > 2) 328 regaddr |= REG_ADDR_AI; 329 330 /* PCA9575 needs address-increment on multi-byte writes */ 331 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) 332 regaddr |= REG_ADDR_AI; 333 334 return regaddr; 335 } 336 337 static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 338 { 339 u8 regaddr = pca953x_recalc_addr(chip, reg, 0, true, true); 340 u8 value[MAX_BANK]; 341 int i, ret; 342 343 for (i = 0; i < NBANK(chip); i++) 344 value[i] = bitmap_get_value8(val, i * BANK_SZ); 345 346 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip)); 347 if (ret < 0) { 348 dev_err(&chip->client->dev, "failed writing register\n"); 349 return ret; 350 } 351 352 return 0; 353 } 354 355 static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 356 { 357 u8 regaddr = pca953x_recalc_addr(chip, reg, 0, false, true); 358 u8 value[MAX_BANK]; 359 int i, ret; 360 361 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip)); 362 if (ret < 0) { 363 dev_err(&chip->client->dev, "failed reading register\n"); 364 return ret; 365 } 366 367 for (i = 0; i < NBANK(chip); i++) 368 bitmap_set_value8(val, value[i], i * BANK_SZ); 369 370 return 0; 371 } 372 373 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) 374 { 375 struct pca953x_chip *chip = gpiochip_get_data(gc); 376 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, 377 true, false); 378 u8 bit = BIT(off % BANK_SZ); 379 int ret; 380 381 mutex_lock(&chip->i2c_lock); 382 ret = regmap_write_bits(chip->regmap, dirreg, bit, bit); 383 mutex_unlock(&chip->i2c_lock); 384 return ret; 385 } 386 387 static int pca953x_gpio_direction_output(struct gpio_chip *gc, 388 unsigned off, int val) 389 { 390 struct pca953x_chip *chip = gpiochip_get_data(gc); 391 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, 392 true, false); 393 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, 394 true, false); 395 u8 bit = BIT(off % BANK_SZ); 396 int ret; 397 398 mutex_lock(&chip->i2c_lock); 399 /* set output level */ 400 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 401 if (ret) 402 goto exit; 403 404 /* then direction */ 405 ret = regmap_write_bits(chip->regmap, dirreg, bit, 0); 406 exit: 407 mutex_unlock(&chip->i2c_lock); 408 return ret; 409 } 410 411 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) 412 { 413 struct pca953x_chip *chip = gpiochip_get_data(gc); 414 u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off, 415 true, false); 416 u8 bit = BIT(off % BANK_SZ); 417 u32 reg_val; 418 int ret; 419 420 mutex_lock(&chip->i2c_lock); 421 ret = regmap_read(chip->regmap, inreg, ®_val); 422 mutex_unlock(&chip->i2c_lock); 423 if (ret < 0) { 424 /* 425 * NOTE: 426 * diagnostic already emitted; that's all we should 427 * do unless gpio_*_value_cansleep() calls become different 428 * from their nonsleeping siblings (and report faults). 429 */ 430 return 0; 431 } 432 433 return !!(reg_val & bit); 434 } 435 436 static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) 437 { 438 struct pca953x_chip *chip = gpiochip_get_data(gc); 439 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, 440 true, false); 441 u8 bit = BIT(off % BANK_SZ); 442 443 mutex_lock(&chip->i2c_lock); 444 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 445 mutex_unlock(&chip->i2c_lock); 446 } 447 448 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) 449 { 450 struct pca953x_chip *chip = gpiochip_get_data(gc); 451 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, 452 true, false); 453 u8 bit = BIT(off % BANK_SZ); 454 u32 reg_val; 455 int ret; 456 457 mutex_lock(&chip->i2c_lock); 458 ret = regmap_read(chip->regmap, dirreg, ®_val); 459 mutex_unlock(&chip->i2c_lock); 460 if (ret < 0) 461 return ret; 462 463 if (reg_val & bit) 464 return GPIO_LINE_DIRECTION_IN; 465 466 return GPIO_LINE_DIRECTION_OUT; 467 } 468 469 static void pca953x_gpio_set_multiple(struct gpio_chip *gc, 470 unsigned long *mask, unsigned long *bits) 471 { 472 struct pca953x_chip *chip = gpiochip_get_data(gc); 473 DECLARE_BITMAP(reg_val, MAX_LINE); 474 int ret; 475 476 mutex_lock(&chip->i2c_lock); 477 ret = pca953x_read_regs(chip, chip->regs->output, reg_val); 478 if (ret) 479 goto exit; 480 481 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio); 482 483 pca953x_write_regs(chip, chip->regs->output, reg_val); 484 exit: 485 mutex_unlock(&chip->i2c_lock); 486 } 487 488 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, 489 unsigned int offset, 490 unsigned long config) 491 { 492 u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset, 493 true, false); 494 u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset, 495 true, false); 496 u8 bit = BIT(offset % BANK_SZ); 497 int ret; 498 499 /* 500 * pull-up/pull-down configuration requires PCAL extended 501 * registers 502 */ 503 if (!(chip->driver_data & PCA_PCAL)) 504 return -ENOTSUPP; 505 506 mutex_lock(&chip->i2c_lock); 507 508 /* Disable pull-up/pull-down */ 509 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0); 510 if (ret) 511 goto exit; 512 513 /* Configure pull-up/pull-down */ 514 if (config == PIN_CONFIG_BIAS_PULL_UP) 515 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit); 516 else if (config == PIN_CONFIG_BIAS_PULL_DOWN) 517 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0); 518 if (ret) 519 goto exit; 520 521 /* Enable pull-up/pull-down */ 522 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit); 523 524 exit: 525 mutex_unlock(&chip->i2c_lock); 526 return ret; 527 } 528 529 static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 530 unsigned long config) 531 { 532 struct pca953x_chip *chip = gpiochip_get_data(gc); 533 534 switch (config) { 535 case PIN_CONFIG_BIAS_PULL_UP: 536 case PIN_CONFIG_BIAS_PULL_DOWN: 537 return pca953x_gpio_set_pull_up_down(chip, offset, config); 538 default: 539 return -ENOTSUPP; 540 } 541 } 542 543 static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) 544 { 545 struct gpio_chip *gc; 546 547 gc = &chip->gpio_chip; 548 549 gc->direction_input = pca953x_gpio_direction_input; 550 gc->direction_output = pca953x_gpio_direction_output; 551 gc->get = pca953x_gpio_get_value; 552 gc->set = pca953x_gpio_set_value; 553 gc->get_direction = pca953x_gpio_get_direction; 554 gc->set_multiple = pca953x_gpio_set_multiple; 555 gc->set_config = pca953x_gpio_set_config; 556 gc->can_sleep = true; 557 558 gc->base = chip->gpio_start; 559 gc->ngpio = gpios; 560 gc->label = dev_name(&chip->client->dev); 561 gc->parent = &chip->client->dev; 562 gc->owner = THIS_MODULE; 563 gc->names = chip->names; 564 } 565 566 #ifdef CONFIG_GPIO_PCA953X_IRQ 567 static void pca953x_irq_mask(struct irq_data *d) 568 { 569 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 570 struct pca953x_chip *chip = gpiochip_get_data(gc); 571 572 chip->irq_mask[d->hwirq / BANK_SZ] &= ~BIT(d->hwirq % BANK_SZ); 573 } 574 575 static void pca953x_irq_unmask(struct irq_data *d) 576 { 577 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 578 struct pca953x_chip *chip = gpiochip_get_data(gc); 579 580 chip->irq_mask[d->hwirq / BANK_SZ] |= BIT(d->hwirq % BANK_SZ); 581 } 582 583 static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) 584 { 585 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 586 struct pca953x_chip *chip = gpiochip_get_data(gc); 587 588 if (on) 589 atomic_inc(&chip->wakeup_path); 590 else 591 atomic_dec(&chip->wakeup_path); 592 593 return irq_set_irq_wake(chip->client->irq, on); 594 } 595 596 static void pca953x_irq_bus_lock(struct irq_data *d) 597 { 598 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 599 struct pca953x_chip *chip = gpiochip_get_data(gc); 600 601 mutex_lock(&chip->irq_lock); 602 } 603 604 static void pca953x_irq_bus_sync_unlock(struct irq_data *d) 605 { 606 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 607 struct pca953x_chip *chip = gpiochip_get_data(gc); 608 DECLARE_BITMAP(irq_mask, MAX_LINE); 609 DECLARE_BITMAP(reg_direction, MAX_LINE); 610 int level; 611 612 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 613 614 if (chip->driver_data & PCA_PCAL) { 615 /* Enable latch on interrupt-enabled inputs */ 616 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); 617 618 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio); 619 620 /* Unmask enabled interrupts */ 621 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask); 622 } 623 624 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio); 625 bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio); 626 627 /* Look for any newly setup interrupt */ 628 for_each_set_bit(level, irq_mask, gc->ngpio) 629 pca953x_gpio_direction_input(&chip->gpio_chip, level); 630 631 mutex_unlock(&chip->irq_lock); 632 } 633 634 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) 635 { 636 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 637 struct pca953x_chip *chip = gpiochip_get_data(gc); 638 int bank_nb = d->hwirq / BANK_SZ; 639 u8 mask = BIT(d->hwirq % BANK_SZ); 640 641 if (!(type & IRQ_TYPE_EDGE_BOTH)) { 642 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", 643 d->irq, type); 644 return -EINVAL; 645 } 646 647 if (type & IRQ_TYPE_EDGE_FALLING) 648 chip->irq_trig_fall[bank_nb] |= mask; 649 else 650 chip->irq_trig_fall[bank_nb] &= ~mask; 651 652 if (type & IRQ_TYPE_EDGE_RISING) 653 chip->irq_trig_raise[bank_nb] |= mask; 654 else 655 chip->irq_trig_raise[bank_nb] &= ~mask; 656 657 return 0; 658 } 659 660 static void pca953x_irq_shutdown(struct irq_data *d) 661 { 662 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 663 struct pca953x_chip *chip = gpiochip_get_data(gc); 664 u8 mask = BIT(d->hwirq % BANK_SZ); 665 666 chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask; 667 chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask; 668 } 669 670 static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending) 671 { 672 struct gpio_chip *gc = &chip->gpio_chip; 673 DECLARE_BITMAP(reg_direction, MAX_LINE); 674 DECLARE_BITMAP(old_stat, MAX_LINE); 675 DECLARE_BITMAP(cur_stat, MAX_LINE); 676 DECLARE_BITMAP(new_stat, MAX_LINE); 677 DECLARE_BITMAP(trigger, MAX_LINE); 678 int ret; 679 680 if (chip->driver_data & PCA_PCAL) { 681 /* Read the current interrupt status from the device */ 682 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); 683 if (ret) 684 return false; 685 686 /* Check latched inputs and clear interrupt status */ 687 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 688 if (ret) 689 return false; 690 691 /* Apply filter for rising/falling edge selection */ 692 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio); 693 694 bitmap_and(pending, new_stat, trigger, gc->ngpio); 695 696 return !bitmap_empty(pending, gc->ngpio); 697 } 698 699 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 700 if (ret) 701 return false; 702 703 /* Remove output pins from the equation */ 704 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 705 706 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio); 707 708 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio); 709 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio); 710 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio); 711 712 if (bitmap_empty(trigger, gc->ngpio)) 713 return false; 714 715 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio); 716 717 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio); 718 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio); 719 bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio); 720 bitmap_and(pending, new_stat, trigger, gc->ngpio); 721 722 return !bitmap_empty(pending, gc->ngpio); 723 } 724 725 static irqreturn_t pca953x_irq_handler(int irq, void *devid) 726 { 727 struct pca953x_chip *chip = devid; 728 struct gpio_chip *gc = &chip->gpio_chip; 729 DECLARE_BITMAP(pending, MAX_LINE); 730 int level; 731 732 if (!pca953x_irq_pending(chip, pending)) 733 return IRQ_NONE; 734 735 for_each_set_bit(level, pending, gc->ngpio) 736 handle_nested_irq(irq_find_mapping(gc->irq.domain, level)); 737 738 return IRQ_HANDLED; 739 } 740 741 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 742 { 743 struct i2c_client *client = chip->client; 744 struct irq_chip *irq_chip = &chip->irq_chip; 745 DECLARE_BITMAP(reg_direction, MAX_LINE); 746 DECLARE_BITMAP(irq_stat, MAX_LINE); 747 int ret; 748 749 if (!client->irq) 750 return 0; 751 752 if (irq_base == -1) 753 return 0; 754 755 if (!(chip->driver_data & PCA_INT)) 756 return 0; 757 758 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat); 759 if (ret) 760 return ret; 761 762 /* 763 * There is no way to know which GPIO line generated the 764 * interrupt. We have to rely on the previous read for 765 * this purpose. 766 */ 767 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 768 bitmap_and(chip->irq_stat, irq_stat, reg_direction, chip->gpio_chip.ngpio); 769 mutex_init(&chip->irq_lock); 770 771 ret = devm_request_threaded_irq(&client->dev, client->irq, 772 NULL, pca953x_irq_handler, 773 IRQF_TRIGGER_LOW | IRQF_ONESHOT | 774 IRQF_SHARED, 775 dev_name(&client->dev), chip); 776 if (ret) { 777 dev_err(&client->dev, "failed to request irq %d\n", 778 client->irq); 779 return ret; 780 } 781 782 irq_chip->name = dev_name(&chip->client->dev); 783 irq_chip->irq_mask = pca953x_irq_mask; 784 irq_chip->irq_unmask = pca953x_irq_unmask; 785 irq_chip->irq_set_wake = pca953x_irq_set_wake; 786 irq_chip->irq_bus_lock = pca953x_irq_bus_lock; 787 irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock; 788 irq_chip->irq_set_type = pca953x_irq_set_type; 789 irq_chip->irq_shutdown = pca953x_irq_shutdown; 790 791 ret = gpiochip_irqchip_add_nested(&chip->gpio_chip, irq_chip, 792 irq_base, handle_simple_irq, 793 IRQ_TYPE_NONE); 794 if (ret) { 795 dev_err(&client->dev, 796 "could not connect irqchip to gpiochip\n"); 797 return ret; 798 } 799 800 gpiochip_set_nested_irqchip(&chip->gpio_chip, irq_chip, client->irq); 801 802 return 0; 803 } 804 805 #else /* CONFIG_GPIO_PCA953X_IRQ */ 806 static int pca953x_irq_setup(struct pca953x_chip *chip, 807 int irq_base) 808 { 809 struct i2c_client *client = chip->client; 810 811 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) 812 dev_warn(&client->dev, "interrupt support not compiled in\n"); 813 814 return 0; 815 } 816 #endif 817 818 static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert) 819 { 820 DECLARE_BITMAP(val, MAX_LINE); 821 int ret; 822 823 ret = regcache_sync_region(chip->regmap, chip->regs->output, 824 chip->regs->output + NBANK(chip)); 825 if (ret) 826 goto out; 827 828 ret = regcache_sync_region(chip->regmap, chip->regs->direction, 829 chip->regs->direction + NBANK(chip)); 830 if (ret) 831 goto out; 832 833 /* set platform specific polarity inversion */ 834 if (invert) 835 bitmap_fill(val, MAX_LINE); 836 else 837 bitmap_zero(val, MAX_LINE); 838 839 ret = pca953x_write_regs(chip, chip->regs->invert, val); 840 out: 841 return ret; 842 } 843 844 static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) 845 { 846 DECLARE_BITMAP(val, MAX_LINE); 847 int ret; 848 849 ret = device_pca95xx_init(chip, invert); 850 if (ret) 851 goto out; 852 853 /* To enable register 6, 7 to control pull up and pull down */ 854 memset(val, 0x02, NBANK(chip)); 855 ret = pca953x_write_regs(chip, PCA957X_BKEN, val); 856 if (ret) 857 goto out; 858 859 return 0; 860 out: 861 return ret; 862 } 863 864 static const struct of_device_id pca953x_dt_ids[]; 865 866 static int pca953x_probe(struct i2c_client *client, 867 const struct i2c_device_id *i2c_id) 868 { 869 struct pca953x_platform_data *pdata; 870 struct pca953x_chip *chip; 871 int irq_base = 0; 872 int ret; 873 u32 invert = 0; 874 struct regulator *reg; 875 876 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); 877 if (chip == NULL) 878 return -ENOMEM; 879 880 pdata = dev_get_platdata(&client->dev); 881 if (pdata) { 882 irq_base = pdata->irq_base; 883 chip->gpio_start = pdata->gpio_base; 884 invert = pdata->invert; 885 chip->names = pdata->names; 886 } else { 887 struct gpio_desc *reset_gpio; 888 889 chip->gpio_start = -1; 890 irq_base = 0; 891 892 /* 893 * See if we need to de-assert a reset pin. 894 * 895 * There is no known ACPI-enabled platforms that are 896 * using "reset" GPIO. Otherwise any of those platform 897 * must use _DSD method with corresponding property. 898 */ 899 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 900 GPIOD_OUT_LOW); 901 if (IS_ERR(reset_gpio)) 902 return PTR_ERR(reset_gpio); 903 } 904 905 chip->client = client; 906 907 reg = devm_regulator_get(&client->dev, "vcc"); 908 if (IS_ERR(reg)) { 909 ret = PTR_ERR(reg); 910 if (ret != -EPROBE_DEFER) 911 dev_err(&client->dev, "reg get err: %d\n", ret); 912 return ret; 913 } 914 ret = regulator_enable(reg); 915 if (ret) { 916 dev_err(&client->dev, "reg en err: %d\n", ret); 917 return ret; 918 } 919 chip->regulator = reg; 920 921 if (i2c_id) { 922 chip->driver_data = i2c_id->driver_data; 923 } else { 924 const void *match; 925 926 match = device_get_match_data(&client->dev); 927 if (!match) { 928 ret = -ENODEV; 929 goto err_exit; 930 } 931 932 chip->driver_data = (uintptr_t)match; 933 } 934 935 i2c_set_clientdata(client, chip); 936 937 chip->regmap = devm_regmap_init_i2c(client, &pca953x_i2c_regmap); 938 if (IS_ERR(chip->regmap)) { 939 ret = PTR_ERR(chip->regmap); 940 goto err_exit; 941 } 942 943 regcache_mark_dirty(chip->regmap); 944 945 mutex_init(&chip->i2c_lock); 946 /* 947 * In case we have an i2c-mux controlled by a GPIO provided by an 948 * expander using the same driver higher on the device tree, read the 949 * i2c adapter nesting depth and use the retrieved value as lockdep 950 * subclass for chip->i2c_lock. 951 * 952 * REVISIT: This solution is not complete. It protects us from lockdep 953 * false positives when the expander controlling the i2c-mux is on 954 * a different level on the device tree, but not when it's on the same 955 * level on a different branch (in which case the subclass number 956 * would be the same). 957 * 958 * TODO: Once a correct solution is developed, a similar fix should be 959 * applied to all other i2c-controlled GPIO expanders (and potentially 960 * regmap-i2c). 961 */ 962 lockdep_set_subclass(&chip->i2c_lock, 963 i2c_adapter_depth(client->adapter)); 964 965 /* initialize cached registers from their original values. 966 * we can't share this chip with another i2c master. 967 */ 968 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); 969 970 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { 971 chip->regs = &pca953x_regs; 972 ret = device_pca95xx_init(chip, invert); 973 } else { 974 chip->regs = &pca957x_regs; 975 ret = device_pca957x_init(chip, invert); 976 } 977 if (ret) 978 goto err_exit; 979 980 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); 981 if (ret) 982 goto err_exit; 983 984 ret = pca953x_irq_setup(chip, irq_base); 985 if (ret) 986 goto err_exit; 987 988 if (pdata && pdata->setup) { 989 ret = pdata->setup(client, chip->gpio_chip.base, 990 chip->gpio_chip.ngpio, pdata->context); 991 if (ret < 0) 992 dev_warn(&client->dev, "setup failed, %d\n", ret); 993 } 994 995 return 0; 996 997 err_exit: 998 regulator_disable(chip->regulator); 999 return ret; 1000 } 1001 1002 static int pca953x_remove(struct i2c_client *client) 1003 { 1004 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); 1005 struct pca953x_chip *chip = i2c_get_clientdata(client); 1006 int ret; 1007 1008 if (pdata && pdata->teardown) { 1009 ret = pdata->teardown(client, chip->gpio_chip.base, 1010 chip->gpio_chip.ngpio, pdata->context); 1011 if (ret < 0) 1012 dev_err(&client->dev, "teardown failed, %d\n", ret); 1013 } else { 1014 ret = 0; 1015 } 1016 1017 regulator_disable(chip->regulator); 1018 1019 return ret; 1020 } 1021 1022 #ifdef CONFIG_PM_SLEEP 1023 static int pca953x_regcache_sync(struct device *dev) 1024 { 1025 struct pca953x_chip *chip = dev_get_drvdata(dev); 1026 int ret; 1027 1028 /* 1029 * The ordering between direction and output is important, 1030 * sync these registers first and only then sync the rest. 1031 */ 1032 ret = regcache_sync_region(chip->regmap, chip->regs->direction, 1033 chip->regs->direction + NBANK(chip)); 1034 if (ret) { 1035 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); 1036 return ret; 1037 } 1038 1039 ret = regcache_sync_region(chip->regmap, chip->regs->output, 1040 chip->regs->output + NBANK(chip)); 1041 if (ret) { 1042 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); 1043 return ret; 1044 } 1045 1046 #ifdef CONFIG_GPIO_PCA953X_IRQ 1047 if (chip->driver_data & PCA_PCAL) { 1048 ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH, 1049 PCAL953X_IN_LATCH + NBANK(chip)); 1050 if (ret) { 1051 dev_err(dev, "Failed to sync INT latch registers: %d\n", 1052 ret); 1053 return ret; 1054 } 1055 1056 ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK, 1057 PCAL953X_INT_MASK + NBANK(chip)); 1058 if (ret) { 1059 dev_err(dev, "Failed to sync INT mask registers: %d\n", 1060 ret); 1061 return ret; 1062 } 1063 } 1064 #endif 1065 1066 return 0; 1067 } 1068 1069 static int pca953x_suspend(struct device *dev) 1070 { 1071 struct pca953x_chip *chip = dev_get_drvdata(dev); 1072 1073 regcache_cache_only(chip->regmap, true); 1074 1075 if (atomic_read(&chip->wakeup_path)) 1076 device_set_wakeup_path(dev); 1077 else 1078 regulator_disable(chip->regulator); 1079 1080 return 0; 1081 } 1082 1083 static int pca953x_resume(struct device *dev) 1084 { 1085 struct pca953x_chip *chip = dev_get_drvdata(dev); 1086 int ret; 1087 1088 if (!atomic_read(&chip->wakeup_path)) { 1089 ret = regulator_enable(chip->regulator); 1090 if (ret) { 1091 dev_err(dev, "Failed to enable regulator: %d\n", ret); 1092 return 0; 1093 } 1094 } 1095 1096 regcache_cache_only(chip->regmap, false); 1097 regcache_mark_dirty(chip->regmap); 1098 ret = pca953x_regcache_sync(dev); 1099 if (ret) 1100 return ret; 1101 1102 ret = regcache_sync(chip->regmap); 1103 if (ret) { 1104 dev_err(dev, "Failed to restore register map: %d\n", ret); 1105 return ret; 1106 } 1107 1108 return 0; 1109 } 1110 #endif 1111 1112 /* convenience to stop overlong match-table lines */ 1113 #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) 1114 #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) 1115 1116 static const struct of_device_id pca953x_dt_ids[] = { 1117 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, 1118 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, 1119 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, 1120 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, 1121 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, 1122 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, 1123 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, 1124 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, 1125 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, 1126 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, 1127 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, 1128 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, 1129 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, 1130 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, 1131 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, 1132 1133 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1134 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, 1135 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, 1136 1137 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, 1138 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, 1139 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, 1140 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, 1141 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, 1142 1143 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, 1144 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, 1145 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, 1146 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, 1147 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, 1148 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, 1149 1150 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, 1151 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, 1152 1153 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, 1154 { } 1155 }; 1156 1157 MODULE_DEVICE_TABLE(of, pca953x_dt_ids); 1158 1159 static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); 1160 1161 static struct i2c_driver pca953x_driver = { 1162 .driver = { 1163 .name = "pca953x", 1164 .pm = &pca953x_pm_ops, 1165 .of_match_table = pca953x_dt_ids, 1166 .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), 1167 }, 1168 .probe = pca953x_probe, 1169 .remove = pca953x_remove, 1170 .id_table = pca953x_id, 1171 }; 1172 1173 static int __init pca953x_init(void) 1174 { 1175 return i2c_add_driver(&pca953x_driver); 1176 } 1177 /* register after i2c postcore initcall and before 1178 * subsys initcalls that may rely on these GPIOs 1179 */ 1180 subsys_initcall(pca953x_init); 1181 1182 static void __exit pca953x_exit(void) 1183 { 1184 i2c_del_driver(&pca953x_driver); 1185 } 1186 module_exit(pca953x_exit); 1187 1188 MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); 1189 MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); 1190 MODULE_LICENSE("GPL"); 1191