1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCA953x 4/8/16/24/40 bit I/O ports 4 * 5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> 6 * Copyright (C) 2007 Marvell International Ltd. 7 * 8 * Derived from drivers/i2c/chips/pca9539.c 9 */ 10 11 #include <linux/acpi.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/module.h> 18 #include <linux/of_platform.h> 19 #include <linux/platform_data/pca953x.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 24 #include <asm/unaligned.h> 25 26 #define PCA953X_INPUT 0x00 27 #define PCA953X_OUTPUT 0x01 28 #define PCA953X_INVERT 0x02 29 #define PCA953X_DIRECTION 0x03 30 31 #define REG_ADDR_MASK 0x3f 32 #define REG_ADDR_EXT 0x40 33 #define REG_ADDR_AI 0x80 34 35 #define PCA957X_IN 0x00 36 #define PCA957X_INVRT 0x01 37 #define PCA957X_BKEN 0x02 38 #define PCA957X_PUPD 0x03 39 #define PCA957X_CFG 0x04 40 #define PCA957X_OUT 0x05 41 #define PCA957X_MSK 0x06 42 #define PCA957X_INTS 0x07 43 44 #define PCAL953X_OUT_STRENGTH 0x20 45 #define PCAL953X_IN_LATCH 0x22 46 #define PCAL953X_PULL_EN 0x23 47 #define PCAL953X_PULL_SEL 0x24 48 #define PCAL953X_INT_MASK 0x25 49 #define PCAL953X_INT_STAT 0x26 50 #define PCAL953X_OUT_CONF 0x27 51 52 #define PCAL6524_INT_EDGE 0x28 53 #define PCAL6524_INT_CLR 0x2a 54 #define PCAL6524_IN_STATUS 0x2b 55 #define PCAL6524_OUT_INDCONF 0x2c 56 #define PCAL6524_DEBOUNCE 0x2d 57 58 #define PCA_GPIO_MASK 0x00FF 59 60 #define PCAL_GPIO_MASK 0x1f 61 #define PCAL_PINCTRL_MASK 0x60 62 63 #define PCA_INT 0x0100 64 #define PCA_PCAL 0x0200 65 #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) 66 #define PCA953X_TYPE 0x1000 67 #define PCA957X_TYPE 0x2000 68 #define PCA_TYPE_MASK 0xF000 69 70 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) 71 72 static const struct i2c_device_id pca953x_id[] = { 73 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, 74 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, 75 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, 76 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, 77 { "pca9536", 4 | PCA953X_TYPE, }, 78 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, 79 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, 80 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, 81 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, 82 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, 83 { "pca9556", 8 | PCA953X_TYPE, }, 84 { "pca9557", 8 | PCA953X_TYPE, }, 85 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, 86 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, 87 { "pca9698", 40 | PCA953X_TYPE, }, 88 89 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 90 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, 91 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 92 93 { "max7310", 8 | PCA953X_TYPE, }, 94 { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, 95 { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, 96 { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, 97 { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, 98 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, 99 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, 100 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, 101 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, 102 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, 103 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, 104 { "xra1202", 8 | PCA953X_TYPE }, 105 { } 106 }; 107 MODULE_DEVICE_TABLE(i2c, pca953x_id); 108 109 static const struct acpi_device_id pca953x_acpi_ids[] = { 110 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 111 { } 112 }; 113 MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); 114 115 #define MAX_BANK 5 116 #define BANK_SZ 8 117 118 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) 119 120 struct pca953x_reg_config { 121 int direction; 122 int output; 123 int input; 124 int invert; 125 }; 126 127 static const struct pca953x_reg_config pca953x_regs = { 128 .direction = PCA953X_DIRECTION, 129 .output = PCA953X_OUTPUT, 130 .input = PCA953X_INPUT, 131 .invert = PCA953X_INVERT, 132 }; 133 134 static const struct pca953x_reg_config pca957x_regs = { 135 .direction = PCA957X_CFG, 136 .output = PCA957X_OUT, 137 .input = PCA957X_IN, 138 .invert = PCA957X_INVRT, 139 }; 140 141 struct pca953x_chip { 142 unsigned gpio_start; 143 struct mutex i2c_lock; 144 struct regmap *regmap; 145 146 #ifdef CONFIG_GPIO_PCA953X_IRQ 147 struct mutex irq_lock; 148 u8 irq_mask[MAX_BANK]; 149 u8 irq_stat[MAX_BANK]; 150 u8 irq_trig_raise[MAX_BANK]; 151 u8 irq_trig_fall[MAX_BANK]; 152 struct irq_chip irq_chip; 153 #endif 154 atomic_t wakeup_path; 155 156 struct i2c_client *client; 157 struct gpio_chip gpio_chip; 158 const char *const *names; 159 unsigned long driver_data; 160 struct regulator *regulator; 161 162 const struct pca953x_reg_config *regs; 163 }; 164 165 static int pca953x_bank_shift(struct pca953x_chip *chip) 166 { 167 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); 168 } 169 170 #define PCA953x_BANK_INPUT BIT(0) 171 #define PCA953x_BANK_OUTPUT BIT(1) 172 #define PCA953x_BANK_POLARITY BIT(2) 173 #define PCA953x_BANK_CONFIG BIT(3) 174 175 #define PCA957x_BANK_INPUT BIT(0) 176 #define PCA957x_BANK_POLARITY BIT(1) 177 #define PCA957x_BANK_BUSHOLD BIT(2) 178 #define PCA957x_BANK_CONFIG BIT(4) 179 #define PCA957x_BANK_OUTPUT BIT(5) 180 181 #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) 182 #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) 183 #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) 184 #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) 185 #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) 186 187 /* 188 * We care about the following registers: 189 * - Standard set, below 0x40, each port can be replicated up to 8 times 190 * - PCA953x standard 191 * Input port 0x00 + 0 * bank_size R 192 * Output port 0x00 + 1 * bank_size RW 193 * Polarity Inversion port 0x00 + 2 * bank_size RW 194 * Configuration port 0x00 + 3 * bank_size RW 195 * - PCA957x with mixed up registers 196 * Input port 0x00 + 0 * bank_size R 197 * Polarity Inversion port 0x00 + 1 * bank_size RW 198 * Bus hold port 0x00 + 2 * bank_size RW 199 * Configuration port 0x00 + 4 * bank_size RW 200 * Output port 0x00 + 5 * bank_size RW 201 * 202 * - Extended set, above 0x40, often chip specific. 203 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: 204 * Input latch register 0x40 + 2 * bank_size RW 205 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW 206 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW 207 * Interrupt mask register 0x40 + 5 * bank_size RW 208 * Interrupt status register 0x40 + 6 * bank_size R 209 * 210 * - Registers with bit 0x80 set, the AI bit 211 * The bit is cleared and the registers fall into one of the 212 * categories above. 213 */ 214 215 static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, 216 u32 checkbank) 217 { 218 int bank_shift = pca953x_bank_shift(chip); 219 int bank = (reg & REG_ADDR_MASK) >> bank_shift; 220 int offset = reg & (BIT(bank_shift) - 1); 221 222 /* Special PCAL extended register check. */ 223 if (reg & REG_ADDR_EXT) { 224 if (!(chip->driver_data & PCA_PCAL)) 225 return false; 226 bank += 8; 227 } 228 229 /* Register is not in the matching bank. */ 230 if (!(BIT(bank) & checkbank)) 231 return false; 232 233 /* Register is not within allowed range of bank. */ 234 if (offset >= NBANK(chip)) 235 return false; 236 237 return true; 238 } 239 240 static bool pca953x_readable_register(struct device *dev, unsigned int reg) 241 { 242 struct pca953x_chip *chip = dev_get_drvdata(dev); 243 u32 bank; 244 245 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { 246 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | 247 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; 248 } else { 249 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | 250 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | 251 PCA957x_BANK_BUSHOLD; 252 } 253 254 if (chip->driver_data & PCA_PCAL) { 255 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 256 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | 257 PCAL9xxx_BANK_IRQ_STAT; 258 } 259 260 return pca953x_check_register(chip, reg, bank); 261 } 262 263 static bool pca953x_writeable_register(struct device *dev, unsigned int reg) 264 { 265 struct pca953x_chip *chip = dev_get_drvdata(dev); 266 u32 bank; 267 268 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { 269 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | 270 PCA953x_BANK_CONFIG; 271 } else { 272 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | 273 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; 274 } 275 276 if (chip->driver_data & PCA_PCAL) 277 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 278 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; 279 280 return pca953x_check_register(chip, reg, bank); 281 } 282 283 static bool pca953x_volatile_register(struct device *dev, unsigned int reg) 284 { 285 struct pca953x_chip *chip = dev_get_drvdata(dev); 286 u32 bank; 287 288 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) 289 bank = PCA953x_BANK_INPUT; 290 else 291 bank = PCA957x_BANK_INPUT; 292 293 if (chip->driver_data & PCA_PCAL) 294 bank |= PCAL9xxx_BANK_IRQ_STAT; 295 296 return pca953x_check_register(chip, reg, bank); 297 } 298 299 static const struct regmap_config pca953x_i2c_regmap = { 300 .reg_bits = 8, 301 .val_bits = 8, 302 303 .readable_reg = pca953x_readable_register, 304 .writeable_reg = pca953x_writeable_register, 305 .volatile_reg = pca953x_volatile_register, 306 307 .cache_type = REGCACHE_RBTREE, 308 .max_register = 0x7f, 309 }; 310 311 static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off, 312 bool write, bool addrinc) 313 { 314 int bank_shift = pca953x_bank_shift(chip); 315 int addr = (reg & PCAL_GPIO_MASK) << bank_shift; 316 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; 317 u8 regaddr = pinctrl | addr | (off / BANK_SZ); 318 319 /* Single byte read doesn't need AI bit set. */ 320 if (!addrinc) 321 return regaddr; 322 323 /* Chips with 24 and more GPIOs always support Auto Increment */ 324 if (write && NBANK(chip) > 2) 325 regaddr |= REG_ADDR_AI; 326 327 /* PCA9575 needs address-increment on multi-byte writes */ 328 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) 329 regaddr |= REG_ADDR_AI; 330 331 return regaddr; 332 } 333 334 static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) 335 { 336 u8 regaddr = pca953x_recalc_addr(chip, reg, 0, true, true); 337 int ret; 338 339 ret = regmap_bulk_write(chip->regmap, regaddr, val, NBANK(chip)); 340 if (ret < 0) { 341 dev_err(&chip->client->dev, "failed writing register\n"); 342 return ret; 343 } 344 345 return 0; 346 } 347 348 static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) 349 { 350 u8 regaddr = pca953x_recalc_addr(chip, reg, 0, false, true); 351 int ret; 352 353 ret = regmap_bulk_read(chip->regmap, regaddr, val, NBANK(chip)); 354 if (ret < 0) { 355 dev_err(&chip->client->dev, "failed reading register\n"); 356 return ret; 357 } 358 359 return 0; 360 } 361 362 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) 363 { 364 struct pca953x_chip *chip = gpiochip_get_data(gc); 365 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, 366 true, false); 367 u8 bit = BIT(off % BANK_SZ); 368 int ret; 369 370 mutex_lock(&chip->i2c_lock); 371 ret = regmap_write_bits(chip->regmap, dirreg, bit, bit); 372 mutex_unlock(&chip->i2c_lock); 373 return ret; 374 } 375 376 static int pca953x_gpio_direction_output(struct gpio_chip *gc, 377 unsigned off, int val) 378 { 379 struct pca953x_chip *chip = gpiochip_get_data(gc); 380 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, 381 true, false); 382 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, 383 true, false); 384 u8 bit = BIT(off % BANK_SZ); 385 int ret; 386 387 mutex_lock(&chip->i2c_lock); 388 /* set output level */ 389 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 390 if (ret) 391 goto exit; 392 393 /* then direction */ 394 ret = regmap_write_bits(chip->regmap, dirreg, bit, 0); 395 exit: 396 mutex_unlock(&chip->i2c_lock); 397 return ret; 398 } 399 400 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) 401 { 402 struct pca953x_chip *chip = gpiochip_get_data(gc); 403 u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off, 404 true, false); 405 u8 bit = BIT(off % BANK_SZ); 406 u32 reg_val; 407 int ret; 408 409 mutex_lock(&chip->i2c_lock); 410 ret = regmap_read(chip->regmap, inreg, ®_val); 411 mutex_unlock(&chip->i2c_lock); 412 if (ret < 0) { 413 /* NOTE: diagnostic already emitted; that's all we should 414 * do unless gpio_*_value_cansleep() calls become different 415 * from their nonsleeping siblings (and report faults). 416 */ 417 return 0; 418 } 419 420 return !!(reg_val & bit); 421 } 422 423 static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) 424 { 425 struct pca953x_chip *chip = gpiochip_get_data(gc); 426 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, 427 true, false); 428 u8 bit = BIT(off % BANK_SZ); 429 430 mutex_lock(&chip->i2c_lock); 431 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 432 mutex_unlock(&chip->i2c_lock); 433 } 434 435 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) 436 { 437 struct pca953x_chip *chip = gpiochip_get_data(gc); 438 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, 439 true, false); 440 u8 bit = BIT(off % BANK_SZ); 441 u32 reg_val; 442 int ret; 443 444 mutex_lock(&chip->i2c_lock); 445 ret = regmap_read(chip->regmap, dirreg, ®_val); 446 mutex_unlock(&chip->i2c_lock); 447 if (ret < 0) 448 return ret; 449 450 return !!(reg_val & bit); 451 } 452 453 static void pca953x_gpio_set_multiple(struct gpio_chip *gc, 454 unsigned long *mask, unsigned long *bits) 455 { 456 struct pca953x_chip *chip = gpiochip_get_data(gc); 457 unsigned int bank_mask, bank_val; 458 int bank; 459 u8 reg_val[MAX_BANK]; 460 int ret; 461 462 mutex_lock(&chip->i2c_lock); 463 ret = pca953x_read_regs(chip, chip->regs->output, reg_val); 464 if (ret) 465 goto exit; 466 467 for (bank = 0; bank < NBANK(chip); bank++) { 468 bank_mask = mask[bank / sizeof(*mask)] >> 469 ((bank % sizeof(*mask)) * 8); 470 if (bank_mask) { 471 bank_val = bits[bank / sizeof(*bits)] >> 472 ((bank % sizeof(*bits)) * 8); 473 bank_val &= bank_mask; 474 reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val; 475 } 476 } 477 478 pca953x_write_regs(chip, chip->regs->output, reg_val); 479 exit: 480 mutex_unlock(&chip->i2c_lock); 481 } 482 483 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, 484 unsigned int offset, 485 unsigned long config) 486 { 487 u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset, 488 true, false); 489 u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset, 490 true, false); 491 u8 bit = BIT(offset % BANK_SZ); 492 int ret; 493 494 /* 495 * pull-up/pull-down configuration requires PCAL extended 496 * registers 497 */ 498 if (!(chip->driver_data & PCA_PCAL)) 499 return -ENOTSUPP; 500 501 mutex_lock(&chip->i2c_lock); 502 503 /* Disable pull-up/pull-down */ 504 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0); 505 if (ret) 506 goto exit; 507 508 /* Configure pull-up/pull-down */ 509 if (config == PIN_CONFIG_BIAS_PULL_UP) 510 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit); 511 else if (config == PIN_CONFIG_BIAS_PULL_DOWN) 512 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0); 513 if (ret) 514 goto exit; 515 516 /* Enable pull-up/pull-down */ 517 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit); 518 519 exit: 520 mutex_unlock(&chip->i2c_lock); 521 return ret; 522 } 523 524 static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 525 unsigned long config) 526 { 527 struct pca953x_chip *chip = gpiochip_get_data(gc); 528 529 switch (config) { 530 case PIN_CONFIG_BIAS_PULL_UP: 531 case PIN_CONFIG_BIAS_PULL_DOWN: 532 return pca953x_gpio_set_pull_up_down(chip, offset, config); 533 default: 534 return -ENOTSUPP; 535 } 536 } 537 538 static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) 539 { 540 struct gpio_chip *gc; 541 542 gc = &chip->gpio_chip; 543 544 gc->direction_input = pca953x_gpio_direction_input; 545 gc->direction_output = pca953x_gpio_direction_output; 546 gc->get = pca953x_gpio_get_value; 547 gc->set = pca953x_gpio_set_value; 548 gc->get_direction = pca953x_gpio_get_direction; 549 gc->set_multiple = pca953x_gpio_set_multiple; 550 gc->set_config = pca953x_gpio_set_config; 551 gc->can_sleep = true; 552 553 gc->base = chip->gpio_start; 554 gc->ngpio = gpios; 555 gc->label = dev_name(&chip->client->dev); 556 gc->parent = &chip->client->dev; 557 gc->owner = THIS_MODULE; 558 gc->names = chip->names; 559 } 560 561 #ifdef CONFIG_GPIO_PCA953X_IRQ 562 static void pca953x_irq_mask(struct irq_data *d) 563 { 564 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 565 struct pca953x_chip *chip = gpiochip_get_data(gc); 566 567 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); 568 } 569 570 static void pca953x_irq_unmask(struct irq_data *d) 571 { 572 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 573 struct pca953x_chip *chip = gpiochip_get_data(gc); 574 575 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); 576 } 577 578 static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) 579 { 580 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 581 struct pca953x_chip *chip = gpiochip_get_data(gc); 582 583 if (on) 584 atomic_inc(&chip->wakeup_path); 585 else 586 atomic_dec(&chip->wakeup_path); 587 588 return irq_set_irq_wake(chip->client->irq, on); 589 } 590 591 static void pca953x_irq_bus_lock(struct irq_data *d) 592 { 593 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 594 struct pca953x_chip *chip = gpiochip_get_data(gc); 595 596 mutex_lock(&chip->irq_lock); 597 } 598 599 static void pca953x_irq_bus_sync_unlock(struct irq_data *d) 600 { 601 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 602 struct pca953x_chip *chip = gpiochip_get_data(gc); 603 u8 new_irqs; 604 int level, i; 605 u8 invert_irq_mask[MAX_BANK]; 606 int reg_direction[MAX_BANK]; 607 608 regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction, 609 NBANK(chip)); 610 611 if (chip->driver_data & PCA_PCAL) { 612 /* Enable latch on interrupt-enabled inputs */ 613 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); 614 615 for (i = 0; i < NBANK(chip); i++) 616 invert_irq_mask[i] = ~chip->irq_mask[i]; 617 618 /* Unmask enabled interrupts */ 619 pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask); 620 } 621 622 /* Look for any newly setup interrupt */ 623 for (i = 0; i < NBANK(chip); i++) { 624 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; 625 new_irqs &= reg_direction[i]; 626 627 while (new_irqs) { 628 level = __ffs(new_irqs); 629 pca953x_gpio_direction_input(&chip->gpio_chip, 630 level + (BANK_SZ * i)); 631 new_irqs &= ~(1 << level); 632 } 633 } 634 635 mutex_unlock(&chip->irq_lock); 636 } 637 638 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) 639 { 640 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 641 struct pca953x_chip *chip = gpiochip_get_data(gc); 642 int bank_nb = d->hwirq / BANK_SZ; 643 u8 mask = 1 << (d->hwirq % BANK_SZ); 644 645 if (!(type & IRQ_TYPE_EDGE_BOTH)) { 646 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", 647 d->irq, type); 648 return -EINVAL; 649 } 650 651 if (type & IRQ_TYPE_EDGE_FALLING) 652 chip->irq_trig_fall[bank_nb] |= mask; 653 else 654 chip->irq_trig_fall[bank_nb] &= ~mask; 655 656 if (type & IRQ_TYPE_EDGE_RISING) 657 chip->irq_trig_raise[bank_nb] |= mask; 658 else 659 chip->irq_trig_raise[bank_nb] &= ~mask; 660 661 return 0; 662 } 663 664 static void pca953x_irq_shutdown(struct irq_data *d) 665 { 666 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 667 struct pca953x_chip *chip = gpiochip_get_data(gc); 668 u8 mask = 1 << (d->hwirq % BANK_SZ); 669 670 chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask; 671 chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask; 672 } 673 674 static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) 675 { 676 u8 cur_stat[MAX_BANK]; 677 u8 old_stat[MAX_BANK]; 678 bool pending_seen = false; 679 bool trigger_seen = false; 680 u8 trigger[MAX_BANK]; 681 int reg_direction[MAX_BANK]; 682 int ret, i; 683 684 if (chip->driver_data & PCA_PCAL) { 685 /* Read the current interrupt status from the device */ 686 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); 687 if (ret) 688 return false; 689 690 /* Check latched inputs and clear interrupt status */ 691 ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat); 692 if (ret) 693 return false; 694 695 for (i = 0; i < NBANK(chip); i++) { 696 /* Apply filter for rising/falling edge selection */ 697 pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) | 698 (cur_stat[i] & chip->irq_trig_raise[i]); 699 pending[i] &= trigger[i]; 700 if (pending[i]) 701 pending_seen = true; 702 } 703 704 return pending_seen; 705 } 706 707 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 708 if (ret) 709 return false; 710 711 /* Remove output pins from the equation */ 712 regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction, 713 NBANK(chip)); 714 for (i = 0; i < NBANK(chip); i++) 715 cur_stat[i] &= reg_direction[i]; 716 717 memcpy(old_stat, chip->irq_stat, NBANK(chip)); 718 719 for (i = 0; i < NBANK(chip); i++) { 720 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; 721 if (trigger[i]) 722 trigger_seen = true; 723 } 724 725 if (!trigger_seen) 726 return false; 727 728 memcpy(chip->irq_stat, cur_stat, NBANK(chip)); 729 730 for (i = 0; i < NBANK(chip); i++) { 731 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | 732 (cur_stat[i] & chip->irq_trig_raise[i]); 733 pending[i] &= trigger[i]; 734 if (pending[i]) 735 pending_seen = true; 736 } 737 738 return pending_seen; 739 } 740 741 static irqreturn_t pca953x_irq_handler(int irq, void *devid) 742 { 743 struct pca953x_chip *chip = devid; 744 u8 pending[MAX_BANK]; 745 u8 level; 746 unsigned nhandled = 0; 747 int i; 748 749 if (!pca953x_irq_pending(chip, pending)) 750 return IRQ_NONE; 751 752 for (i = 0; i < NBANK(chip); i++) { 753 while (pending[i]) { 754 level = __ffs(pending[i]); 755 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain, 756 level + (BANK_SZ * i))); 757 pending[i] &= ~(1 << level); 758 nhandled++; 759 } 760 } 761 762 return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; 763 } 764 765 static int pca953x_irq_setup(struct pca953x_chip *chip, 766 int irq_base) 767 { 768 struct i2c_client *client = chip->client; 769 struct irq_chip *irq_chip = &chip->irq_chip; 770 int reg_direction[MAX_BANK]; 771 int ret, i; 772 773 if (!client->irq) 774 return 0; 775 776 if (irq_base == -1) 777 return 0; 778 779 if (!(chip->driver_data & PCA_INT)) 780 return 0; 781 782 ret = pca953x_read_regs(chip, chip->regs->input, chip->irq_stat); 783 if (ret) 784 return ret; 785 786 /* 787 * There is no way to know which GPIO line generated the 788 * interrupt. We have to rely on the previous read for 789 * this purpose. 790 */ 791 regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction, 792 NBANK(chip)); 793 for (i = 0; i < NBANK(chip); i++) 794 chip->irq_stat[i] &= reg_direction[i]; 795 mutex_init(&chip->irq_lock); 796 797 ret = devm_request_threaded_irq(&client->dev, client->irq, 798 NULL, pca953x_irq_handler, 799 IRQF_TRIGGER_LOW | IRQF_ONESHOT | 800 IRQF_SHARED, 801 dev_name(&client->dev), chip); 802 if (ret) { 803 dev_err(&client->dev, "failed to request irq %d\n", 804 client->irq); 805 return ret; 806 } 807 808 irq_chip->name = dev_name(&chip->client->dev); 809 irq_chip->irq_mask = pca953x_irq_mask; 810 irq_chip->irq_unmask = pca953x_irq_unmask; 811 irq_chip->irq_set_wake = pca953x_irq_set_wake; 812 irq_chip->irq_bus_lock = pca953x_irq_bus_lock; 813 irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock; 814 irq_chip->irq_set_type = pca953x_irq_set_type; 815 irq_chip->irq_shutdown = pca953x_irq_shutdown; 816 817 ret = gpiochip_irqchip_add_nested(&chip->gpio_chip, irq_chip, 818 irq_base, handle_simple_irq, 819 IRQ_TYPE_NONE); 820 if (ret) { 821 dev_err(&client->dev, 822 "could not connect irqchip to gpiochip\n"); 823 return ret; 824 } 825 826 gpiochip_set_nested_irqchip(&chip->gpio_chip, irq_chip, client->irq); 827 828 return 0; 829 } 830 831 #else /* CONFIG_GPIO_PCA953X_IRQ */ 832 static int pca953x_irq_setup(struct pca953x_chip *chip, 833 int irq_base) 834 { 835 struct i2c_client *client = chip->client; 836 837 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) 838 dev_warn(&client->dev, "interrupt support not compiled in\n"); 839 840 return 0; 841 } 842 #endif 843 844 static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert) 845 { 846 int ret; 847 u8 val[MAX_BANK]; 848 849 ret = regcache_sync_region(chip->regmap, chip->regs->output, 850 chip->regs->output + NBANK(chip)); 851 if (ret != 0) 852 goto out; 853 854 ret = regcache_sync_region(chip->regmap, chip->regs->direction, 855 chip->regs->direction + NBANK(chip)); 856 if (ret != 0) 857 goto out; 858 859 /* set platform specific polarity inversion */ 860 if (invert) 861 memset(val, 0xFF, NBANK(chip)); 862 else 863 memset(val, 0, NBANK(chip)); 864 865 ret = pca953x_write_regs(chip, chip->regs->invert, val); 866 out: 867 return ret; 868 } 869 870 static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) 871 { 872 int ret; 873 u8 val[MAX_BANK]; 874 875 ret = device_pca95xx_init(chip, invert); 876 if (ret) 877 goto out; 878 879 /* To enable register 6, 7 to control pull up and pull down */ 880 memset(val, 0x02, NBANK(chip)); 881 ret = pca953x_write_regs(chip, PCA957X_BKEN, val); 882 if (ret) 883 goto out; 884 885 return 0; 886 out: 887 return ret; 888 } 889 890 static const struct of_device_id pca953x_dt_ids[]; 891 892 static int pca953x_probe(struct i2c_client *client, 893 const struct i2c_device_id *i2c_id) 894 { 895 struct pca953x_platform_data *pdata; 896 struct pca953x_chip *chip; 897 int irq_base = 0; 898 int ret; 899 u32 invert = 0; 900 struct regulator *reg; 901 902 chip = devm_kzalloc(&client->dev, 903 sizeof(struct pca953x_chip), GFP_KERNEL); 904 if (chip == NULL) 905 return -ENOMEM; 906 907 pdata = dev_get_platdata(&client->dev); 908 if (pdata) { 909 irq_base = pdata->irq_base; 910 chip->gpio_start = pdata->gpio_base; 911 invert = pdata->invert; 912 chip->names = pdata->names; 913 } else { 914 struct gpio_desc *reset_gpio; 915 916 chip->gpio_start = -1; 917 irq_base = 0; 918 919 /* 920 * See if we need to de-assert a reset pin. 921 * 922 * There is no known ACPI-enabled platforms that are 923 * using "reset" GPIO. Otherwise any of those platform 924 * must use _DSD method with corresponding property. 925 */ 926 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 927 GPIOD_OUT_LOW); 928 if (IS_ERR(reset_gpio)) 929 return PTR_ERR(reset_gpio); 930 } 931 932 chip->client = client; 933 934 reg = devm_regulator_get(&client->dev, "vcc"); 935 if (IS_ERR(reg)) { 936 ret = PTR_ERR(reg); 937 if (ret != -EPROBE_DEFER) 938 dev_err(&client->dev, "reg get err: %d\n", ret); 939 return ret; 940 } 941 ret = regulator_enable(reg); 942 if (ret) { 943 dev_err(&client->dev, "reg en err: %d\n", ret); 944 return ret; 945 } 946 chip->regulator = reg; 947 948 if (i2c_id) { 949 chip->driver_data = i2c_id->driver_data; 950 } else { 951 const struct acpi_device_id *acpi_id; 952 struct device *dev = &client->dev; 953 954 chip->driver_data = (uintptr_t)of_device_get_match_data(dev); 955 if (!chip->driver_data) { 956 acpi_id = acpi_match_device(pca953x_acpi_ids, dev); 957 if (!acpi_id) { 958 ret = -ENODEV; 959 goto err_exit; 960 } 961 962 chip->driver_data = acpi_id->driver_data; 963 } 964 } 965 966 i2c_set_clientdata(client, chip); 967 968 chip->regmap = devm_regmap_init_i2c(client, &pca953x_i2c_regmap); 969 if (IS_ERR(chip->regmap)) { 970 ret = PTR_ERR(chip->regmap); 971 goto err_exit; 972 } 973 974 regcache_mark_dirty(chip->regmap); 975 976 mutex_init(&chip->i2c_lock); 977 /* 978 * In case we have an i2c-mux controlled by a GPIO provided by an 979 * expander using the same driver higher on the device tree, read the 980 * i2c adapter nesting depth and use the retrieved value as lockdep 981 * subclass for chip->i2c_lock. 982 * 983 * REVISIT: This solution is not complete. It protects us from lockdep 984 * false positives when the expander controlling the i2c-mux is on 985 * a different level on the device tree, but not when it's on the same 986 * level on a different branch (in which case the subclass number 987 * would be the same). 988 * 989 * TODO: Once a correct solution is developed, a similar fix should be 990 * applied to all other i2c-controlled GPIO expanders (and potentially 991 * regmap-i2c). 992 */ 993 lockdep_set_subclass(&chip->i2c_lock, 994 i2c_adapter_depth(client->adapter)); 995 996 /* initialize cached registers from their original values. 997 * we can't share this chip with another i2c master. 998 */ 999 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); 1000 1001 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { 1002 chip->regs = &pca953x_regs; 1003 ret = device_pca95xx_init(chip, invert); 1004 } else { 1005 chip->regs = &pca957x_regs; 1006 ret = device_pca957x_init(chip, invert); 1007 } 1008 if (ret) 1009 goto err_exit; 1010 1011 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); 1012 if (ret) 1013 goto err_exit; 1014 1015 ret = pca953x_irq_setup(chip, irq_base); 1016 if (ret) 1017 goto err_exit; 1018 1019 if (pdata && pdata->setup) { 1020 ret = pdata->setup(client, chip->gpio_chip.base, 1021 chip->gpio_chip.ngpio, pdata->context); 1022 if (ret < 0) 1023 dev_warn(&client->dev, "setup failed, %d\n", ret); 1024 } 1025 1026 return 0; 1027 1028 err_exit: 1029 regulator_disable(chip->regulator); 1030 return ret; 1031 } 1032 1033 static int pca953x_remove(struct i2c_client *client) 1034 { 1035 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); 1036 struct pca953x_chip *chip = i2c_get_clientdata(client); 1037 int ret; 1038 1039 if (pdata && pdata->teardown) { 1040 ret = pdata->teardown(client, chip->gpio_chip.base, 1041 chip->gpio_chip.ngpio, pdata->context); 1042 if (ret < 0) 1043 dev_err(&client->dev, "%s failed, %d\n", 1044 "teardown", ret); 1045 } else { 1046 ret = 0; 1047 } 1048 1049 regulator_disable(chip->regulator); 1050 1051 return ret; 1052 } 1053 1054 #ifdef CONFIG_PM_SLEEP 1055 static int pca953x_regcache_sync(struct device *dev) 1056 { 1057 struct pca953x_chip *chip = dev_get_drvdata(dev); 1058 int ret; 1059 1060 /* 1061 * The ordering between direction and output is important, 1062 * sync these registers first and only then sync the rest. 1063 */ 1064 ret = regcache_sync_region(chip->regmap, chip->regs->direction, 1065 chip->regs->direction + NBANK(chip)); 1066 if (ret != 0) { 1067 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); 1068 return ret; 1069 } 1070 1071 ret = regcache_sync_region(chip->regmap, chip->regs->output, 1072 chip->regs->output + NBANK(chip)); 1073 if (ret != 0) { 1074 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); 1075 return ret; 1076 } 1077 1078 #ifdef CONFIG_GPIO_PCA953X_IRQ 1079 if (chip->driver_data & PCA_PCAL) { 1080 ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH, 1081 PCAL953X_IN_LATCH + NBANK(chip)); 1082 if (ret != 0) { 1083 dev_err(dev, "Failed to sync INT latch registers: %d\n", 1084 ret); 1085 return ret; 1086 } 1087 1088 ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK, 1089 PCAL953X_INT_MASK + NBANK(chip)); 1090 if (ret != 0) { 1091 dev_err(dev, "Failed to sync INT mask registers: %d\n", 1092 ret); 1093 return ret; 1094 } 1095 } 1096 #endif 1097 1098 return 0; 1099 } 1100 1101 static int pca953x_suspend(struct device *dev) 1102 { 1103 struct pca953x_chip *chip = dev_get_drvdata(dev); 1104 1105 regcache_cache_only(chip->regmap, true); 1106 1107 if (atomic_read(&chip->wakeup_path)) 1108 device_set_wakeup_path(dev); 1109 else 1110 regulator_disable(chip->regulator); 1111 1112 return 0; 1113 } 1114 1115 static int pca953x_resume(struct device *dev) 1116 { 1117 struct pca953x_chip *chip = dev_get_drvdata(dev); 1118 int ret; 1119 1120 if (!atomic_read(&chip->wakeup_path)) { 1121 ret = regulator_enable(chip->regulator); 1122 if (ret != 0) { 1123 dev_err(dev, "Failed to enable regulator: %d\n", ret); 1124 return 0; 1125 } 1126 } 1127 1128 regcache_cache_only(chip->regmap, false); 1129 regcache_mark_dirty(chip->regmap); 1130 ret = pca953x_regcache_sync(dev); 1131 if (ret) 1132 return ret; 1133 1134 ret = regcache_sync(chip->regmap); 1135 if (ret != 0) { 1136 dev_err(dev, "Failed to restore register map: %d\n", ret); 1137 return ret; 1138 } 1139 1140 return 0; 1141 } 1142 #endif 1143 1144 /* convenience to stop overlong match-table lines */ 1145 #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) 1146 #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) 1147 1148 static const struct of_device_id pca953x_dt_ids[] = { 1149 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, 1150 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, 1151 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, 1152 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, 1153 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, 1154 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, 1155 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, 1156 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, 1157 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, 1158 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, 1159 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, 1160 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, 1161 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, 1162 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, 1163 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, 1164 1165 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1166 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, 1167 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, 1168 1169 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, 1170 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, 1171 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, 1172 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, 1173 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, 1174 1175 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, 1176 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, 1177 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, 1178 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, 1179 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, 1180 1181 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, 1182 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, 1183 1184 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, 1185 { } 1186 }; 1187 1188 MODULE_DEVICE_TABLE(of, pca953x_dt_ids); 1189 1190 static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); 1191 1192 static struct i2c_driver pca953x_driver = { 1193 .driver = { 1194 .name = "pca953x", 1195 .pm = &pca953x_pm_ops, 1196 .of_match_table = pca953x_dt_ids, 1197 .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), 1198 }, 1199 .probe = pca953x_probe, 1200 .remove = pca953x_remove, 1201 .id_table = pca953x_id, 1202 }; 1203 1204 static int __init pca953x_init(void) 1205 { 1206 return i2c_add_driver(&pca953x_driver); 1207 } 1208 /* register after i2c postcore initcall and before 1209 * subsys initcalls that may rely on these GPIOs 1210 */ 1211 subsys_initcall(pca953x_init); 1212 1213 static void __exit pca953x_exit(void) 1214 { 1215 i2c_del_driver(&pca953x_driver); 1216 } 1217 module_exit(pca953x_exit); 1218 1219 MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); 1220 MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); 1221 MODULE_LICENSE("GPL"); 1222