1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCA953x 4/8/16/24/40 bit I/O ports 4 * 5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> 6 * Copyright (C) 2007 Marvell International Ltd. 7 * 8 * Derived from drivers/i2c/chips/pca9539.c 9 */ 10 11 #include <linux/acpi.h> 12 #include <linux/bits.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/i2c.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/module.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_data/pca953x.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 25 #include <asm/unaligned.h> 26 27 #define PCA953X_INPUT 0x00 28 #define PCA953X_OUTPUT 0x01 29 #define PCA953X_INVERT 0x02 30 #define PCA953X_DIRECTION 0x03 31 32 #define REG_ADDR_MASK GENMASK(5, 0) 33 #define REG_ADDR_EXT BIT(6) 34 #define REG_ADDR_AI BIT(7) 35 36 #define PCA957X_IN 0x00 37 #define PCA957X_INVRT 0x01 38 #define PCA957X_BKEN 0x02 39 #define PCA957X_PUPD 0x03 40 #define PCA957X_CFG 0x04 41 #define PCA957X_OUT 0x05 42 #define PCA957X_MSK 0x06 43 #define PCA957X_INTS 0x07 44 45 #define PCAL953X_OUT_STRENGTH 0x20 46 #define PCAL953X_IN_LATCH 0x22 47 #define PCAL953X_PULL_EN 0x23 48 #define PCAL953X_PULL_SEL 0x24 49 #define PCAL953X_INT_MASK 0x25 50 #define PCAL953X_INT_STAT 0x26 51 #define PCAL953X_OUT_CONF 0x27 52 53 #define PCAL6524_INT_EDGE 0x28 54 #define PCAL6524_INT_CLR 0x2a 55 #define PCAL6524_IN_STATUS 0x2b 56 #define PCAL6524_OUT_INDCONF 0x2c 57 #define PCAL6524_DEBOUNCE 0x2d 58 59 #define PCA_GPIO_MASK GENMASK(7, 0) 60 61 #define PCAL_GPIO_MASK GENMASK(4, 0) 62 #define PCAL_PINCTRL_MASK GENMASK(6, 5) 63 64 #define PCA_INT BIT(8) 65 #define PCA_PCAL BIT(9) 66 #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) 67 #define PCA953X_TYPE BIT(12) 68 #define PCA957X_TYPE BIT(13) 69 #define PCA_TYPE_MASK GENMASK(15, 12) 70 71 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) 72 73 static const struct i2c_device_id pca953x_id[] = { 74 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, 75 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, 76 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, 77 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, 78 { "pca9536", 4 | PCA953X_TYPE, }, 79 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, 80 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, 81 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, 82 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, 83 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, 84 { "pca9556", 8 | PCA953X_TYPE, }, 85 { "pca9557", 8 | PCA953X_TYPE, }, 86 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, 87 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, 88 { "pca9698", 40 | PCA953X_TYPE, }, 89 90 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 91 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, 92 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 93 94 { "max7310", 8 | PCA953X_TYPE, }, 95 { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, 96 { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, 97 { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, 98 { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, 99 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, 100 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, 101 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, 102 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, 103 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, 104 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, 105 { "xra1202", 8 | PCA953X_TYPE }, 106 { } 107 }; 108 MODULE_DEVICE_TABLE(i2c, pca953x_id); 109 110 static const struct acpi_device_id pca953x_acpi_ids[] = { 111 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 112 { } 113 }; 114 MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); 115 116 #define MAX_BANK 5 117 #define BANK_SZ 8 118 119 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) 120 121 struct pca953x_reg_config { 122 int direction; 123 int output; 124 int input; 125 int invert; 126 }; 127 128 static const struct pca953x_reg_config pca953x_regs = { 129 .direction = PCA953X_DIRECTION, 130 .output = PCA953X_OUTPUT, 131 .input = PCA953X_INPUT, 132 .invert = PCA953X_INVERT, 133 }; 134 135 static const struct pca953x_reg_config pca957x_regs = { 136 .direction = PCA957X_CFG, 137 .output = PCA957X_OUT, 138 .input = PCA957X_IN, 139 .invert = PCA957X_INVRT, 140 }; 141 142 struct pca953x_chip { 143 unsigned gpio_start; 144 struct mutex i2c_lock; 145 struct regmap *regmap; 146 147 #ifdef CONFIG_GPIO_PCA953X_IRQ 148 struct mutex irq_lock; 149 u8 irq_mask[MAX_BANK]; 150 u8 irq_stat[MAX_BANK]; 151 u8 irq_trig_raise[MAX_BANK]; 152 u8 irq_trig_fall[MAX_BANK]; 153 struct irq_chip irq_chip; 154 #endif 155 atomic_t wakeup_path; 156 157 struct i2c_client *client; 158 struct gpio_chip gpio_chip; 159 const char *const *names; 160 unsigned long driver_data; 161 struct regulator *regulator; 162 163 const struct pca953x_reg_config *regs; 164 }; 165 166 static int pca953x_bank_shift(struct pca953x_chip *chip) 167 { 168 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); 169 } 170 171 #define PCA953x_BANK_INPUT BIT(0) 172 #define PCA953x_BANK_OUTPUT BIT(1) 173 #define PCA953x_BANK_POLARITY BIT(2) 174 #define PCA953x_BANK_CONFIG BIT(3) 175 176 #define PCA957x_BANK_INPUT BIT(0) 177 #define PCA957x_BANK_POLARITY BIT(1) 178 #define PCA957x_BANK_BUSHOLD BIT(2) 179 #define PCA957x_BANK_CONFIG BIT(4) 180 #define PCA957x_BANK_OUTPUT BIT(5) 181 182 #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) 183 #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) 184 #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) 185 #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) 186 #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) 187 188 /* 189 * We care about the following registers: 190 * - Standard set, below 0x40, each port can be replicated up to 8 times 191 * - PCA953x standard 192 * Input port 0x00 + 0 * bank_size R 193 * Output port 0x00 + 1 * bank_size RW 194 * Polarity Inversion port 0x00 + 2 * bank_size RW 195 * Configuration port 0x00 + 3 * bank_size RW 196 * - PCA957x with mixed up registers 197 * Input port 0x00 + 0 * bank_size R 198 * Polarity Inversion port 0x00 + 1 * bank_size RW 199 * Bus hold port 0x00 + 2 * bank_size RW 200 * Configuration port 0x00 + 4 * bank_size RW 201 * Output port 0x00 + 5 * bank_size RW 202 * 203 * - Extended set, above 0x40, often chip specific. 204 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: 205 * Input latch register 0x40 + 2 * bank_size RW 206 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW 207 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW 208 * Interrupt mask register 0x40 + 5 * bank_size RW 209 * Interrupt status register 0x40 + 6 * bank_size R 210 * 211 * - Registers with bit 0x80 set, the AI bit 212 * The bit is cleared and the registers fall into one of the 213 * categories above. 214 */ 215 216 static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, 217 u32 checkbank) 218 { 219 int bank_shift = pca953x_bank_shift(chip); 220 int bank = (reg & REG_ADDR_MASK) >> bank_shift; 221 int offset = reg & (BIT(bank_shift) - 1); 222 223 /* Special PCAL extended register check. */ 224 if (reg & REG_ADDR_EXT) { 225 if (!(chip->driver_data & PCA_PCAL)) 226 return false; 227 bank += 8; 228 } 229 230 /* Register is not in the matching bank. */ 231 if (!(BIT(bank) & checkbank)) 232 return false; 233 234 /* Register is not within allowed range of bank. */ 235 if (offset >= NBANK(chip)) 236 return false; 237 238 return true; 239 } 240 241 static bool pca953x_readable_register(struct device *dev, unsigned int reg) 242 { 243 struct pca953x_chip *chip = dev_get_drvdata(dev); 244 u32 bank; 245 246 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { 247 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | 248 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; 249 } else { 250 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | 251 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | 252 PCA957x_BANK_BUSHOLD; 253 } 254 255 if (chip->driver_data & PCA_PCAL) { 256 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 257 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | 258 PCAL9xxx_BANK_IRQ_STAT; 259 } 260 261 return pca953x_check_register(chip, reg, bank); 262 } 263 264 static bool pca953x_writeable_register(struct device *dev, unsigned int reg) 265 { 266 struct pca953x_chip *chip = dev_get_drvdata(dev); 267 u32 bank; 268 269 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { 270 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | 271 PCA953x_BANK_CONFIG; 272 } else { 273 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | 274 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; 275 } 276 277 if (chip->driver_data & PCA_PCAL) 278 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 279 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; 280 281 return pca953x_check_register(chip, reg, bank); 282 } 283 284 static bool pca953x_volatile_register(struct device *dev, unsigned int reg) 285 { 286 struct pca953x_chip *chip = dev_get_drvdata(dev); 287 u32 bank; 288 289 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) 290 bank = PCA953x_BANK_INPUT; 291 else 292 bank = PCA957x_BANK_INPUT; 293 294 if (chip->driver_data & PCA_PCAL) 295 bank |= PCAL9xxx_BANK_IRQ_STAT; 296 297 return pca953x_check_register(chip, reg, bank); 298 } 299 300 static const struct regmap_config pca953x_i2c_regmap = { 301 .reg_bits = 8, 302 .val_bits = 8, 303 304 .readable_reg = pca953x_readable_register, 305 .writeable_reg = pca953x_writeable_register, 306 .volatile_reg = pca953x_volatile_register, 307 308 .cache_type = REGCACHE_RBTREE, 309 /* REVISIT: should be 0x7f but some 24 bit chips use REG_ADDR_AI */ 310 .max_register = 0xff, 311 }; 312 313 static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off, 314 bool write, bool addrinc) 315 { 316 int bank_shift = pca953x_bank_shift(chip); 317 int addr = (reg & PCAL_GPIO_MASK) << bank_shift; 318 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; 319 u8 regaddr = pinctrl | addr | (off / BANK_SZ); 320 321 /* Single byte read doesn't need AI bit set. */ 322 if (!addrinc) 323 return regaddr; 324 325 /* Chips with 24 and more GPIOs always support Auto Increment */ 326 if (write && NBANK(chip) > 2) 327 regaddr |= REG_ADDR_AI; 328 329 /* PCA9575 needs address-increment on multi-byte writes */ 330 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) 331 regaddr |= REG_ADDR_AI; 332 333 return regaddr; 334 } 335 336 static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) 337 { 338 u8 regaddr = pca953x_recalc_addr(chip, reg, 0, true, true); 339 int ret; 340 341 ret = regmap_bulk_write(chip->regmap, regaddr, val, NBANK(chip)); 342 if (ret < 0) { 343 dev_err(&chip->client->dev, "failed writing register\n"); 344 return ret; 345 } 346 347 return 0; 348 } 349 350 static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) 351 { 352 u8 regaddr = pca953x_recalc_addr(chip, reg, 0, false, true); 353 int ret; 354 355 ret = regmap_bulk_read(chip->regmap, regaddr, val, NBANK(chip)); 356 if (ret < 0) { 357 dev_err(&chip->client->dev, "failed reading register\n"); 358 return ret; 359 } 360 361 return 0; 362 } 363 364 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) 365 { 366 struct pca953x_chip *chip = gpiochip_get_data(gc); 367 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, 368 true, false); 369 u8 bit = BIT(off % BANK_SZ); 370 int ret; 371 372 mutex_lock(&chip->i2c_lock); 373 ret = regmap_write_bits(chip->regmap, dirreg, bit, bit); 374 mutex_unlock(&chip->i2c_lock); 375 return ret; 376 } 377 378 static int pca953x_gpio_direction_output(struct gpio_chip *gc, 379 unsigned off, int val) 380 { 381 struct pca953x_chip *chip = gpiochip_get_data(gc); 382 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, 383 true, false); 384 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, 385 true, false); 386 u8 bit = BIT(off % BANK_SZ); 387 int ret; 388 389 mutex_lock(&chip->i2c_lock); 390 /* set output level */ 391 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 392 if (ret) 393 goto exit; 394 395 /* then direction */ 396 ret = regmap_write_bits(chip->regmap, dirreg, bit, 0); 397 exit: 398 mutex_unlock(&chip->i2c_lock); 399 return ret; 400 } 401 402 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) 403 { 404 struct pca953x_chip *chip = gpiochip_get_data(gc); 405 u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off, 406 true, false); 407 u8 bit = BIT(off % BANK_SZ); 408 u32 reg_val; 409 int ret; 410 411 mutex_lock(&chip->i2c_lock); 412 ret = regmap_read(chip->regmap, inreg, ®_val); 413 mutex_unlock(&chip->i2c_lock); 414 if (ret < 0) { 415 /* NOTE: diagnostic already emitted; that's all we should 416 * do unless gpio_*_value_cansleep() calls become different 417 * from their nonsleeping siblings (and report faults). 418 */ 419 return 0; 420 } 421 422 return !!(reg_val & bit); 423 } 424 425 static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) 426 { 427 struct pca953x_chip *chip = gpiochip_get_data(gc); 428 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, 429 true, false); 430 u8 bit = BIT(off % BANK_SZ); 431 432 mutex_lock(&chip->i2c_lock); 433 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 434 mutex_unlock(&chip->i2c_lock); 435 } 436 437 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) 438 { 439 struct pca953x_chip *chip = gpiochip_get_data(gc); 440 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off, 441 true, false); 442 u8 bit = BIT(off % BANK_SZ); 443 u32 reg_val; 444 int ret; 445 446 mutex_lock(&chip->i2c_lock); 447 ret = regmap_read(chip->regmap, dirreg, ®_val); 448 mutex_unlock(&chip->i2c_lock); 449 if (ret < 0) 450 return ret; 451 452 if (reg_val & bit) 453 return GPIO_LINE_DIRECTION_IN; 454 455 return GPIO_LINE_DIRECTION_OUT; 456 } 457 458 static void pca953x_gpio_set_multiple(struct gpio_chip *gc, 459 unsigned long *mask, unsigned long *bits) 460 { 461 struct pca953x_chip *chip = gpiochip_get_data(gc); 462 unsigned int bank_mask, bank_val; 463 int bank; 464 u8 reg_val[MAX_BANK]; 465 int ret; 466 467 mutex_lock(&chip->i2c_lock); 468 ret = pca953x_read_regs(chip, chip->regs->output, reg_val); 469 if (ret) 470 goto exit; 471 472 for (bank = 0; bank < NBANK(chip); bank++) { 473 bank_mask = mask[bank / sizeof(*mask)] >> 474 ((bank % sizeof(*mask)) * 8); 475 if (bank_mask) { 476 bank_val = bits[bank / sizeof(*bits)] >> 477 ((bank % sizeof(*bits)) * 8); 478 bank_val &= bank_mask; 479 reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val; 480 } 481 } 482 483 pca953x_write_regs(chip, chip->regs->output, reg_val); 484 exit: 485 mutex_unlock(&chip->i2c_lock); 486 } 487 488 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, 489 unsigned int offset, 490 unsigned long config) 491 { 492 u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset, 493 true, false); 494 u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset, 495 true, false); 496 u8 bit = BIT(offset % BANK_SZ); 497 int ret; 498 499 /* 500 * pull-up/pull-down configuration requires PCAL extended 501 * registers 502 */ 503 if (!(chip->driver_data & PCA_PCAL)) 504 return -ENOTSUPP; 505 506 mutex_lock(&chip->i2c_lock); 507 508 /* Disable pull-up/pull-down */ 509 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0); 510 if (ret) 511 goto exit; 512 513 /* Configure pull-up/pull-down */ 514 if (config == PIN_CONFIG_BIAS_PULL_UP) 515 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit); 516 else if (config == PIN_CONFIG_BIAS_PULL_DOWN) 517 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0); 518 if (ret) 519 goto exit; 520 521 /* Enable pull-up/pull-down */ 522 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit); 523 524 exit: 525 mutex_unlock(&chip->i2c_lock); 526 return ret; 527 } 528 529 static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 530 unsigned long config) 531 { 532 struct pca953x_chip *chip = gpiochip_get_data(gc); 533 534 switch (config) { 535 case PIN_CONFIG_BIAS_PULL_UP: 536 case PIN_CONFIG_BIAS_PULL_DOWN: 537 return pca953x_gpio_set_pull_up_down(chip, offset, config); 538 default: 539 return -ENOTSUPP; 540 } 541 } 542 543 static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) 544 { 545 struct gpio_chip *gc; 546 547 gc = &chip->gpio_chip; 548 549 gc->direction_input = pca953x_gpio_direction_input; 550 gc->direction_output = pca953x_gpio_direction_output; 551 gc->get = pca953x_gpio_get_value; 552 gc->set = pca953x_gpio_set_value; 553 gc->get_direction = pca953x_gpio_get_direction; 554 gc->set_multiple = pca953x_gpio_set_multiple; 555 gc->set_config = pca953x_gpio_set_config; 556 gc->can_sleep = true; 557 558 gc->base = chip->gpio_start; 559 gc->ngpio = gpios; 560 gc->label = dev_name(&chip->client->dev); 561 gc->parent = &chip->client->dev; 562 gc->owner = THIS_MODULE; 563 gc->names = chip->names; 564 } 565 566 #ifdef CONFIG_GPIO_PCA953X_IRQ 567 static void pca953x_irq_mask(struct irq_data *d) 568 { 569 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 570 struct pca953x_chip *chip = gpiochip_get_data(gc); 571 572 chip->irq_mask[d->hwirq / BANK_SZ] &= ~BIT(d->hwirq % BANK_SZ); 573 } 574 575 static void pca953x_irq_unmask(struct irq_data *d) 576 { 577 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 578 struct pca953x_chip *chip = gpiochip_get_data(gc); 579 580 chip->irq_mask[d->hwirq / BANK_SZ] |= BIT(d->hwirq % BANK_SZ); 581 } 582 583 static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) 584 { 585 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 586 struct pca953x_chip *chip = gpiochip_get_data(gc); 587 588 if (on) 589 atomic_inc(&chip->wakeup_path); 590 else 591 atomic_dec(&chip->wakeup_path); 592 593 return irq_set_irq_wake(chip->client->irq, on); 594 } 595 596 static void pca953x_irq_bus_lock(struct irq_data *d) 597 { 598 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 599 struct pca953x_chip *chip = gpiochip_get_data(gc); 600 601 mutex_lock(&chip->irq_lock); 602 } 603 604 static void pca953x_irq_bus_sync_unlock(struct irq_data *d) 605 { 606 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 607 struct pca953x_chip *chip = gpiochip_get_data(gc); 608 u8 new_irqs; 609 int level, i; 610 u8 invert_irq_mask[MAX_BANK]; 611 u8 reg_direction[MAX_BANK]; 612 613 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 614 615 if (chip->driver_data & PCA_PCAL) { 616 /* Enable latch on interrupt-enabled inputs */ 617 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); 618 619 for (i = 0; i < NBANK(chip); i++) 620 invert_irq_mask[i] = ~chip->irq_mask[i]; 621 622 /* Unmask enabled interrupts */ 623 pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask); 624 } 625 626 /* Look for any newly setup interrupt */ 627 for (i = 0; i < NBANK(chip); i++) { 628 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; 629 new_irqs &= reg_direction[i]; 630 631 while (new_irqs) { 632 level = __ffs(new_irqs); 633 pca953x_gpio_direction_input(&chip->gpio_chip, 634 level + (BANK_SZ * i)); 635 new_irqs &= ~(1 << level); 636 } 637 } 638 639 mutex_unlock(&chip->irq_lock); 640 } 641 642 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) 643 { 644 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 645 struct pca953x_chip *chip = gpiochip_get_data(gc); 646 int bank_nb = d->hwirq / BANK_SZ; 647 u8 mask = BIT(d->hwirq % BANK_SZ); 648 649 if (!(type & IRQ_TYPE_EDGE_BOTH)) { 650 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", 651 d->irq, type); 652 return -EINVAL; 653 } 654 655 if (type & IRQ_TYPE_EDGE_FALLING) 656 chip->irq_trig_fall[bank_nb] |= mask; 657 else 658 chip->irq_trig_fall[bank_nb] &= ~mask; 659 660 if (type & IRQ_TYPE_EDGE_RISING) 661 chip->irq_trig_raise[bank_nb] |= mask; 662 else 663 chip->irq_trig_raise[bank_nb] &= ~mask; 664 665 return 0; 666 } 667 668 static void pca953x_irq_shutdown(struct irq_data *d) 669 { 670 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 671 struct pca953x_chip *chip = gpiochip_get_data(gc); 672 u8 mask = BIT(d->hwirq % BANK_SZ); 673 674 chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask; 675 chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask; 676 } 677 678 static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) 679 { 680 u8 cur_stat[MAX_BANK]; 681 u8 old_stat[MAX_BANK]; 682 bool pending_seen = false; 683 bool trigger_seen = false; 684 u8 trigger[MAX_BANK]; 685 u8 reg_direction[MAX_BANK]; 686 int ret, i; 687 688 if (chip->driver_data & PCA_PCAL) { 689 /* Read the current interrupt status from the device */ 690 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); 691 if (ret) 692 return false; 693 694 /* Check latched inputs and clear interrupt status */ 695 ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat); 696 if (ret) 697 return false; 698 699 for (i = 0; i < NBANK(chip); i++) { 700 /* Apply filter for rising/falling edge selection */ 701 pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) | 702 (cur_stat[i] & chip->irq_trig_raise[i]); 703 pending[i] &= trigger[i]; 704 if (pending[i]) 705 pending_seen = true; 706 } 707 708 return pending_seen; 709 } 710 711 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 712 if (ret) 713 return false; 714 715 /* Remove output pins from the equation */ 716 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 717 for (i = 0; i < NBANK(chip); i++) 718 cur_stat[i] &= reg_direction[i]; 719 720 memcpy(old_stat, chip->irq_stat, NBANK(chip)); 721 722 for (i = 0; i < NBANK(chip); i++) { 723 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; 724 if (trigger[i]) 725 trigger_seen = true; 726 } 727 728 if (!trigger_seen) 729 return false; 730 731 memcpy(chip->irq_stat, cur_stat, NBANK(chip)); 732 733 for (i = 0; i < NBANK(chip); i++) { 734 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | 735 (cur_stat[i] & chip->irq_trig_raise[i]); 736 pending[i] &= trigger[i]; 737 if (pending[i]) 738 pending_seen = true; 739 } 740 741 return pending_seen; 742 } 743 744 static irqreturn_t pca953x_irq_handler(int irq, void *devid) 745 { 746 struct pca953x_chip *chip = devid; 747 u8 pending[MAX_BANK]; 748 u8 level; 749 unsigned nhandled = 0; 750 int i; 751 752 if (!pca953x_irq_pending(chip, pending)) 753 return IRQ_NONE; 754 755 for (i = 0; i < NBANK(chip); i++) { 756 while (pending[i]) { 757 level = __ffs(pending[i]); 758 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain, 759 level + (BANK_SZ * i))); 760 pending[i] &= ~(1 << level); 761 nhandled++; 762 } 763 } 764 765 return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; 766 } 767 768 static int pca953x_irq_setup(struct pca953x_chip *chip, 769 int irq_base) 770 { 771 struct i2c_client *client = chip->client; 772 struct irq_chip *irq_chip = &chip->irq_chip; 773 u8 reg_direction[MAX_BANK]; 774 int ret, i; 775 776 if (!client->irq) 777 return 0; 778 779 if (irq_base == -1) 780 return 0; 781 782 if (!(chip->driver_data & PCA_INT)) 783 return 0; 784 785 ret = pca953x_read_regs(chip, chip->regs->input, chip->irq_stat); 786 if (ret) 787 return ret; 788 789 /* 790 * There is no way to know which GPIO line generated the 791 * interrupt. We have to rely on the previous read for 792 * this purpose. 793 */ 794 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 795 for (i = 0; i < NBANK(chip); i++) 796 chip->irq_stat[i] &= reg_direction[i]; 797 mutex_init(&chip->irq_lock); 798 799 ret = devm_request_threaded_irq(&client->dev, client->irq, 800 NULL, pca953x_irq_handler, 801 IRQF_TRIGGER_LOW | IRQF_ONESHOT | 802 IRQF_SHARED, 803 dev_name(&client->dev), chip); 804 if (ret) { 805 dev_err(&client->dev, "failed to request irq %d\n", 806 client->irq); 807 return ret; 808 } 809 810 irq_chip->name = dev_name(&chip->client->dev); 811 irq_chip->irq_mask = pca953x_irq_mask; 812 irq_chip->irq_unmask = pca953x_irq_unmask; 813 irq_chip->irq_set_wake = pca953x_irq_set_wake; 814 irq_chip->irq_bus_lock = pca953x_irq_bus_lock; 815 irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock; 816 irq_chip->irq_set_type = pca953x_irq_set_type; 817 irq_chip->irq_shutdown = pca953x_irq_shutdown; 818 819 ret = gpiochip_irqchip_add_nested(&chip->gpio_chip, irq_chip, 820 irq_base, handle_simple_irq, 821 IRQ_TYPE_NONE); 822 if (ret) { 823 dev_err(&client->dev, 824 "could not connect irqchip to gpiochip\n"); 825 return ret; 826 } 827 828 gpiochip_set_nested_irqchip(&chip->gpio_chip, irq_chip, client->irq); 829 830 return 0; 831 } 832 833 #else /* CONFIG_GPIO_PCA953X_IRQ */ 834 static int pca953x_irq_setup(struct pca953x_chip *chip, 835 int irq_base) 836 { 837 struct i2c_client *client = chip->client; 838 839 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) 840 dev_warn(&client->dev, "interrupt support not compiled in\n"); 841 842 return 0; 843 } 844 #endif 845 846 static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert) 847 { 848 int ret; 849 u8 val[MAX_BANK]; 850 851 ret = regcache_sync_region(chip->regmap, chip->regs->output, 852 chip->regs->output + NBANK(chip)); 853 if (ret) 854 goto out; 855 856 ret = regcache_sync_region(chip->regmap, chip->regs->direction, 857 chip->regs->direction + NBANK(chip)); 858 if (ret) 859 goto out; 860 861 /* set platform specific polarity inversion */ 862 if (invert) 863 memset(val, 0xFF, NBANK(chip)); 864 else 865 memset(val, 0, NBANK(chip)); 866 867 ret = pca953x_write_regs(chip, chip->regs->invert, val); 868 out: 869 return ret; 870 } 871 872 static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) 873 { 874 int ret; 875 u8 val[MAX_BANK]; 876 877 ret = device_pca95xx_init(chip, invert); 878 if (ret) 879 goto out; 880 881 /* To enable register 6, 7 to control pull up and pull down */ 882 memset(val, 0x02, NBANK(chip)); 883 ret = pca953x_write_regs(chip, PCA957X_BKEN, val); 884 if (ret) 885 goto out; 886 887 return 0; 888 out: 889 return ret; 890 } 891 892 static const struct of_device_id pca953x_dt_ids[]; 893 894 static int pca953x_probe(struct i2c_client *client, 895 const struct i2c_device_id *i2c_id) 896 { 897 struct pca953x_platform_data *pdata; 898 struct pca953x_chip *chip; 899 int irq_base = 0; 900 int ret; 901 u32 invert = 0; 902 struct regulator *reg; 903 904 chip = devm_kzalloc(&client->dev, 905 sizeof(struct pca953x_chip), GFP_KERNEL); 906 if (chip == NULL) 907 return -ENOMEM; 908 909 pdata = dev_get_platdata(&client->dev); 910 if (pdata) { 911 irq_base = pdata->irq_base; 912 chip->gpio_start = pdata->gpio_base; 913 invert = pdata->invert; 914 chip->names = pdata->names; 915 } else { 916 struct gpio_desc *reset_gpio; 917 918 chip->gpio_start = -1; 919 irq_base = 0; 920 921 /* 922 * See if we need to de-assert a reset pin. 923 * 924 * There is no known ACPI-enabled platforms that are 925 * using "reset" GPIO. Otherwise any of those platform 926 * must use _DSD method with corresponding property. 927 */ 928 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 929 GPIOD_OUT_LOW); 930 if (IS_ERR(reset_gpio)) 931 return PTR_ERR(reset_gpio); 932 } 933 934 chip->client = client; 935 936 reg = devm_regulator_get(&client->dev, "vcc"); 937 if (IS_ERR(reg)) { 938 ret = PTR_ERR(reg); 939 if (ret != -EPROBE_DEFER) 940 dev_err(&client->dev, "reg get err: %d\n", ret); 941 return ret; 942 } 943 ret = regulator_enable(reg); 944 if (ret) { 945 dev_err(&client->dev, "reg en err: %d\n", ret); 946 return ret; 947 } 948 chip->regulator = reg; 949 950 if (i2c_id) { 951 chip->driver_data = i2c_id->driver_data; 952 } else { 953 const void *match; 954 955 match = device_get_match_data(&client->dev); 956 if (!match) { 957 ret = -ENODEV; 958 goto err_exit; 959 } 960 961 chip->driver_data = (uintptr_t)match; 962 } 963 964 i2c_set_clientdata(client, chip); 965 966 chip->regmap = devm_regmap_init_i2c(client, &pca953x_i2c_regmap); 967 if (IS_ERR(chip->regmap)) { 968 ret = PTR_ERR(chip->regmap); 969 goto err_exit; 970 } 971 972 regcache_mark_dirty(chip->regmap); 973 974 mutex_init(&chip->i2c_lock); 975 /* 976 * In case we have an i2c-mux controlled by a GPIO provided by an 977 * expander using the same driver higher on the device tree, read the 978 * i2c adapter nesting depth and use the retrieved value as lockdep 979 * subclass for chip->i2c_lock. 980 * 981 * REVISIT: This solution is not complete. It protects us from lockdep 982 * false positives when the expander controlling the i2c-mux is on 983 * a different level on the device tree, but not when it's on the same 984 * level on a different branch (in which case the subclass number 985 * would be the same). 986 * 987 * TODO: Once a correct solution is developed, a similar fix should be 988 * applied to all other i2c-controlled GPIO expanders (and potentially 989 * regmap-i2c). 990 */ 991 lockdep_set_subclass(&chip->i2c_lock, 992 i2c_adapter_depth(client->adapter)); 993 994 /* initialize cached registers from their original values. 995 * we can't share this chip with another i2c master. 996 */ 997 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); 998 999 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { 1000 chip->regs = &pca953x_regs; 1001 ret = device_pca95xx_init(chip, invert); 1002 } else { 1003 chip->regs = &pca957x_regs; 1004 ret = device_pca957x_init(chip, invert); 1005 } 1006 if (ret) 1007 goto err_exit; 1008 1009 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); 1010 if (ret) 1011 goto err_exit; 1012 1013 ret = pca953x_irq_setup(chip, irq_base); 1014 if (ret) 1015 goto err_exit; 1016 1017 if (pdata && pdata->setup) { 1018 ret = pdata->setup(client, chip->gpio_chip.base, 1019 chip->gpio_chip.ngpio, pdata->context); 1020 if (ret < 0) 1021 dev_warn(&client->dev, "setup failed, %d\n", ret); 1022 } 1023 1024 return 0; 1025 1026 err_exit: 1027 regulator_disable(chip->regulator); 1028 return ret; 1029 } 1030 1031 static int pca953x_remove(struct i2c_client *client) 1032 { 1033 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); 1034 struct pca953x_chip *chip = i2c_get_clientdata(client); 1035 int ret; 1036 1037 if (pdata && pdata->teardown) { 1038 ret = pdata->teardown(client, chip->gpio_chip.base, 1039 chip->gpio_chip.ngpio, pdata->context); 1040 if (ret < 0) 1041 dev_err(&client->dev, "teardown failed, %d\n", ret); 1042 } else { 1043 ret = 0; 1044 } 1045 1046 regulator_disable(chip->regulator); 1047 1048 return ret; 1049 } 1050 1051 #ifdef CONFIG_PM_SLEEP 1052 static int pca953x_regcache_sync(struct device *dev) 1053 { 1054 struct pca953x_chip *chip = dev_get_drvdata(dev); 1055 int ret; 1056 1057 /* 1058 * The ordering between direction and output is important, 1059 * sync these registers first and only then sync the rest. 1060 */ 1061 ret = regcache_sync_region(chip->regmap, chip->regs->direction, 1062 chip->regs->direction + NBANK(chip)); 1063 if (ret) { 1064 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); 1065 return ret; 1066 } 1067 1068 ret = regcache_sync_region(chip->regmap, chip->regs->output, 1069 chip->regs->output + NBANK(chip)); 1070 if (ret) { 1071 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); 1072 return ret; 1073 } 1074 1075 #ifdef CONFIG_GPIO_PCA953X_IRQ 1076 if (chip->driver_data & PCA_PCAL) { 1077 ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH, 1078 PCAL953X_IN_LATCH + NBANK(chip)); 1079 if (ret) { 1080 dev_err(dev, "Failed to sync INT latch registers: %d\n", 1081 ret); 1082 return ret; 1083 } 1084 1085 ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK, 1086 PCAL953X_INT_MASK + NBANK(chip)); 1087 if (ret) { 1088 dev_err(dev, "Failed to sync INT mask registers: %d\n", 1089 ret); 1090 return ret; 1091 } 1092 } 1093 #endif 1094 1095 return 0; 1096 } 1097 1098 static int pca953x_suspend(struct device *dev) 1099 { 1100 struct pca953x_chip *chip = dev_get_drvdata(dev); 1101 1102 regcache_cache_only(chip->regmap, true); 1103 1104 if (atomic_read(&chip->wakeup_path)) 1105 device_set_wakeup_path(dev); 1106 else 1107 regulator_disable(chip->regulator); 1108 1109 return 0; 1110 } 1111 1112 static int pca953x_resume(struct device *dev) 1113 { 1114 struct pca953x_chip *chip = dev_get_drvdata(dev); 1115 int ret; 1116 1117 if (!atomic_read(&chip->wakeup_path)) { 1118 ret = regulator_enable(chip->regulator); 1119 if (ret) { 1120 dev_err(dev, "Failed to enable regulator: %d\n", ret); 1121 return 0; 1122 } 1123 } 1124 1125 regcache_cache_only(chip->regmap, false); 1126 regcache_mark_dirty(chip->regmap); 1127 ret = pca953x_regcache_sync(dev); 1128 if (ret) 1129 return ret; 1130 1131 ret = regcache_sync(chip->regmap); 1132 if (ret) { 1133 dev_err(dev, "Failed to restore register map: %d\n", ret); 1134 return ret; 1135 } 1136 1137 return 0; 1138 } 1139 #endif 1140 1141 /* convenience to stop overlong match-table lines */ 1142 #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) 1143 #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) 1144 1145 static const struct of_device_id pca953x_dt_ids[] = { 1146 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, 1147 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, 1148 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, 1149 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, 1150 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, 1151 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, 1152 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, 1153 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, 1154 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, 1155 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, 1156 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, 1157 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, 1158 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, 1159 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, 1160 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, 1161 1162 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1163 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, 1164 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, 1165 1166 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, 1167 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, 1168 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, 1169 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, 1170 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, 1171 1172 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, 1173 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, 1174 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, 1175 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, 1176 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, 1177 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, 1178 1179 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, 1180 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, 1181 1182 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, 1183 { } 1184 }; 1185 1186 MODULE_DEVICE_TABLE(of, pca953x_dt_ids); 1187 1188 static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); 1189 1190 static struct i2c_driver pca953x_driver = { 1191 .driver = { 1192 .name = "pca953x", 1193 .pm = &pca953x_pm_ops, 1194 .of_match_table = pca953x_dt_ids, 1195 .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), 1196 }, 1197 .probe = pca953x_probe, 1198 .remove = pca953x_remove, 1199 .id_table = pca953x_id, 1200 }; 1201 1202 static int __init pca953x_init(void) 1203 { 1204 return i2c_add_driver(&pca953x_driver); 1205 } 1206 /* register after i2c postcore initcall and before 1207 * subsys initcalls that may rely on these GPIOs 1208 */ 1209 subsys_initcall(pca953x_init); 1210 1211 static void __exit pca953x_exit(void) 1212 { 1213 i2c_del_driver(&pca953x_driver); 1214 } 1215 module_exit(pca953x_exit); 1216 1217 MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); 1218 MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); 1219 MODULE_LICENSE("GPL"); 1220