xref: /openbmc/linux/drivers/gpio/gpio-omap.c (revision f7d84fa7) 
1 /*
2  * Support functions for OMAP GPIO
3  *
4  * Copyright (C) 2003-2005 Nokia Corporation
5  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6  *
7  * Copyright (C) 2009 Texas Instruments
8  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  */
14 
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/gpio.h>
28 #include <linux/bitops.h>
29 #include <linux/platform_data/gpio-omap.h>
30 
31 #define OFF_MODE	1
32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
33 
34 static LIST_HEAD(omap_gpio_list);
35 
36 struct gpio_regs {
37 	u32 irqenable1;
38 	u32 irqenable2;
39 	u32 wake_en;
40 	u32 ctrl;
41 	u32 oe;
42 	u32 leveldetect0;
43 	u32 leveldetect1;
44 	u32 risingdetect;
45 	u32 fallingdetect;
46 	u32 dataout;
47 	u32 debounce;
48 	u32 debounce_en;
49 };
50 
51 struct gpio_bank {
52 	struct list_head node;
53 	void __iomem *base;
54 	int irq;
55 	u32 non_wakeup_gpios;
56 	u32 enabled_non_wakeup_gpios;
57 	struct gpio_regs context;
58 	u32 saved_datain;
59 	u32 level_mask;
60 	u32 toggle_mask;
61 	raw_spinlock_t lock;
62 	raw_spinlock_t wa_lock;
63 	struct gpio_chip chip;
64 	struct clk *dbck;
65 	u32 mod_usage;
66 	u32 irq_usage;
67 	u32 dbck_enable_mask;
68 	bool dbck_enabled;
69 	bool is_mpuio;
70 	bool dbck_flag;
71 	bool loses_context;
72 	bool context_valid;
73 	int stride;
74 	u32 width;
75 	int context_loss_count;
76 	int power_mode;
77 	bool workaround_enabled;
78 
79 	void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
80 	int (*get_context_loss_count)(struct device *dev);
81 
82 	struct omap_gpio_reg_offs *regs;
83 };
84 
85 #define GPIO_MOD_CTRL_BIT	BIT(0)
86 
87 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
88 #define LINE_USED(line, offset) (line & (BIT(offset)))
89 
90 static void omap_gpio_unmask_irq(struct irq_data *d);
91 
92 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
93 {
94 	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
95 	return gpiochip_get_data(chip);
96 }
97 
98 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
99 				    int is_input)
100 {
101 	void __iomem *reg = bank->base;
102 	u32 l;
103 
104 	reg += bank->regs->direction;
105 	l = readl_relaxed(reg);
106 	if (is_input)
107 		l |= BIT(gpio);
108 	else
109 		l &= ~(BIT(gpio));
110 	writel_relaxed(l, reg);
111 	bank->context.oe = l;
112 }
113 
114 
115 /* set data out value using dedicate set/clear register */
116 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
117 				      int enable)
118 {
119 	void __iomem *reg = bank->base;
120 	u32 l = BIT(offset);
121 
122 	if (enable) {
123 		reg += bank->regs->set_dataout;
124 		bank->context.dataout |= l;
125 	} else {
126 		reg += bank->regs->clr_dataout;
127 		bank->context.dataout &= ~l;
128 	}
129 
130 	writel_relaxed(l, reg);
131 }
132 
133 /* set data out value using mask register */
134 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
135 				       int enable)
136 {
137 	void __iomem *reg = bank->base + bank->regs->dataout;
138 	u32 gpio_bit = BIT(offset);
139 	u32 l;
140 
141 	l = readl_relaxed(reg);
142 	if (enable)
143 		l |= gpio_bit;
144 	else
145 		l &= ~gpio_bit;
146 	writel_relaxed(l, reg);
147 	bank->context.dataout = l;
148 }
149 
150 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
151 {
152 	void __iomem *reg = bank->base + bank->regs->datain;
153 
154 	return (readl_relaxed(reg) & (BIT(offset))) != 0;
155 }
156 
157 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
158 {
159 	void __iomem *reg = bank->base + bank->regs->dataout;
160 
161 	return (readl_relaxed(reg) & (BIT(offset))) != 0;
162 }
163 
164 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
165 {
166 	int l = readl_relaxed(base + reg);
167 
168 	if (set)
169 		l |= mask;
170 	else
171 		l &= ~mask;
172 
173 	writel_relaxed(l, base + reg);
174 }
175 
176 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
177 {
178 	if (bank->dbck_enable_mask && !bank->dbck_enabled) {
179 		clk_enable(bank->dbck);
180 		bank->dbck_enabled = true;
181 
182 		writel_relaxed(bank->dbck_enable_mask,
183 			     bank->base + bank->regs->debounce_en);
184 	}
185 }
186 
187 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
188 {
189 	if (bank->dbck_enable_mask && bank->dbck_enabled) {
190 		/*
191 		 * Disable debounce before cutting it's clock. If debounce is
192 		 * enabled but the clock is not, GPIO module seems to be unable
193 		 * to detect events and generate interrupts at least on OMAP3.
194 		 */
195 		writel_relaxed(0, bank->base + bank->regs->debounce_en);
196 
197 		clk_disable(bank->dbck);
198 		bank->dbck_enabled = false;
199 	}
200 }
201 
202 /**
203  * omap2_set_gpio_debounce - low level gpio debounce time
204  * @bank: the gpio bank we're acting upon
205  * @offset: the gpio number on this @bank
206  * @debounce: debounce time to use
207  *
208  * OMAP's debounce time is in 31us steps
209  *   <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
210  * so we need to convert and round up to the closest unit.
211  *
212  * Return: 0 on success, negative error otherwise.
213  */
214 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
215 				   unsigned debounce)
216 {
217 	void __iomem		*reg;
218 	u32			val;
219 	u32			l;
220 	bool			enable = !!debounce;
221 
222 	if (!bank->dbck_flag)
223 		return -ENOTSUPP;
224 
225 	if (enable) {
226 		debounce = DIV_ROUND_UP(debounce, 31) - 1;
227 		if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
228 			return -EINVAL;
229 	}
230 
231 	l = BIT(offset);
232 
233 	clk_enable(bank->dbck);
234 	reg = bank->base + bank->regs->debounce;
235 	writel_relaxed(debounce, reg);
236 
237 	reg = bank->base + bank->regs->debounce_en;
238 	val = readl_relaxed(reg);
239 
240 	if (enable)
241 		val |= l;
242 	else
243 		val &= ~l;
244 	bank->dbck_enable_mask = val;
245 
246 	writel_relaxed(val, reg);
247 	clk_disable(bank->dbck);
248 	/*
249 	 * Enable debounce clock per module.
250 	 * This call is mandatory because in omap_gpio_request() when
251 	 * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
252 	 * runtime callbck fails to turn on dbck because dbck_enable_mask
253 	 * used within _gpio_dbck_enable() is still not initialized at
254 	 * that point. Therefore we have to enable dbck here.
255 	 */
256 	omap_gpio_dbck_enable(bank);
257 	if (bank->dbck_enable_mask) {
258 		bank->context.debounce = debounce;
259 		bank->context.debounce_en = val;
260 	}
261 
262 	return 0;
263 }
264 
265 /**
266  * omap_clear_gpio_debounce - clear debounce settings for a gpio
267  * @bank: the gpio bank we're acting upon
268  * @offset: the gpio number on this @bank
269  *
270  * If a gpio is using debounce, then clear the debounce enable bit and if
271  * this is the only gpio in this bank using debounce, then clear the debounce
272  * time too. The debounce clock will also be disabled when calling this function
273  * if this is the only gpio in the bank using debounce.
274  */
275 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
276 {
277 	u32 gpio_bit = BIT(offset);
278 
279 	if (!bank->dbck_flag)
280 		return;
281 
282 	if (!(bank->dbck_enable_mask & gpio_bit))
283 		return;
284 
285 	bank->dbck_enable_mask &= ~gpio_bit;
286 	bank->context.debounce_en &= ~gpio_bit;
287         writel_relaxed(bank->context.debounce_en,
288 		     bank->base + bank->regs->debounce_en);
289 
290 	if (!bank->dbck_enable_mask) {
291 		bank->context.debounce = 0;
292 		writel_relaxed(bank->context.debounce, bank->base +
293 			     bank->regs->debounce);
294 		clk_disable(bank->dbck);
295 		bank->dbck_enabled = false;
296 	}
297 }
298 
299 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
300 						unsigned trigger)
301 {
302 	void __iomem *base = bank->base;
303 	u32 gpio_bit = BIT(gpio);
304 
305 	omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
306 		      trigger & IRQ_TYPE_LEVEL_LOW);
307 	omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
308 		      trigger & IRQ_TYPE_LEVEL_HIGH);
309 	omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
310 		      trigger & IRQ_TYPE_EDGE_RISING);
311 	omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
312 		      trigger & IRQ_TYPE_EDGE_FALLING);
313 
314 	bank->context.leveldetect0 =
315 			readl_relaxed(bank->base + bank->regs->leveldetect0);
316 	bank->context.leveldetect1 =
317 			readl_relaxed(bank->base + bank->regs->leveldetect1);
318 	bank->context.risingdetect =
319 			readl_relaxed(bank->base + bank->regs->risingdetect);
320 	bank->context.fallingdetect =
321 			readl_relaxed(bank->base + bank->regs->fallingdetect);
322 
323 	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
324 		omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
325 		bank->context.wake_en =
326 			readl_relaxed(bank->base + bank->regs->wkup_en);
327 	}
328 
329 	/* This part needs to be executed always for OMAP{34xx, 44xx} */
330 	if (!bank->regs->irqctrl) {
331 		/* On omap24xx proceed only when valid GPIO bit is set */
332 		if (bank->non_wakeup_gpios) {
333 			if (!(bank->non_wakeup_gpios & gpio_bit))
334 				goto exit;
335 		}
336 
337 		/*
338 		 * Log the edge gpio and manually trigger the IRQ
339 		 * after resume if the input level changes
340 		 * to avoid irq lost during PER RET/OFF mode
341 		 * Applies for omap2 non-wakeup gpio and all omap3 gpios
342 		 */
343 		if (trigger & IRQ_TYPE_EDGE_BOTH)
344 			bank->enabled_non_wakeup_gpios |= gpio_bit;
345 		else
346 			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
347 	}
348 
349 exit:
350 	bank->level_mask =
351 		readl_relaxed(bank->base + bank->regs->leveldetect0) |
352 		readl_relaxed(bank->base + bank->regs->leveldetect1);
353 }
354 
355 #ifdef CONFIG_ARCH_OMAP1
356 /*
357  * This only applies to chips that can't do both rising and falling edge
358  * detection at once.  For all other chips, this function is a noop.
359  */
360 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
361 {
362 	void __iomem *reg = bank->base;
363 	u32 l = 0;
364 
365 	if (!bank->regs->irqctrl)
366 		return;
367 
368 	reg += bank->regs->irqctrl;
369 
370 	l = readl_relaxed(reg);
371 	if ((l >> gpio) & 1)
372 		l &= ~(BIT(gpio));
373 	else
374 		l |= BIT(gpio);
375 
376 	writel_relaxed(l, reg);
377 }
378 #else
379 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
380 #endif
381 
382 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
383 				    unsigned trigger)
384 {
385 	void __iomem *reg = bank->base;
386 	void __iomem *base = bank->base;
387 	u32 l = 0;
388 
389 	if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
390 		omap_set_gpio_trigger(bank, gpio, trigger);
391 	} else if (bank->regs->irqctrl) {
392 		reg += bank->regs->irqctrl;
393 
394 		l = readl_relaxed(reg);
395 		if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
396 			bank->toggle_mask |= BIT(gpio);
397 		if (trigger & IRQ_TYPE_EDGE_RISING)
398 			l |= BIT(gpio);
399 		else if (trigger & IRQ_TYPE_EDGE_FALLING)
400 			l &= ~(BIT(gpio));
401 		else
402 			return -EINVAL;
403 
404 		writel_relaxed(l, reg);
405 	} else if (bank->regs->edgectrl1) {
406 		if (gpio & 0x08)
407 			reg += bank->regs->edgectrl2;
408 		else
409 			reg += bank->regs->edgectrl1;
410 
411 		gpio &= 0x07;
412 		l = readl_relaxed(reg);
413 		l &= ~(3 << (gpio << 1));
414 		if (trigger & IRQ_TYPE_EDGE_RISING)
415 			l |= 2 << (gpio << 1);
416 		if (trigger & IRQ_TYPE_EDGE_FALLING)
417 			l |= BIT(gpio << 1);
418 
419 		/* Enable wake-up during idle for dynamic tick */
420 		omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
421 		bank->context.wake_en =
422 			readl_relaxed(bank->base + bank->regs->wkup_en);
423 		writel_relaxed(l, reg);
424 	}
425 	return 0;
426 }
427 
428 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
429 {
430 	if (bank->regs->pinctrl) {
431 		void __iomem *reg = bank->base + bank->regs->pinctrl;
432 
433 		/* Claim the pin for MPU */
434 		writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
435 	}
436 
437 	if (bank->regs->ctrl && !BANK_USED(bank)) {
438 		void __iomem *reg = bank->base + bank->regs->ctrl;
439 		u32 ctrl;
440 
441 		ctrl = readl_relaxed(reg);
442 		/* Module is enabled, clocks are not gated */
443 		ctrl &= ~GPIO_MOD_CTRL_BIT;
444 		writel_relaxed(ctrl, reg);
445 		bank->context.ctrl = ctrl;
446 	}
447 }
448 
449 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
450 {
451 	void __iomem *base = bank->base;
452 
453 	if (bank->regs->wkup_en &&
454 	    !LINE_USED(bank->mod_usage, offset) &&
455 	    !LINE_USED(bank->irq_usage, offset)) {
456 		/* Disable wake-up during idle for dynamic tick */
457 		omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
458 		bank->context.wake_en =
459 			readl_relaxed(bank->base + bank->regs->wkup_en);
460 	}
461 
462 	if (bank->regs->ctrl && !BANK_USED(bank)) {
463 		void __iomem *reg = bank->base + bank->regs->ctrl;
464 		u32 ctrl;
465 
466 		ctrl = readl_relaxed(reg);
467 		/* Module is disabled, clocks are gated */
468 		ctrl |= GPIO_MOD_CTRL_BIT;
469 		writel_relaxed(ctrl, reg);
470 		bank->context.ctrl = ctrl;
471 	}
472 }
473 
474 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
475 {
476 	void __iomem *reg = bank->base + bank->regs->direction;
477 
478 	return readl_relaxed(reg) & BIT(offset);
479 }
480 
481 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
482 {
483 	if (!LINE_USED(bank->mod_usage, offset)) {
484 		omap_enable_gpio_module(bank, offset);
485 		omap_set_gpio_direction(bank, offset, 1);
486 	}
487 	bank->irq_usage |= BIT(offset);
488 }
489 
490 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
491 {
492 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
493 	int retval;
494 	unsigned long flags;
495 	unsigned offset = d->hwirq;
496 
497 	if (type & ~IRQ_TYPE_SENSE_MASK)
498 		return -EINVAL;
499 
500 	if (!bank->regs->leveldetect0 &&
501 		(type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
502 		return -EINVAL;
503 
504 	raw_spin_lock_irqsave(&bank->lock, flags);
505 	retval = omap_set_gpio_triggering(bank, offset, type);
506 	if (retval) {
507 		raw_spin_unlock_irqrestore(&bank->lock, flags);
508 		goto error;
509 	}
510 	omap_gpio_init_irq(bank, offset);
511 	if (!omap_gpio_is_input(bank, offset)) {
512 		raw_spin_unlock_irqrestore(&bank->lock, flags);
513 		retval = -EINVAL;
514 		goto error;
515 	}
516 	raw_spin_unlock_irqrestore(&bank->lock, flags);
517 
518 	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
519 		irq_set_handler_locked(d, handle_level_irq);
520 	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
521 		irq_set_handler_locked(d, handle_edge_irq);
522 
523 	return 0;
524 
525 error:
526 	return retval;
527 }
528 
529 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
530 {
531 	void __iomem *reg = bank->base;
532 
533 	reg += bank->regs->irqstatus;
534 	writel_relaxed(gpio_mask, reg);
535 
536 	/* Workaround for clearing DSP GPIO interrupts to allow retention */
537 	if (bank->regs->irqstatus2) {
538 		reg = bank->base + bank->regs->irqstatus2;
539 		writel_relaxed(gpio_mask, reg);
540 	}
541 
542 	/* Flush posted write for the irq status to avoid spurious interrupts */
543 	readl_relaxed(reg);
544 }
545 
546 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
547 					     unsigned offset)
548 {
549 	omap_clear_gpio_irqbank(bank, BIT(offset));
550 }
551 
552 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
553 {
554 	void __iomem *reg = bank->base;
555 	u32 l;
556 	u32 mask = (BIT(bank->width)) - 1;
557 
558 	reg += bank->regs->irqenable;
559 	l = readl_relaxed(reg);
560 	if (bank->regs->irqenable_inv)
561 		l = ~l;
562 	l &= mask;
563 	return l;
564 }
565 
566 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
567 {
568 	void __iomem *reg = bank->base;
569 	u32 l;
570 
571 	if (bank->regs->set_irqenable) {
572 		reg += bank->regs->set_irqenable;
573 		l = gpio_mask;
574 		bank->context.irqenable1 |= gpio_mask;
575 	} else {
576 		reg += bank->regs->irqenable;
577 		l = readl_relaxed(reg);
578 		if (bank->regs->irqenable_inv)
579 			l &= ~gpio_mask;
580 		else
581 			l |= gpio_mask;
582 		bank->context.irqenable1 = l;
583 	}
584 
585 	writel_relaxed(l, reg);
586 }
587 
588 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
589 {
590 	void __iomem *reg = bank->base;
591 	u32 l;
592 
593 	if (bank->regs->clr_irqenable) {
594 		reg += bank->regs->clr_irqenable;
595 		l = gpio_mask;
596 		bank->context.irqenable1 &= ~gpio_mask;
597 	} else {
598 		reg += bank->regs->irqenable;
599 		l = readl_relaxed(reg);
600 		if (bank->regs->irqenable_inv)
601 			l |= gpio_mask;
602 		else
603 			l &= ~gpio_mask;
604 		bank->context.irqenable1 = l;
605 	}
606 
607 	writel_relaxed(l, reg);
608 }
609 
610 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
611 					   unsigned offset, int enable)
612 {
613 	if (enable)
614 		omap_enable_gpio_irqbank(bank, BIT(offset));
615 	else
616 		omap_disable_gpio_irqbank(bank, BIT(offset));
617 }
618 
619 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
620 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
621 {
622 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
623 
624 	return irq_set_irq_wake(bank->irq, enable);
625 }
626 
627 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
628 {
629 	struct gpio_bank *bank = gpiochip_get_data(chip);
630 	unsigned long flags;
631 
632 	/*
633 	 * If this is the first gpio_request for the bank,
634 	 * enable the bank module.
635 	 */
636 	if (!BANK_USED(bank))
637 		pm_runtime_get_sync(chip->parent);
638 
639 	raw_spin_lock_irqsave(&bank->lock, flags);
640 	omap_enable_gpio_module(bank, offset);
641 	bank->mod_usage |= BIT(offset);
642 	raw_spin_unlock_irqrestore(&bank->lock, flags);
643 
644 	return 0;
645 }
646 
647 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
648 {
649 	struct gpio_bank *bank = gpiochip_get_data(chip);
650 	unsigned long flags;
651 
652 	raw_spin_lock_irqsave(&bank->lock, flags);
653 	bank->mod_usage &= ~(BIT(offset));
654 	if (!LINE_USED(bank->irq_usage, offset)) {
655 		omap_set_gpio_direction(bank, offset, 1);
656 		omap_clear_gpio_debounce(bank, offset);
657 	}
658 	omap_disable_gpio_module(bank, offset);
659 	raw_spin_unlock_irqrestore(&bank->lock, flags);
660 
661 	/*
662 	 * If this is the last gpio to be freed in the bank,
663 	 * disable the bank module.
664 	 */
665 	if (!BANK_USED(bank))
666 		pm_runtime_put(chip->parent);
667 }
668 
669 /*
670  * We need to unmask the GPIO bank interrupt as soon as possible to
671  * avoid missing GPIO interrupts for other lines in the bank.
672  * Then we need to mask-read-clear-unmask the triggered GPIO lines
673  * in the bank to avoid missing nested interrupts for a GPIO line.
674  * If we wait to unmask individual GPIO lines in the bank after the
675  * line's interrupt handler has been run, we may miss some nested
676  * interrupts.
677  */
678 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
679 {
680 	void __iomem *isr_reg = NULL;
681 	u32 isr;
682 	unsigned int bit;
683 	struct gpio_bank *bank = gpiobank;
684 	unsigned long wa_lock_flags;
685 	unsigned long lock_flags;
686 
687 	isr_reg = bank->base + bank->regs->irqstatus;
688 	if (WARN_ON(!isr_reg))
689 		goto exit;
690 
691 	pm_runtime_get_sync(bank->chip.parent);
692 
693 	while (1) {
694 		u32 isr_saved, level_mask = 0;
695 		u32 enabled;
696 
697 		raw_spin_lock_irqsave(&bank->lock, lock_flags);
698 
699 		enabled = omap_get_gpio_irqbank_mask(bank);
700 		isr_saved = isr = readl_relaxed(isr_reg) & enabled;
701 
702 		if (bank->level_mask)
703 			level_mask = bank->level_mask & enabled;
704 
705 		/* clear edge sensitive interrupts before handler(s) are
706 		called so that we don't miss any interrupt occurred while
707 		executing them */
708 		omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
709 		omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
710 		omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
711 
712 		raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
713 
714 		if (!isr)
715 			break;
716 
717 		while (isr) {
718 			bit = __ffs(isr);
719 			isr &= ~(BIT(bit));
720 
721 			raw_spin_lock_irqsave(&bank->lock, lock_flags);
722 			/*
723 			 * Some chips can't respond to both rising and falling
724 			 * at the same time.  If this irq was requested with
725 			 * both flags, we need to flip the ICR data for the IRQ
726 			 * to respond to the IRQ for the opposite direction.
727 			 * This will be indicated in the bank toggle_mask.
728 			 */
729 			if (bank->toggle_mask & (BIT(bit)))
730 				omap_toggle_gpio_edge_triggering(bank, bit);
731 
732 			raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
733 
734 			raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
735 
736 			generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
737 							    bit));
738 
739 			raw_spin_unlock_irqrestore(&bank->wa_lock,
740 						   wa_lock_flags);
741 		}
742 	}
743 exit:
744 	pm_runtime_put(bank->chip.parent);
745 	return IRQ_HANDLED;
746 }
747 
748 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
749 {
750 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
751 	unsigned long flags;
752 	unsigned offset = d->hwirq;
753 
754 	raw_spin_lock_irqsave(&bank->lock, flags);
755 
756 	if (!LINE_USED(bank->mod_usage, offset))
757 		omap_set_gpio_direction(bank, offset, 1);
758 	else if (!omap_gpio_is_input(bank, offset))
759 		goto err;
760 	omap_enable_gpio_module(bank, offset);
761 	bank->irq_usage |= BIT(offset);
762 
763 	raw_spin_unlock_irqrestore(&bank->lock, flags);
764 	omap_gpio_unmask_irq(d);
765 
766 	return 0;
767 err:
768 	raw_spin_unlock_irqrestore(&bank->lock, flags);
769 	return -EINVAL;
770 }
771 
772 static void omap_gpio_irq_shutdown(struct irq_data *d)
773 {
774 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
775 	unsigned long flags;
776 	unsigned offset = d->hwirq;
777 
778 	raw_spin_lock_irqsave(&bank->lock, flags);
779 	bank->irq_usage &= ~(BIT(offset));
780 	omap_set_gpio_irqenable(bank, offset, 0);
781 	omap_clear_gpio_irqstatus(bank, offset);
782 	omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
783 	if (!LINE_USED(bank->mod_usage, offset))
784 		omap_clear_gpio_debounce(bank, offset);
785 	omap_disable_gpio_module(bank, offset);
786 	raw_spin_unlock_irqrestore(&bank->lock, flags);
787 }
788 
789 static void omap_gpio_irq_bus_lock(struct irq_data *data)
790 {
791 	struct gpio_bank *bank = omap_irq_data_get_bank(data);
792 
793 	if (!BANK_USED(bank))
794 		pm_runtime_get_sync(bank->chip.parent);
795 }
796 
797 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
798 {
799 	struct gpio_bank *bank = omap_irq_data_get_bank(data);
800 
801 	/*
802 	 * If this is the last IRQ to be freed in the bank,
803 	 * disable the bank module.
804 	 */
805 	if (!BANK_USED(bank))
806 		pm_runtime_put(bank->chip.parent);
807 }
808 
809 static void omap_gpio_ack_irq(struct irq_data *d)
810 {
811 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
812 	unsigned offset = d->hwirq;
813 
814 	omap_clear_gpio_irqstatus(bank, offset);
815 }
816 
817 static void omap_gpio_mask_irq(struct irq_data *d)
818 {
819 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
820 	unsigned offset = d->hwirq;
821 	unsigned long flags;
822 
823 	raw_spin_lock_irqsave(&bank->lock, flags);
824 	omap_set_gpio_irqenable(bank, offset, 0);
825 	omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
826 	raw_spin_unlock_irqrestore(&bank->lock, flags);
827 }
828 
829 static void omap_gpio_unmask_irq(struct irq_data *d)
830 {
831 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
832 	unsigned offset = d->hwirq;
833 	u32 trigger = irqd_get_trigger_type(d);
834 	unsigned long flags;
835 
836 	raw_spin_lock_irqsave(&bank->lock, flags);
837 	if (trigger)
838 		omap_set_gpio_triggering(bank, offset, trigger);
839 
840 	/* For level-triggered GPIOs, the clearing must be done after
841 	 * the HW source is cleared, thus after the handler has run */
842 	if (bank->level_mask & BIT(offset)) {
843 		omap_set_gpio_irqenable(bank, offset, 0);
844 		omap_clear_gpio_irqstatus(bank, offset);
845 	}
846 
847 	omap_set_gpio_irqenable(bank, offset, 1);
848 	raw_spin_unlock_irqrestore(&bank->lock, flags);
849 }
850 
851 /*---------------------------------------------------------------------*/
852 
853 static int omap_mpuio_suspend_noirq(struct device *dev)
854 {
855 	struct platform_device *pdev = to_platform_device(dev);
856 	struct gpio_bank	*bank = platform_get_drvdata(pdev);
857 	void __iomem		*mask_reg = bank->base +
858 					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
859 	unsigned long		flags;
860 
861 	raw_spin_lock_irqsave(&bank->lock, flags);
862 	writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
863 	raw_spin_unlock_irqrestore(&bank->lock, flags);
864 
865 	return 0;
866 }
867 
868 static int omap_mpuio_resume_noirq(struct device *dev)
869 {
870 	struct platform_device *pdev = to_platform_device(dev);
871 	struct gpio_bank	*bank = platform_get_drvdata(pdev);
872 	void __iomem		*mask_reg = bank->base +
873 					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
874 	unsigned long		flags;
875 
876 	raw_spin_lock_irqsave(&bank->lock, flags);
877 	writel_relaxed(bank->context.wake_en, mask_reg);
878 	raw_spin_unlock_irqrestore(&bank->lock, flags);
879 
880 	return 0;
881 }
882 
883 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
884 	.suspend_noirq = omap_mpuio_suspend_noirq,
885 	.resume_noirq = omap_mpuio_resume_noirq,
886 };
887 
888 /* use platform_driver for this. */
889 static struct platform_driver omap_mpuio_driver = {
890 	.driver		= {
891 		.name	= "mpuio",
892 		.pm	= &omap_mpuio_dev_pm_ops,
893 	},
894 };
895 
896 static struct platform_device omap_mpuio_device = {
897 	.name		= "mpuio",
898 	.id		= -1,
899 	.dev = {
900 		.driver = &omap_mpuio_driver.driver,
901 	}
902 	/* could list the /proc/iomem resources */
903 };
904 
905 static inline void omap_mpuio_init(struct gpio_bank *bank)
906 {
907 	platform_set_drvdata(&omap_mpuio_device, bank);
908 
909 	if (platform_driver_register(&omap_mpuio_driver) == 0)
910 		(void) platform_device_register(&omap_mpuio_device);
911 }
912 
913 /*---------------------------------------------------------------------*/
914 
915 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
916 {
917 	struct gpio_bank *bank;
918 	unsigned long flags;
919 	void __iomem *reg;
920 	int dir;
921 
922 	bank = gpiochip_get_data(chip);
923 	reg = bank->base + bank->regs->direction;
924 	raw_spin_lock_irqsave(&bank->lock, flags);
925 	dir = !!(readl_relaxed(reg) & BIT(offset));
926 	raw_spin_unlock_irqrestore(&bank->lock, flags);
927 	return dir;
928 }
929 
930 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
931 {
932 	struct gpio_bank *bank;
933 	unsigned long flags;
934 
935 	bank = gpiochip_get_data(chip);
936 	raw_spin_lock_irqsave(&bank->lock, flags);
937 	omap_set_gpio_direction(bank, offset, 1);
938 	raw_spin_unlock_irqrestore(&bank->lock, flags);
939 	return 0;
940 }
941 
942 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
943 {
944 	struct gpio_bank *bank;
945 
946 	bank = gpiochip_get_data(chip);
947 
948 	if (omap_gpio_is_input(bank, offset))
949 		return omap_get_gpio_datain(bank, offset);
950 	else
951 		return omap_get_gpio_dataout(bank, offset);
952 }
953 
954 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
955 {
956 	struct gpio_bank *bank;
957 	unsigned long flags;
958 
959 	bank = gpiochip_get_data(chip);
960 	raw_spin_lock_irqsave(&bank->lock, flags);
961 	bank->set_dataout(bank, offset, value);
962 	omap_set_gpio_direction(bank, offset, 0);
963 	raw_spin_unlock_irqrestore(&bank->lock, flags);
964 	return 0;
965 }
966 
967 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
968 			      unsigned debounce)
969 {
970 	struct gpio_bank *bank;
971 	unsigned long flags;
972 	int ret;
973 
974 	bank = gpiochip_get_data(chip);
975 
976 	raw_spin_lock_irqsave(&bank->lock, flags);
977 	ret = omap2_set_gpio_debounce(bank, offset, debounce);
978 	raw_spin_unlock_irqrestore(&bank->lock, flags);
979 
980 	if (ret)
981 		dev_info(chip->parent,
982 			 "Could not set line %u debounce to %u microseconds (%d)",
983 			 offset, debounce, ret);
984 
985 	return ret;
986 }
987 
988 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
989 				unsigned long config)
990 {
991 	u32 debounce;
992 
993 	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
994 		return -ENOTSUPP;
995 
996 	debounce = pinconf_to_config_argument(config);
997 	return omap_gpio_debounce(chip, offset, debounce);
998 }
999 
1000 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1001 {
1002 	struct gpio_bank *bank;
1003 	unsigned long flags;
1004 
1005 	bank = gpiochip_get_data(chip);
1006 	raw_spin_lock_irqsave(&bank->lock, flags);
1007 	bank->set_dataout(bank, offset, value);
1008 	raw_spin_unlock_irqrestore(&bank->lock, flags);
1009 }
1010 
1011 /*---------------------------------------------------------------------*/
1012 
1013 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1014 {
1015 	static bool called;
1016 	u32 rev;
1017 
1018 	if (called || bank->regs->revision == USHRT_MAX)
1019 		return;
1020 
1021 	rev = readw_relaxed(bank->base + bank->regs->revision);
1022 	pr_info("OMAP GPIO hardware version %d.%d\n",
1023 		(rev >> 4) & 0x0f, rev & 0x0f);
1024 
1025 	called = true;
1026 }
1027 
1028 static void omap_gpio_mod_init(struct gpio_bank *bank)
1029 {
1030 	void __iomem *base = bank->base;
1031 	u32 l = 0xffffffff;
1032 
1033 	if (bank->width == 16)
1034 		l = 0xffff;
1035 
1036 	if (bank->is_mpuio) {
1037 		writel_relaxed(l, bank->base + bank->regs->irqenable);
1038 		return;
1039 	}
1040 
1041 	omap_gpio_rmw(base, bank->regs->irqenable, l,
1042 		      bank->regs->irqenable_inv);
1043 	omap_gpio_rmw(base, bank->regs->irqstatus, l,
1044 		      !bank->regs->irqenable_inv);
1045 	if (bank->regs->debounce_en)
1046 		writel_relaxed(0, base + bank->regs->debounce_en);
1047 
1048 	/* Save OE default value (0xffffffff) in the context */
1049 	bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1050 	 /* Initialize interface clk ungated, module enabled */
1051 	if (bank->regs->ctrl)
1052 		writel_relaxed(0, base + bank->regs->ctrl);
1053 }
1054 
1055 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1056 {
1057 	static int gpio;
1058 	int irq_base = 0;
1059 	int ret;
1060 
1061 	/*
1062 	 * REVISIT eventually switch from OMAP-specific gpio structs
1063 	 * over to the generic ones
1064 	 */
1065 	bank->chip.request = omap_gpio_request;
1066 	bank->chip.free = omap_gpio_free;
1067 	bank->chip.get_direction = omap_gpio_get_direction;
1068 	bank->chip.direction_input = omap_gpio_input;
1069 	bank->chip.get = omap_gpio_get;
1070 	bank->chip.direction_output = omap_gpio_output;
1071 	bank->chip.set_config = omap_gpio_set_config;
1072 	bank->chip.set = omap_gpio_set;
1073 	if (bank->is_mpuio) {
1074 		bank->chip.label = "mpuio";
1075 		if (bank->regs->wkup_en)
1076 			bank->chip.parent = &omap_mpuio_device.dev;
1077 		bank->chip.base = OMAP_MPUIO(0);
1078 	} else {
1079 		bank->chip.label = "gpio";
1080 		bank->chip.base = gpio;
1081 	}
1082 	bank->chip.ngpio = bank->width;
1083 
1084 	ret = gpiochip_add_data(&bank->chip, bank);
1085 	if (ret) {
1086 		dev_err(bank->chip.parent,
1087 			"Could not register gpio chip %d\n", ret);
1088 		return ret;
1089 	}
1090 
1091 	if (!bank->is_mpuio)
1092 		gpio += bank->width;
1093 
1094 #ifdef CONFIG_ARCH_OMAP1
1095 	/*
1096 	 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1097 	 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1098 	 */
1099 	irq_base = devm_irq_alloc_descs(bank->chip.parent,
1100 					-1, 0, bank->width, 0);
1101 	if (irq_base < 0) {
1102 		dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1103 		return -ENODEV;
1104 	}
1105 #endif
1106 
1107 	/* MPUIO is a bit different, reading IRQ status clears it */
1108 	if (bank->is_mpuio) {
1109 		irqc->irq_ack = dummy_irq_chip.irq_ack;
1110 		if (!bank->regs->wkup_en)
1111 			irqc->irq_set_wake = NULL;
1112 	}
1113 
1114 	ret = gpiochip_irqchip_add(&bank->chip, irqc,
1115 				   irq_base, handle_bad_irq,
1116 				   IRQ_TYPE_NONE);
1117 
1118 	if (ret) {
1119 		dev_err(bank->chip.parent,
1120 			"Couldn't add irqchip to gpiochip %d\n", ret);
1121 		gpiochip_remove(&bank->chip);
1122 		return -ENODEV;
1123 	}
1124 
1125 	gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL);
1126 
1127 	ret = devm_request_irq(bank->chip.parent, bank->irq,
1128 			       omap_gpio_irq_handler,
1129 			       0, dev_name(bank->chip.parent), bank);
1130 	if (ret)
1131 		gpiochip_remove(&bank->chip);
1132 
1133 	return ret;
1134 }
1135 
1136 static const struct of_device_id omap_gpio_match[];
1137 
1138 static int omap_gpio_probe(struct platform_device *pdev)
1139 {
1140 	struct device *dev = &pdev->dev;
1141 	struct device_node *node = dev->of_node;
1142 	const struct of_device_id *match;
1143 	const struct omap_gpio_platform_data *pdata;
1144 	struct resource *res;
1145 	struct gpio_bank *bank;
1146 	struct irq_chip *irqc;
1147 	int ret;
1148 
1149 	match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1150 
1151 	pdata = match ? match->data : dev_get_platdata(dev);
1152 	if (!pdata)
1153 		return -EINVAL;
1154 
1155 	bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1156 	if (!bank) {
1157 		dev_err(dev, "Memory alloc failed\n");
1158 		return -ENOMEM;
1159 	}
1160 
1161 	irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1162 	if (!irqc)
1163 		return -ENOMEM;
1164 
1165 	irqc->irq_startup = omap_gpio_irq_startup,
1166 	irqc->irq_shutdown = omap_gpio_irq_shutdown,
1167 	irqc->irq_ack = omap_gpio_ack_irq,
1168 	irqc->irq_mask = omap_gpio_mask_irq,
1169 	irqc->irq_unmask = omap_gpio_unmask_irq,
1170 	irqc->irq_set_type = omap_gpio_irq_type,
1171 	irqc->irq_set_wake = omap_gpio_wake_enable,
1172 	irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1173 	irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1174 	irqc->name = dev_name(&pdev->dev);
1175 	irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1176 
1177 	bank->irq = platform_get_irq(pdev, 0);
1178 	if (bank->irq <= 0) {
1179 		if (!bank->irq)
1180 			bank->irq = -ENXIO;
1181 		if (bank->irq != -EPROBE_DEFER)
1182 			dev_err(dev,
1183 				"can't get irq resource ret=%d\n", bank->irq);
1184 		return bank->irq;
1185 	}
1186 
1187 	bank->chip.parent = dev;
1188 	bank->chip.owner = THIS_MODULE;
1189 	bank->dbck_flag = pdata->dbck_flag;
1190 	bank->stride = pdata->bank_stride;
1191 	bank->width = pdata->bank_width;
1192 	bank->is_mpuio = pdata->is_mpuio;
1193 	bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1194 	bank->regs = pdata->regs;
1195 #ifdef CONFIG_OF_GPIO
1196 	bank->chip.of_node = of_node_get(node);
1197 #endif
1198 	if (node) {
1199 		if (!of_property_read_bool(node, "ti,gpio-always-on"))
1200 			bank->loses_context = true;
1201 	} else {
1202 		bank->loses_context = pdata->loses_context;
1203 
1204 		if (bank->loses_context)
1205 			bank->get_context_loss_count =
1206 				pdata->get_context_loss_count;
1207 	}
1208 
1209 	if (bank->regs->set_dataout && bank->regs->clr_dataout)
1210 		bank->set_dataout = omap_set_gpio_dataout_reg;
1211 	else
1212 		bank->set_dataout = omap_set_gpio_dataout_mask;
1213 
1214 	raw_spin_lock_init(&bank->lock);
1215 	raw_spin_lock_init(&bank->wa_lock);
1216 
1217 	/* Static mapping, never released */
1218 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1219 	bank->base = devm_ioremap_resource(dev, res);
1220 	if (IS_ERR(bank->base)) {
1221 		return PTR_ERR(bank->base);
1222 	}
1223 
1224 	if (bank->dbck_flag) {
1225 		bank->dbck = devm_clk_get(dev, "dbclk");
1226 		if (IS_ERR(bank->dbck)) {
1227 			dev_err(dev,
1228 				"Could not get gpio dbck. Disable debounce\n");
1229 			bank->dbck_flag = false;
1230 		} else {
1231 			clk_prepare(bank->dbck);
1232 		}
1233 	}
1234 
1235 	platform_set_drvdata(pdev, bank);
1236 
1237 	pm_runtime_enable(dev);
1238 	pm_runtime_irq_safe(dev);
1239 	pm_runtime_get_sync(dev);
1240 
1241 	if (bank->is_mpuio)
1242 		omap_mpuio_init(bank);
1243 
1244 	omap_gpio_mod_init(bank);
1245 
1246 	ret = omap_gpio_chip_init(bank, irqc);
1247 	if (ret) {
1248 		pm_runtime_put_sync(dev);
1249 		pm_runtime_disable(dev);
1250 		return ret;
1251 	}
1252 
1253 	omap_gpio_show_rev(bank);
1254 
1255 	pm_runtime_put(dev);
1256 
1257 	list_add_tail(&bank->node, &omap_gpio_list);
1258 
1259 	return 0;
1260 }
1261 
1262 static int omap_gpio_remove(struct platform_device *pdev)
1263 {
1264 	struct gpio_bank *bank = platform_get_drvdata(pdev);
1265 
1266 	list_del(&bank->node);
1267 	gpiochip_remove(&bank->chip);
1268 	pm_runtime_disable(&pdev->dev);
1269 	if (bank->dbck_flag)
1270 		clk_unprepare(bank->dbck);
1271 
1272 	return 0;
1273 }
1274 
1275 #ifdef CONFIG_ARCH_OMAP2PLUS
1276 
1277 #if defined(CONFIG_PM)
1278 static void omap_gpio_restore_context(struct gpio_bank *bank);
1279 
1280 static int omap_gpio_runtime_suspend(struct device *dev)
1281 {
1282 	struct platform_device *pdev = to_platform_device(dev);
1283 	struct gpio_bank *bank = platform_get_drvdata(pdev);
1284 	u32 l1 = 0, l2 = 0;
1285 	unsigned long flags;
1286 	u32 wake_low, wake_hi;
1287 
1288 	raw_spin_lock_irqsave(&bank->lock, flags);
1289 
1290 	/*
1291 	 * Only edges can generate a wakeup event to the PRCM.
1292 	 *
1293 	 * Therefore, ensure any wake-up capable GPIOs have
1294 	 * edge-detection enabled before going idle to ensure a wakeup
1295 	 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1296 	 * NDA TRM 25.5.3.1)
1297 	 *
1298 	 * The normal values will be restored upon ->runtime_resume()
1299 	 * by writing back the values saved in bank->context.
1300 	 */
1301 	wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1302 	if (wake_low)
1303 		writel_relaxed(wake_low | bank->context.fallingdetect,
1304 			     bank->base + bank->regs->fallingdetect);
1305 	wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1306 	if (wake_hi)
1307 		writel_relaxed(wake_hi | bank->context.risingdetect,
1308 			     bank->base + bank->regs->risingdetect);
1309 
1310 	if (!bank->enabled_non_wakeup_gpios)
1311 		goto update_gpio_context_count;
1312 
1313 	if (bank->power_mode != OFF_MODE) {
1314 		bank->power_mode = 0;
1315 		goto update_gpio_context_count;
1316 	}
1317 	/*
1318 	 * If going to OFF, remove triggering for all
1319 	 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
1320 	 * generated.  See OMAP2420 Errata item 1.101.
1321 	 */
1322 	bank->saved_datain = readl_relaxed(bank->base +
1323 						bank->regs->datain);
1324 	l1 = bank->context.fallingdetect;
1325 	l2 = bank->context.risingdetect;
1326 
1327 	l1 &= ~bank->enabled_non_wakeup_gpios;
1328 	l2 &= ~bank->enabled_non_wakeup_gpios;
1329 
1330 	writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1331 	writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1332 
1333 	bank->workaround_enabled = true;
1334 
1335 update_gpio_context_count:
1336 	if (bank->get_context_loss_count)
1337 		bank->context_loss_count =
1338 				bank->get_context_loss_count(dev);
1339 
1340 	omap_gpio_dbck_disable(bank);
1341 	raw_spin_unlock_irqrestore(&bank->lock, flags);
1342 
1343 	return 0;
1344 }
1345 
1346 static void omap_gpio_init_context(struct gpio_bank *p);
1347 
1348 static int omap_gpio_runtime_resume(struct device *dev)
1349 {
1350 	struct platform_device *pdev = to_platform_device(dev);
1351 	struct gpio_bank *bank = platform_get_drvdata(pdev);
1352 	u32 l = 0, gen, gen0, gen1;
1353 	unsigned long flags;
1354 	int c;
1355 
1356 	raw_spin_lock_irqsave(&bank->lock, flags);
1357 
1358 	/*
1359 	 * On the first resume during the probe, the context has not
1360 	 * been initialised and so initialise it now. Also initialise
1361 	 * the context loss count.
1362 	 */
1363 	if (bank->loses_context && !bank->context_valid) {
1364 		omap_gpio_init_context(bank);
1365 
1366 		if (bank->get_context_loss_count)
1367 			bank->context_loss_count =
1368 				bank->get_context_loss_count(dev);
1369 	}
1370 
1371 	omap_gpio_dbck_enable(bank);
1372 
1373 	/*
1374 	 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1375 	 * GPIOs were set to edge trigger also in order to be able to
1376 	 * generate a PRCM wakeup.  Here we restore the
1377 	 * pre-runtime_suspend() values for edge triggering.
1378 	 */
1379 	writel_relaxed(bank->context.fallingdetect,
1380 		     bank->base + bank->regs->fallingdetect);
1381 	writel_relaxed(bank->context.risingdetect,
1382 		     bank->base + bank->regs->risingdetect);
1383 
1384 	if (bank->loses_context) {
1385 		if (!bank->get_context_loss_count) {
1386 			omap_gpio_restore_context(bank);
1387 		} else {
1388 			c = bank->get_context_loss_count(dev);
1389 			if (c != bank->context_loss_count) {
1390 				omap_gpio_restore_context(bank);
1391 			} else {
1392 				raw_spin_unlock_irqrestore(&bank->lock, flags);
1393 				return 0;
1394 			}
1395 		}
1396 	}
1397 
1398 	if (!bank->workaround_enabled) {
1399 		raw_spin_unlock_irqrestore(&bank->lock, flags);
1400 		return 0;
1401 	}
1402 
1403 	l = readl_relaxed(bank->base + bank->regs->datain);
1404 
1405 	/*
1406 	 * Check if any of the non-wakeup interrupt GPIOs have changed
1407 	 * state.  If so, generate an IRQ by software.  This is
1408 	 * horribly racy, but it's the best we can do to work around
1409 	 * this silicon bug.
1410 	 */
1411 	l ^= bank->saved_datain;
1412 	l &= bank->enabled_non_wakeup_gpios;
1413 
1414 	/*
1415 	 * No need to generate IRQs for the rising edge for gpio IRQs
1416 	 * configured with falling edge only; and vice versa.
1417 	 */
1418 	gen0 = l & bank->context.fallingdetect;
1419 	gen0 &= bank->saved_datain;
1420 
1421 	gen1 = l & bank->context.risingdetect;
1422 	gen1 &= ~(bank->saved_datain);
1423 
1424 	/* FIXME: Consider GPIO IRQs with level detections properly! */
1425 	gen = l & (~(bank->context.fallingdetect) &
1426 					 ~(bank->context.risingdetect));
1427 	/* Consider all GPIO IRQs needed to be updated */
1428 	gen |= gen0 | gen1;
1429 
1430 	if (gen) {
1431 		u32 old0, old1;
1432 
1433 		old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1434 		old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1435 
1436 		if (!bank->regs->irqstatus_raw0) {
1437 			writel_relaxed(old0 | gen, bank->base +
1438 						bank->regs->leveldetect0);
1439 			writel_relaxed(old1 | gen, bank->base +
1440 						bank->regs->leveldetect1);
1441 		}
1442 
1443 		if (bank->regs->irqstatus_raw0) {
1444 			writel_relaxed(old0 | l, bank->base +
1445 						bank->regs->leveldetect0);
1446 			writel_relaxed(old1 | l, bank->base +
1447 						bank->regs->leveldetect1);
1448 		}
1449 		writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1450 		writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1451 	}
1452 
1453 	bank->workaround_enabled = false;
1454 	raw_spin_unlock_irqrestore(&bank->lock, flags);
1455 
1456 	return 0;
1457 }
1458 #endif /* CONFIG_PM */
1459 
1460 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
1461 void omap2_gpio_prepare_for_idle(int pwr_mode)
1462 {
1463 	struct gpio_bank *bank;
1464 
1465 	list_for_each_entry(bank, &omap_gpio_list, node) {
1466 		if (!BANK_USED(bank) || !bank->loses_context)
1467 			continue;
1468 
1469 		bank->power_mode = pwr_mode;
1470 
1471 		pm_runtime_put_sync_suspend(bank->chip.parent);
1472 	}
1473 }
1474 
1475 void omap2_gpio_resume_after_idle(void)
1476 {
1477 	struct gpio_bank *bank;
1478 
1479 	list_for_each_entry(bank, &omap_gpio_list, node) {
1480 		if (!BANK_USED(bank) || !bank->loses_context)
1481 			continue;
1482 
1483 		pm_runtime_get_sync(bank->chip.parent);
1484 	}
1485 }
1486 #endif
1487 
1488 #if defined(CONFIG_PM)
1489 static void omap_gpio_init_context(struct gpio_bank *p)
1490 {
1491 	struct omap_gpio_reg_offs *regs = p->regs;
1492 	void __iomem *base = p->base;
1493 
1494 	p->context.ctrl		= readl_relaxed(base + regs->ctrl);
1495 	p->context.oe		= readl_relaxed(base + regs->direction);
1496 	p->context.wake_en	= readl_relaxed(base + regs->wkup_en);
1497 	p->context.leveldetect0	= readl_relaxed(base + regs->leveldetect0);
1498 	p->context.leveldetect1	= readl_relaxed(base + regs->leveldetect1);
1499 	p->context.risingdetect	= readl_relaxed(base + regs->risingdetect);
1500 	p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1501 	p->context.irqenable1	= readl_relaxed(base + regs->irqenable);
1502 	p->context.irqenable2	= readl_relaxed(base + regs->irqenable2);
1503 
1504 	if (regs->set_dataout && p->regs->clr_dataout)
1505 		p->context.dataout = readl_relaxed(base + regs->set_dataout);
1506 	else
1507 		p->context.dataout = readl_relaxed(base + regs->dataout);
1508 
1509 	p->context_valid = true;
1510 }
1511 
1512 static void omap_gpio_restore_context(struct gpio_bank *bank)
1513 {
1514 	writel_relaxed(bank->context.wake_en,
1515 				bank->base + bank->regs->wkup_en);
1516 	writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1517 	writel_relaxed(bank->context.leveldetect0,
1518 				bank->base + bank->regs->leveldetect0);
1519 	writel_relaxed(bank->context.leveldetect1,
1520 				bank->base + bank->regs->leveldetect1);
1521 	writel_relaxed(bank->context.risingdetect,
1522 				bank->base + bank->regs->risingdetect);
1523 	writel_relaxed(bank->context.fallingdetect,
1524 				bank->base + bank->regs->fallingdetect);
1525 	if (bank->regs->set_dataout && bank->regs->clr_dataout)
1526 		writel_relaxed(bank->context.dataout,
1527 				bank->base + bank->regs->set_dataout);
1528 	else
1529 		writel_relaxed(bank->context.dataout,
1530 				bank->base + bank->regs->dataout);
1531 	writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1532 
1533 	if (bank->dbck_enable_mask) {
1534 		writel_relaxed(bank->context.debounce, bank->base +
1535 					bank->regs->debounce);
1536 		writel_relaxed(bank->context.debounce_en,
1537 					bank->base + bank->regs->debounce_en);
1538 	}
1539 
1540 	writel_relaxed(bank->context.irqenable1,
1541 				bank->base + bank->regs->irqenable);
1542 	writel_relaxed(bank->context.irqenable2,
1543 				bank->base + bank->regs->irqenable2);
1544 }
1545 #endif /* CONFIG_PM */
1546 #else
1547 #define omap_gpio_runtime_suspend NULL
1548 #define omap_gpio_runtime_resume NULL
1549 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1550 #endif
1551 
1552 static const struct dev_pm_ops gpio_pm_ops = {
1553 	SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1554 									NULL)
1555 };
1556 
1557 #if defined(CONFIG_OF)
1558 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1559 	.revision =		OMAP24XX_GPIO_REVISION,
1560 	.direction =		OMAP24XX_GPIO_OE,
1561 	.datain =		OMAP24XX_GPIO_DATAIN,
1562 	.dataout =		OMAP24XX_GPIO_DATAOUT,
1563 	.set_dataout =		OMAP24XX_GPIO_SETDATAOUT,
1564 	.clr_dataout =		OMAP24XX_GPIO_CLEARDATAOUT,
1565 	.irqstatus =		OMAP24XX_GPIO_IRQSTATUS1,
1566 	.irqstatus2 =		OMAP24XX_GPIO_IRQSTATUS2,
1567 	.irqenable =		OMAP24XX_GPIO_IRQENABLE1,
1568 	.irqenable2 =		OMAP24XX_GPIO_IRQENABLE2,
1569 	.set_irqenable =	OMAP24XX_GPIO_SETIRQENABLE1,
1570 	.clr_irqenable =	OMAP24XX_GPIO_CLEARIRQENABLE1,
1571 	.debounce =		OMAP24XX_GPIO_DEBOUNCE_VAL,
1572 	.debounce_en =		OMAP24XX_GPIO_DEBOUNCE_EN,
1573 	.ctrl =			OMAP24XX_GPIO_CTRL,
1574 	.wkup_en =		OMAP24XX_GPIO_WAKE_EN,
1575 	.leveldetect0 =		OMAP24XX_GPIO_LEVELDETECT0,
1576 	.leveldetect1 =		OMAP24XX_GPIO_LEVELDETECT1,
1577 	.risingdetect =		OMAP24XX_GPIO_RISINGDETECT,
1578 	.fallingdetect =	OMAP24XX_GPIO_FALLINGDETECT,
1579 };
1580 
1581 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1582 	.revision =		OMAP4_GPIO_REVISION,
1583 	.direction =		OMAP4_GPIO_OE,
1584 	.datain =		OMAP4_GPIO_DATAIN,
1585 	.dataout =		OMAP4_GPIO_DATAOUT,
1586 	.set_dataout =		OMAP4_GPIO_SETDATAOUT,
1587 	.clr_dataout =		OMAP4_GPIO_CLEARDATAOUT,
1588 	.irqstatus =		OMAP4_GPIO_IRQSTATUS0,
1589 	.irqstatus2 =		OMAP4_GPIO_IRQSTATUS1,
1590 	.irqenable =		OMAP4_GPIO_IRQSTATUSSET0,
1591 	.irqenable2 =		OMAP4_GPIO_IRQSTATUSSET1,
1592 	.set_irqenable =	OMAP4_GPIO_IRQSTATUSSET0,
1593 	.clr_irqenable =	OMAP4_GPIO_IRQSTATUSCLR0,
1594 	.debounce =		OMAP4_GPIO_DEBOUNCINGTIME,
1595 	.debounce_en =		OMAP4_GPIO_DEBOUNCENABLE,
1596 	.ctrl =			OMAP4_GPIO_CTRL,
1597 	.wkup_en =		OMAP4_GPIO_IRQWAKEN0,
1598 	.leveldetect0 =		OMAP4_GPIO_LEVELDETECT0,
1599 	.leveldetect1 =		OMAP4_GPIO_LEVELDETECT1,
1600 	.risingdetect =		OMAP4_GPIO_RISINGDETECT,
1601 	.fallingdetect =	OMAP4_GPIO_FALLINGDETECT,
1602 };
1603 
1604 static const struct omap_gpio_platform_data omap2_pdata = {
1605 	.regs = &omap2_gpio_regs,
1606 	.bank_width = 32,
1607 	.dbck_flag = false,
1608 };
1609 
1610 static const struct omap_gpio_platform_data omap3_pdata = {
1611 	.regs = &omap2_gpio_regs,
1612 	.bank_width = 32,
1613 	.dbck_flag = true,
1614 };
1615 
1616 static const struct omap_gpio_platform_data omap4_pdata = {
1617 	.regs = &omap4_gpio_regs,
1618 	.bank_width = 32,
1619 	.dbck_flag = true,
1620 };
1621 
1622 static const struct of_device_id omap_gpio_match[] = {
1623 	{
1624 		.compatible = "ti,omap4-gpio",
1625 		.data = &omap4_pdata,
1626 	},
1627 	{
1628 		.compatible = "ti,omap3-gpio",
1629 		.data = &omap3_pdata,
1630 	},
1631 	{
1632 		.compatible = "ti,omap2-gpio",
1633 		.data = &omap2_pdata,
1634 	},
1635 	{ },
1636 };
1637 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1638 #endif
1639 
1640 static struct platform_driver omap_gpio_driver = {
1641 	.probe		= omap_gpio_probe,
1642 	.remove		= omap_gpio_remove,
1643 	.driver		= {
1644 		.name	= "omap_gpio",
1645 		.pm	= &gpio_pm_ops,
1646 		.of_match_table = of_match_ptr(omap_gpio_match),
1647 	},
1648 };
1649 
1650 /*
1651  * gpio driver register needs to be done before
1652  * machine_init functions access gpio APIs.
1653  * Hence omap_gpio_drv_reg() is a postcore_initcall.
1654  */
1655 static int __init omap_gpio_drv_reg(void)
1656 {
1657 	return platform_driver_register(&omap_gpio_driver);
1658 }
1659 postcore_initcall(omap_gpio_drv_reg);
1660 
1661 static void __exit omap_gpio_exit(void)
1662 {
1663 	platform_driver_unregister(&omap_gpio_driver);
1664 }
1665 module_exit(omap_gpio_exit);
1666 
1667 MODULE_DESCRIPTION("omap gpio driver");
1668 MODULE_ALIAS("platform:gpio-omap");
1669 MODULE_LICENSE("GPL v2");
1670