xref: /openbmc/linux/drivers/gpio/gpio-omap.c (revision f35e839a) 
1 /*
2  * Support functions for OMAP GPIO
3  *
4  * Copyright (C) 2003-2005 Nokia Corporation
5  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6  *
7  * Copyright (C) 2009 Texas Instruments
8  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  */
14 
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/irqdomain.h>
28 #include <linux/irqchip/chained_irq.h>
29 #include <linux/gpio.h>
30 #include <linux/platform_data/gpio-omap.h>
31 
32 #define OFF_MODE	1
33 
34 static LIST_HEAD(omap_gpio_list);
35 
36 struct gpio_regs {
37 	u32 irqenable1;
38 	u32 irqenable2;
39 	u32 wake_en;
40 	u32 ctrl;
41 	u32 oe;
42 	u32 leveldetect0;
43 	u32 leveldetect1;
44 	u32 risingdetect;
45 	u32 fallingdetect;
46 	u32 dataout;
47 	u32 debounce;
48 	u32 debounce_en;
49 };
50 
51 struct gpio_bank {
52 	struct list_head node;
53 	void __iomem *base;
54 	u16 irq;
55 	struct irq_domain *domain;
56 	u32 non_wakeup_gpios;
57 	u32 enabled_non_wakeup_gpios;
58 	struct gpio_regs context;
59 	u32 saved_datain;
60 	u32 level_mask;
61 	u32 toggle_mask;
62 	spinlock_t lock;
63 	struct gpio_chip chip;
64 	struct clk *dbck;
65 	u32 mod_usage;
66 	u32 dbck_enable_mask;
67 	bool dbck_enabled;
68 	struct device *dev;
69 	bool is_mpuio;
70 	bool dbck_flag;
71 	bool loses_context;
72 	int stride;
73 	u32 width;
74 	int context_loss_count;
75 	int power_mode;
76 	bool workaround_enabled;
77 
78 	void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
79 	int (*get_context_loss_count)(struct device *dev);
80 
81 	struct omap_gpio_reg_offs *regs;
82 };
83 
84 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
85 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
86 #define GPIO_MOD_CTRL_BIT	BIT(0)
87 
88 static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
89 {
90 	return bank->chip.base + gpio_irq;
91 }
92 
93 static int omap_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
94 {
95 	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
96 
97 	return irq_find_mapping(bank->domain, offset);
98 }
99 
100 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
101 {
102 	void __iomem *reg = bank->base;
103 	u32 l;
104 
105 	reg += bank->regs->direction;
106 	l = __raw_readl(reg);
107 	if (is_input)
108 		l |= 1 << gpio;
109 	else
110 		l &= ~(1 << gpio);
111 	__raw_writel(l, reg);
112 	bank->context.oe = l;
113 }
114 
115 
116 /* set data out value using dedicate set/clear register */
117 static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
118 {
119 	void __iomem *reg = bank->base;
120 	u32 l = GPIO_BIT(bank, gpio);
121 
122 	if (enable) {
123 		reg += bank->regs->set_dataout;
124 		bank->context.dataout |= l;
125 	} else {
126 		reg += bank->regs->clr_dataout;
127 		bank->context.dataout &= ~l;
128 	}
129 
130 	__raw_writel(l, reg);
131 }
132 
133 /* set data out value using mask register */
134 static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
135 {
136 	void __iomem *reg = bank->base + bank->regs->dataout;
137 	u32 gpio_bit = GPIO_BIT(bank, gpio);
138 	u32 l;
139 
140 	l = __raw_readl(reg);
141 	if (enable)
142 		l |= gpio_bit;
143 	else
144 		l &= ~gpio_bit;
145 	__raw_writel(l, reg);
146 	bank->context.dataout = l;
147 }
148 
149 static int _get_gpio_datain(struct gpio_bank *bank, int offset)
150 {
151 	void __iomem *reg = bank->base + bank->regs->datain;
152 
153 	return (__raw_readl(reg) & (1 << offset)) != 0;
154 }
155 
156 static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
157 {
158 	void __iomem *reg = bank->base + bank->regs->dataout;
159 
160 	return (__raw_readl(reg) & (1 << offset)) != 0;
161 }
162 
163 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
164 {
165 	int l = __raw_readl(base + reg);
166 
167 	if (set)
168 		l |= mask;
169 	else
170 		l &= ~mask;
171 
172 	__raw_writel(l, base + reg);
173 }
174 
175 static inline void _gpio_dbck_enable(struct gpio_bank *bank)
176 {
177 	if (bank->dbck_enable_mask && !bank->dbck_enabled) {
178 		clk_enable(bank->dbck);
179 		bank->dbck_enabled = true;
180 
181 		__raw_writel(bank->dbck_enable_mask,
182 			     bank->base + bank->regs->debounce_en);
183 	}
184 }
185 
186 static inline void _gpio_dbck_disable(struct gpio_bank *bank)
187 {
188 	if (bank->dbck_enable_mask && bank->dbck_enabled) {
189 		/*
190 		 * Disable debounce before cutting it's clock. If debounce is
191 		 * enabled but the clock is not, GPIO module seems to be unable
192 		 * to detect events and generate interrupts at least on OMAP3.
193 		 */
194 		__raw_writel(0, bank->base + bank->regs->debounce_en);
195 
196 		clk_disable(bank->dbck);
197 		bank->dbck_enabled = false;
198 	}
199 }
200 
201 /**
202  * _set_gpio_debounce - low level gpio debounce time
203  * @bank: the gpio bank we're acting upon
204  * @gpio: the gpio number on this @gpio
205  * @debounce: debounce time to use
206  *
207  * OMAP's debounce time is in 31us steps so we need
208  * to convert and round up to the closest unit.
209  */
210 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
211 		unsigned debounce)
212 {
213 	void __iomem		*reg;
214 	u32			val;
215 	u32			l;
216 
217 	if (!bank->dbck_flag)
218 		return;
219 
220 	if (debounce < 32)
221 		debounce = 0x01;
222 	else if (debounce > 7936)
223 		debounce = 0xff;
224 	else
225 		debounce = (debounce / 0x1f) - 1;
226 
227 	l = GPIO_BIT(bank, gpio);
228 
229 	clk_enable(bank->dbck);
230 	reg = bank->base + bank->regs->debounce;
231 	__raw_writel(debounce, reg);
232 
233 	reg = bank->base + bank->regs->debounce_en;
234 	val = __raw_readl(reg);
235 
236 	if (debounce)
237 		val |= l;
238 	else
239 		val &= ~l;
240 	bank->dbck_enable_mask = val;
241 
242 	__raw_writel(val, reg);
243 	clk_disable(bank->dbck);
244 	/*
245 	 * Enable debounce clock per module.
246 	 * This call is mandatory because in omap_gpio_request() when
247 	 * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
248 	 * runtime callbck fails to turn on dbck because dbck_enable_mask
249 	 * used within _gpio_dbck_enable() is still not initialized at
250 	 * that point. Therefore we have to enable dbck here.
251 	 */
252 	_gpio_dbck_enable(bank);
253 	if (bank->dbck_enable_mask) {
254 		bank->context.debounce = debounce;
255 		bank->context.debounce_en = val;
256 	}
257 }
258 
259 /**
260  * _clear_gpio_debounce - clear debounce settings for a gpio
261  * @bank: the gpio bank we're acting upon
262  * @gpio: the gpio number on this @gpio
263  *
264  * If a gpio is using debounce, then clear the debounce enable bit and if
265  * this is the only gpio in this bank using debounce, then clear the debounce
266  * time too. The debounce clock will also be disabled when calling this function
267  * if this is the only gpio in the bank using debounce.
268  */
269 static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio)
270 {
271 	u32 gpio_bit = GPIO_BIT(bank, gpio);
272 
273 	if (!bank->dbck_flag)
274 		return;
275 
276 	if (!(bank->dbck_enable_mask & gpio_bit))
277 		return;
278 
279 	bank->dbck_enable_mask &= ~gpio_bit;
280 	bank->context.debounce_en &= ~gpio_bit;
281 	__raw_writel(bank->context.debounce_en,
282 		     bank->base + bank->regs->debounce_en);
283 
284 	if (!bank->dbck_enable_mask) {
285 		bank->context.debounce = 0;
286 		__raw_writel(bank->context.debounce, bank->base +
287 			     bank->regs->debounce);
288 		clk_disable(bank->dbck);
289 		bank->dbck_enabled = false;
290 	}
291 }
292 
293 static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
294 						unsigned trigger)
295 {
296 	void __iomem *base = bank->base;
297 	u32 gpio_bit = 1 << gpio;
298 
299 	_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
300 		  trigger & IRQ_TYPE_LEVEL_LOW);
301 	_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
302 		  trigger & IRQ_TYPE_LEVEL_HIGH);
303 	_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
304 		  trigger & IRQ_TYPE_EDGE_RISING);
305 	_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
306 		  trigger & IRQ_TYPE_EDGE_FALLING);
307 
308 	bank->context.leveldetect0 =
309 			__raw_readl(bank->base + bank->regs->leveldetect0);
310 	bank->context.leveldetect1 =
311 			__raw_readl(bank->base + bank->regs->leveldetect1);
312 	bank->context.risingdetect =
313 			__raw_readl(bank->base + bank->regs->risingdetect);
314 	bank->context.fallingdetect =
315 			__raw_readl(bank->base + bank->regs->fallingdetect);
316 
317 	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
318 		_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
319 		bank->context.wake_en =
320 			__raw_readl(bank->base + bank->regs->wkup_en);
321 	}
322 
323 	/* This part needs to be executed always for OMAP{34xx, 44xx} */
324 	if (!bank->regs->irqctrl) {
325 		/* On omap24xx proceed only when valid GPIO bit is set */
326 		if (bank->non_wakeup_gpios) {
327 			if (!(bank->non_wakeup_gpios & gpio_bit))
328 				goto exit;
329 		}
330 
331 		/*
332 		 * Log the edge gpio and manually trigger the IRQ
333 		 * after resume if the input level changes
334 		 * to avoid irq lost during PER RET/OFF mode
335 		 * Applies for omap2 non-wakeup gpio and all omap3 gpios
336 		 */
337 		if (trigger & IRQ_TYPE_EDGE_BOTH)
338 			bank->enabled_non_wakeup_gpios |= gpio_bit;
339 		else
340 			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
341 	}
342 
343 exit:
344 	bank->level_mask =
345 		__raw_readl(bank->base + bank->regs->leveldetect0) |
346 		__raw_readl(bank->base + bank->regs->leveldetect1);
347 }
348 
349 #ifdef CONFIG_ARCH_OMAP1
350 /*
351  * This only applies to chips that can't do both rising and falling edge
352  * detection at once.  For all other chips, this function is a noop.
353  */
354 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
355 {
356 	void __iomem *reg = bank->base;
357 	u32 l = 0;
358 
359 	if (!bank->regs->irqctrl)
360 		return;
361 
362 	reg += bank->regs->irqctrl;
363 
364 	l = __raw_readl(reg);
365 	if ((l >> gpio) & 1)
366 		l &= ~(1 << gpio);
367 	else
368 		l |= 1 << gpio;
369 
370 	__raw_writel(l, reg);
371 }
372 #else
373 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
374 #endif
375 
376 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
377 							unsigned trigger)
378 {
379 	void __iomem *reg = bank->base;
380 	void __iomem *base = bank->base;
381 	u32 l = 0;
382 
383 	if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
384 		set_gpio_trigger(bank, gpio, trigger);
385 	} else if (bank->regs->irqctrl) {
386 		reg += bank->regs->irqctrl;
387 
388 		l = __raw_readl(reg);
389 		if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
390 			bank->toggle_mask |= 1 << gpio;
391 		if (trigger & IRQ_TYPE_EDGE_RISING)
392 			l |= 1 << gpio;
393 		else if (trigger & IRQ_TYPE_EDGE_FALLING)
394 			l &= ~(1 << gpio);
395 		else
396 			return -EINVAL;
397 
398 		__raw_writel(l, reg);
399 	} else if (bank->regs->edgectrl1) {
400 		if (gpio & 0x08)
401 			reg += bank->regs->edgectrl2;
402 		else
403 			reg += bank->regs->edgectrl1;
404 
405 		gpio &= 0x07;
406 		l = __raw_readl(reg);
407 		l &= ~(3 << (gpio << 1));
408 		if (trigger & IRQ_TYPE_EDGE_RISING)
409 			l |= 2 << (gpio << 1);
410 		if (trigger & IRQ_TYPE_EDGE_FALLING)
411 			l |= 1 << (gpio << 1);
412 
413 		/* Enable wake-up during idle for dynamic tick */
414 		_gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
415 		bank->context.wake_en =
416 			__raw_readl(bank->base + bank->regs->wkup_en);
417 		__raw_writel(l, reg);
418 	}
419 	return 0;
420 }
421 
422 static int gpio_irq_type(struct irq_data *d, unsigned type)
423 {
424 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
425 	unsigned gpio = 0;
426 	int retval;
427 	unsigned long flags;
428 
429 	if (WARN_ON(!bank->mod_usage))
430 		return -EINVAL;
431 
432 #ifdef CONFIG_ARCH_OMAP1
433 	if (d->irq > IH_MPUIO_BASE)
434 		gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
435 #endif
436 
437 	if (!gpio)
438 		gpio = irq_to_gpio(bank, d->hwirq);
439 
440 	if (type & ~IRQ_TYPE_SENSE_MASK)
441 		return -EINVAL;
442 
443 	if (!bank->regs->leveldetect0 &&
444 		(type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
445 		return -EINVAL;
446 
447 	spin_lock_irqsave(&bank->lock, flags);
448 	retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
449 	spin_unlock_irqrestore(&bank->lock, flags);
450 
451 	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
452 		__irq_set_handler_locked(d->irq, handle_level_irq);
453 	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
454 		__irq_set_handler_locked(d->irq, handle_edge_irq);
455 
456 	return retval;
457 }
458 
459 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
460 {
461 	void __iomem *reg = bank->base;
462 
463 	reg += bank->regs->irqstatus;
464 	__raw_writel(gpio_mask, reg);
465 
466 	/* Workaround for clearing DSP GPIO interrupts to allow retention */
467 	if (bank->regs->irqstatus2) {
468 		reg = bank->base + bank->regs->irqstatus2;
469 		__raw_writel(gpio_mask, reg);
470 	}
471 
472 	/* Flush posted write for the irq status to avoid spurious interrupts */
473 	__raw_readl(reg);
474 }
475 
476 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
477 {
478 	_clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
479 }
480 
481 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
482 {
483 	void __iomem *reg = bank->base;
484 	u32 l;
485 	u32 mask = (1 << bank->width) - 1;
486 
487 	reg += bank->regs->irqenable;
488 	l = __raw_readl(reg);
489 	if (bank->regs->irqenable_inv)
490 		l = ~l;
491 	l &= mask;
492 	return l;
493 }
494 
495 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
496 {
497 	void __iomem *reg = bank->base;
498 	u32 l;
499 
500 	if (bank->regs->set_irqenable) {
501 		reg += bank->regs->set_irqenable;
502 		l = gpio_mask;
503 		bank->context.irqenable1 |= gpio_mask;
504 	} else {
505 		reg += bank->regs->irqenable;
506 		l = __raw_readl(reg);
507 		if (bank->regs->irqenable_inv)
508 			l &= ~gpio_mask;
509 		else
510 			l |= gpio_mask;
511 		bank->context.irqenable1 = l;
512 	}
513 
514 	__raw_writel(l, reg);
515 }
516 
517 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
518 {
519 	void __iomem *reg = bank->base;
520 	u32 l;
521 
522 	if (bank->regs->clr_irqenable) {
523 		reg += bank->regs->clr_irqenable;
524 		l = gpio_mask;
525 		bank->context.irqenable1 &= ~gpio_mask;
526 	} else {
527 		reg += bank->regs->irqenable;
528 		l = __raw_readl(reg);
529 		if (bank->regs->irqenable_inv)
530 			l |= gpio_mask;
531 		else
532 			l &= ~gpio_mask;
533 		bank->context.irqenable1 = l;
534 	}
535 
536 	__raw_writel(l, reg);
537 }
538 
539 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
540 {
541 	if (enable)
542 		_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
543 	else
544 		_disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
545 }
546 
547 /*
548  * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
549  * 1510 does not seem to have a wake-up register. If JTAG is connected
550  * to the target, system will wake up always on GPIO events. While
551  * system is running all registered GPIO interrupts need to have wake-up
552  * enabled. When system is suspended, only selected GPIO interrupts need
553  * to have wake-up enabled.
554  */
555 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
556 {
557 	u32 gpio_bit = GPIO_BIT(bank, gpio);
558 	unsigned long flags;
559 
560 	if (bank->non_wakeup_gpios & gpio_bit) {
561 		dev_err(bank->dev,
562 			"Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
563 		return -EINVAL;
564 	}
565 
566 	spin_lock_irqsave(&bank->lock, flags);
567 	if (enable)
568 		bank->context.wake_en |= gpio_bit;
569 	else
570 		bank->context.wake_en &= ~gpio_bit;
571 
572 	__raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
573 	spin_unlock_irqrestore(&bank->lock, flags);
574 
575 	return 0;
576 }
577 
578 static void _reset_gpio(struct gpio_bank *bank, int gpio)
579 {
580 	_set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
581 	_set_gpio_irqenable(bank, gpio, 0);
582 	_clear_gpio_irqstatus(bank, gpio);
583 	_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
584 	_clear_gpio_debounce(bank, gpio);
585 }
586 
587 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
588 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
589 {
590 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
591 	unsigned int gpio = irq_to_gpio(bank, d->hwirq);
592 
593 	return _set_gpio_wakeup(bank, gpio, enable);
594 }
595 
596 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
597 {
598 	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
599 	unsigned long flags;
600 
601 	/*
602 	 * If this is the first gpio_request for the bank,
603 	 * enable the bank module.
604 	 */
605 	if (!bank->mod_usage)
606 		pm_runtime_get_sync(bank->dev);
607 
608 	spin_lock_irqsave(&bank->lock, flags);
609 	/* Set trigger to none. You need to enable the desired trigger with
610 	 * request_irq() or set_irq_type().
611 	 */
612 	_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
613 
614 	if (bank->regs->pinctrl) {
615 		void __iomem *reg = bank->base + bank->regs->pinctrl;
616 
617 		/* Claim the pin for MPU */
618 		__raw_writel(__raw_readl(reg) | (1 << offset), reg);
619 	}
620 
621 	if (bank->regs->ctrl && !bank->mod_usage) {
622 		void __iomem *reg = bank->base + bank->regs->ctrl;
623 		u32 ctrl;
624 
625 		ctrl = __raw_readl(reg);
626 		/* Module is enabled, clocks are not gated */
627 		ctrl &= ~GPIO_MOD_CTRL_BIT;
628 		__raw_writel(ctrl, reg);
629 		bank->context.ctrl = ctrl;
630 	}
631 
632 	bank->mod_usage |= 1 << offset;
633 
634 	spin_unlock_irqrestore(&bank->lock, flags);
635 
636 	return 0;
637 }
638 
639 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
640 {
641 	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
642 	void __iomem *base = bank->base;
643 	unsigned long flags;
644 
645 	spin_lock_irqsave(&bank->lock, flags);
646 
647 	if (bank->regs->wkup_en) {
648 		/* Disable wake-up during idle for dynamic tick */
649 		_gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
650 		bank->context.wake_en =
651 			__raw_readl(bank->base + bank->regs->wkup_en);
652 	}
653 
654 	bank->mod_usage &= ~(1 << offset);
655 
656 	if (bank->regs->ctrl && !bank->mod_usage) {
657 		void __iomem *reg = bank->base + bank->regs->ctrl;
658 		u32 ctrl;
659 
660 		ctrl = __raw_readl(reg);
661 		/* Module is disabled, clocks are gated */
662 		ctrl |= GPIO_MOD_CTRL_BIT;
663 		__raw_writel(ctrl, reg);
664 		bank->context.ctrl = ctrl;
665 	}
666 
667 	_reset_gpio(bank, bank->chip.base + offset);
668 	spin_unlock_irqrestore(&bank->lock, flags);
669 
670 	/*
671 	 * If this is the last gpio to be freed in the bank,
672 	 * disable the bank module.
673 	 */
674 	if (!bank->mod_usage)
675 		pm_runtime_put(bank->dev);
676 }
677 
678 /*
679  * We need to unmask the GPIO bank interrupt as soon as possible to
680  * avoid missing GPIO interrupts for other lines in the bank.
681  * Then we need to mask-read-clear-unmask the triggered GPIO lines
682  * in the bank to avoid missing nested interrupts for a GPIO line.
683  * If we wait to unmask individual GPIO lines in the bank after the
684  * line's interrupt handler has been run, we may miss some nested
685  * interrupts.
686  */
687 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
688 {
689 	void __iomem *isr_reg = NULL;
690 	u32 isr;
691 	unsigned int bit;
692 	struct gpio_bank *bank;
693 	int unmasked = 0;
694 	struct irq_chip *chip = irq_desc_get_chip(desc);
695 
696 	chained_irq_enter(chip, desc);
697 
698 	bank = irq_get_handler_data(irq);
699 	isr_reg = bank->base + bank->regs->irqstatus;
700 	pm_runtime_get_sync(bank->dev);
701 
702 	if (WARN_ON(!isr_reg))
703 		goto exit;
704 
705 	while (1) {
706 		u32 isr_saved, level_mask = 0;
707 		u32 enabled;
708 
709 		enabled = _get_gpio_irqbank_mask(bank);
710 		isr_saved = isr = __raw_readl(isr_reg) & enabled;
711 
712 		if (bank->level_mask)
713 			level_mask = bank->level_mask & enabled;
714 
715 		/* clear edge sensitive interrupts before handler(s) are
716 		called so that we don't miss any interrupt occurred while
717 		executing them */
718 		_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
719 		_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
720 		_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
721 
722 		/* if there is only edge sensitive GPIO pin interrupts
723 		configured, we could unmask GPIO bank interrupt immediately */
724 		if (!level_mask && !unmasked) {
725 			unmasked = 1;
726 			chained_irq_exit(chip, desc);
727 		}
728 
729 		if (!isr)
730 			break;
731 
732 		while (isr) {
733 			bit = __ffs(isr);
734 			isr &= ~(1 << bit);
735 
736 			/*
737 			 * Some chips can't respond to both rising and falling
738 			 * at the same time.  If this irq was requested with
739 			 * both flags, we need to flip the ICR data for the IRQ
740 			 * to respond to the IRQ for the opposite direction.
741 			 * This will be indicated in the bank toggle_mask.
742 			 */
743 			if (bank->toggle_mask & (1 << bit))
744 				_toggle_gpio_edge_triggering(bank, bit);
745 
746 			generic_handle_irq(irq_find_mapping(bank->domain, bit));
747 		}
748 	}
749 	/* if bank has any level sensitive GPIO pin interrupt
750 	configured, we must unmask the bank interrupt only after
751 	handler(s) are executed in order to avoid spurious bank
752 	interrupt */
753 exit:
754 	if (!unmasked)
755 		chained_irq_exit(chip, desc);
756 	pm_runtime_put(bank->dev);
757 }
758 
759 static void gpio_irq_shutdown(struct irq_data *d)
760 {
761 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
762 	unsigned int gpio = irq_to_gpio(bank, d->hwirq);
763 	unsigned long flags;
764 
765 	spin_lock_irqsave(&bank->lock, flags);
766 	_reset_gpio(bank, gpio);
767 	spin_unlock_irqrestore(&bank->lock, flags);
768 }
769 
770 static void gpio_ack_irq(struct irq_data *d)
771 {
772 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
773 	unsigned int gpio = irq_to_gpio(bank, d->hwirq);
774 
775 	_clear_gpio_irqstatus(bank, gpio);
776 }
777 
778 static void gpio_mask_irq(struct irq_data *d)
779 {
780 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
781 	unsigned int gpio = irq_to_gpio(bank, d->hwirq);
782 	unsigned long flags;
783 
784 	spin_lock_irqsave(&bank->lock, flags);
785 	_set_gpio_irqenable(bank, gpio, 0);
786 	_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
787 	spin_unlock_irqrestore(&bank->lock, flags);
788 }
789 
790 static void gpio_unmask_irq(struct irq_data *d)
791 {
792 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
793 	unsigned int gpio = irq_to_gpio(bank, d->hwirq);
794 	unsigned int irq_mask = GPIO_BIT(bank, gpio);
795 	u32 trigger = irqd_get_trigger_type(d);
796 	unsigned long flags;
797 
798 	spin_lock_irqsave(&bank->lock, flags);
799 	if (trigger)
800 		_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
801 
802 	/* For level-triggered GPIOs, the clearing must be done after
803 	 * the HW source is cleared, thus after the handler has run */
804 	if (bank->level_mask & irq_mask) {
805 		_set_gpio_irqenable(bank, gpio, 0);
806 		_clear_gpio_irqstatus(bank, gpio);
807 	}
808 
809 	_set_gpio_irqenable(bank, gpio, 1);
810 	spin_unlock_irqrestore(&bank->lock, flags);
811 }
812 
813 static struct irq_chip gpio_irq_chip = {
814 	.name		= "GPIO",
815 	.irq_shutdown	= gpio_irq_shutdown,
816 	.irq_ack	= gpio_ack_irq,
817 	.irq_mask	= gpio_mask_irq,
818 	.irq_unmask	= gpio_unmask_irq,
819 	.irq_set_type	= gpio_irq_type,
820 	.irq_set_wake	= gpio_wake_enable,
821 };
822 
823 /*---------------------------------------------------------------------*/
824 
825 static int omap_mpuio_suspend_noirq(struct device *dev)
826 {
827 	struct platform_device *pdev = to_platform_device(dev);
828 	struct gpio_bank	*bank = platform_get_drvdata(pdev);
829 	void __iomem		*mask_reg = bank->base +
830 					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
831 	unsigned long		flags;
832 
833 	spin_lock_irqsave(&bank->lock, flags);
834 	__raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
835 	spin_unlock_irqrestore(&bank->lock, flags);
836 
837 	return 0;
838 }
839 
840 static int omap_mpuio_resume_noirq(struct device *dev)
841 {
842 	struct platform_device *pdev = to_platform_device(dev);
843 	struct gpio_bank	*bank = platform_get_drvdata(pdev);
844 	void __iomem		*mask_reg = bank->base +
845 					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
846 	unsigned long		flags;
847 
848 	spin_lock_irqsave(&bank->lock, flags);
849 	__raw_writel(bank->context.wake_en, mask_reg);
850 	spin_unlock_irqrestore(&bank->lock, flags);
851 
852 	return 0;
853 }
854 
855 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
856 	.suspend_noirq = omap_mpuio_suspend_noirq,
857 	.resume_noirq = omap_mpuio_resume_noirq,
858 };
859 
860 /* use platform_driver for this. */
861 static struct platform_driver omap_mpuio_driver = {
862 	.driver		= {
863 		.name	= "mpuio",
864 		.pm	= &omap_mpuio_dev_pm_ops,
865 	},
866 };
867 
868 static struct platform_device omap_mpuio_device = {
869 	.name		= "mpuio",
870 	.id		= -1,
871 	.dev = {
872 		.driver = &omap_mpuio_driver.driver,
873 	}
874 	/* could list the /proc/iomem resources */
875 };
876 
877 static inline void mpuio_init(struct gpio_bank *bank)
878 {
879 	platform_set_drvdata(&omap_mpuio_device, bank);
880 
881 	if (platform_driver_register(&omap_mpuio_driver) == 0)
882 		(void) platform_device_register(&omap_mpuio_device);
883 }
884 
885 /*---------------------------------------------------------------------*/
886 
887 static int gpio_input(struct gpio_chip *chip, unsigned offset)
888 {
889 	struct gpio_bank *bank;
890 	unsigned long flags;
891 
892 	bank = container_of(chip, struct gpio_bank, chip);
893 	spin_lock_irqsave(&bank->lock, flags);
894 	_set_gpio_direction(bank, offset, 1);
895 	spin_unlock_irqrestore(&bank->lock, flags);
896 	return 0;
897 }
898 
899 static int gpio_is_input(struct gpio_bank *bank, int mask)
900 {
901 	void __iomem *reg = bank->base + bank->regs->direction;
902 
903 	return __raw_readl(reg) & mask;
904 }
905 
906 static int gpio_get(struct gpio_chip *chip, unsigned offset)
907 {
908 	struct gpio_bank *bank;
909 	u32 mask;
910 
911 	bank = container_of(chip, struct gpio_bank, chip);
912 	mask = (1 << offset);
913 
914 	if (gpio_is_input(bank, mask))
915 		return _get_gpio_datain(bank, offset);
916 	else
917 		return _get_gpio_dataout(bank, offset);
918 }
919 
920 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
921 {
922 	struct gpio_bank *bank;
923 	unsigned long flags;
924 
925 	bank = container_of(chip, struct gpio_bank, chip);
926 	spin_lock_irqsave(&bank->lock, flags);
927 	bank->set_dataout(bank, offset, value);
928 	_set_gpio_direction(bank, offset, 0);
929 	spin_unlock_irqrestore(&bank->lock, flags);
930 	return 0;
931 }
932 
933 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
934 		unsigned debounce)
935 {
936 	struct gpio_bank *bank;
937 	unsigned long flags;
938 
939 	bank = container_of(chip, struct gpio_bank, chip);
940 
941 	spin_lock_irqsave(&bank->lock, flags);
942 	_set_gpio_debounce(bank, offset, debounce);
943 	spin_unlock_irqrestore(&bank->lock, flags);
944 
945 	return 0;
946 }
947 
948 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
949 {
950 	struct gpio_bank *bank;
951 	unsigned long flags;
952 
953 	bank = container_of(chip, struct gpio_bank, chip);
954 	spin_lock_irqsave(&bank->lock, flags);
955 	bank->set_dataout(bank, offset, value);
956 	spin_unlock_irqrestore(&bank->lock, flags);
957 }
958 
959 /*---------------------------------------------------------------------*/
960 
961 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
962 {
963 	static bool called;
964 	u32 rev;
965 
966 	if (called || bank->regs->revision == USHRT_MAX)
967 		return;
968 
969 	rev = __raw_readw(bank->base + bank->regs->revision);
970 	pr_info("OMAP GPIO hardware version %d.%d\n",
971 		(rev >> 4) & 0x0f, rev & 0x0f);
972 
973 	called = true;
974 }
975 
976 /* This lock class tells lockdep that GPIO irqs are in a different
977  * category than their parents, so it won't report false recursion.
978  */
979 static struct lock_class_key gpio_lock_class;
980 
981 static void omap_gpio_mod_init(struct gpio_bank *bank)
982 {
983 	void __iomem *base = bank->base;
984 	u32 l = 0xffffffff;
985 
986 	if (bank->width == 16)
987 		l = 0xffff;
988 
989 	if (bank->is_mpuio) {
990 		__raw_writel(l, bank->base + bank->regs->irqenable);
991 		return;
992 	}
993 
994 	_gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
995 	_gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
996 	if (bank->regs->debounce_en)
997 		__raw_writel(0, base + bank->regs->debounce_en);
998 
999 	/* Save OE default value (0xffffffff) in the context */
1000 	bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
1001 	 /* Initialize interface clk ungated, module enabled */
1002 	if (bank->regs->ctrl)
1003 		__raw_writel(0, base + bank->regs->ctrl);
1004 
1005 	bank->dbck = clk_get(bank->dev, "dbclk");
1006 	if (IS_ERR(bank->dbck))
1007 		dev_err(bank->dev, "Could not get gpio dbck\n");
1008 }
1009 
1010 static void
1011 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1012 		    unsigned int num)
1013 {
1014 	struct irq_chip_generic *gc;
1015 	struct irq_chip_type *ct;
1016 
1017 	gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1018 				    handle_simple_irq);
1019 	if (!gc) {
1020 		dev_err(bank->dev, "Memory alloc failed for gc\n");
1021 		return;
1022 	}
1023 
1024 	ct = gc->chip_types;
1025 
1026 	/* NOTE: No ack required, reading IRQ status clears it. */
1027 	ct->chip.irq_mask = irq_gc_mask_set_bit;
1028 	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1029 	ct->chip.irq_set_type = gpio_irq_type;
1030 
1031 	if (bank->regs->wkup_en)
1032 		ct->chip.irq_set_wake = gpio_wake_enable,
1033 
1034 	ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1035 	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1036 			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1037 }
1038 
1039 static void omap_gpio_chip_init(struct gpio_bank *bank)
1040 {
1041 	int j;
1042 	static int gpio;
1043 
1044 	/*
1045 	 * REVISIT eventually switch from OMAP-specific gpio structs
1046 	 * over to the generic ones
1047 	 */
1048 	bank->chip.request = omap_gpio_request;
1049 	bank->chip.free = omap_gpio_free;
1050 	bank->chip.direction_input = gpio_input;
1051 	bank->chip.get = gpio_get;
1052 	bank->chip.direction_output = gpio_output;
1053 	bank->chip.set_debounce = gpio_debounce;
1054 	bank->chip.set = gpio_set;
1055 	bank->chip.to_irq = omap_gpio_to_irq;
1056 	if (bank->is_mpuio) {
1057 		bank->chip.label = "mpuio";
1058 		if (bank->regs->wkup_en)
1059 			bank->chip.dev = &omap_mpuio_device.dev;
1060 		bank->chip.base = OMAP_MPUIO(0);
1061 	} else {
1062 		bank->chip.label = "gpio";
1063 		bank->chip.base = gpio;
1064 		gpio += bank->width;
1065 	}
1066 	bank->chip.ngpio = bank->width;
1067 
1068 	gpiochip_add(&bank->chip);
1069 
1070 	for (j = 0; j < bank->width; j++) {
1071 		int irq = irq_create_mapping(bank->domain, j);
1072 		irq_set_lockdep_class(irq, &gpio_lock_class);
1073 		irq_set_chip_data(irq, bank);
1074 		if (bank->is_mpuio) {
1075 			omap_mpuio_alloc_gc(bank, irq, bank->width);
1076 		} else {
1077 			irq_set_chip_and_handler(irq, &gpio_irq_chip,
1078 						 handle_simple_irq);
1079 			set_irq_flags(irq, IRQF_VALID);
1080 		}
1081 	}
1082 	irq_set_chained_handler(bank->irq, gpio_irq_handler);
1083 	irq_set_handler_data(bank->irq, bank);
1084 }
1085 
1086 static const struct of_device_id omap_gpio_match[];
1087 
1088 static int omap_gpio_probe(struct platform_device *pdev)
1089 {
1090 	struct device *dev = &pdev->dev;
1091 	struct device_node *node = dev->of_node;
1092 	const struct of_device_id *match;
1093 	const struct omap_gpio_platform_data *pdata;
1094 	struct resource *res;
1095 	struct gpio_bank *bank;
1096 
1097 	match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1098 
1099 	pdata = match ? match->data : dev->platform_data;
1100 	if (!pdata)
1101 		return -EINVAL;
1102 
1103 	bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1104 	if (!bank) {
1105 		dev_err(dev, "Memory alloc failed\n");
1106 		return -ENOMEM;
1107 	}
1108 
1109 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1110 	if (unlikely(!res)) {
1111 		dev_err(dev, "Invalid IRQ resource\n");
1112 		return -ENODEV;
1113 	}
1114 
1115 	bank->irq = res->start;
1116 	bank->dev = dev;
1117 	bank->dbck_flag = pdata->dbck_flag;
1118 	bank->stride = pdata->bank_stride;
1119 	bank->width = pdata->bank_width;
1120 	bank->is_mpuio = pdata->is_mpuio;
1121 	bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1122 	bank->regs = pdata->regs;
1123 #ifdef CONFIG_OF_GPIO
1124 	bank->chip.of_node = of_node_get(node);
1125 #endif
1126 	if (node) {
1127 		if (!of_property_read_bool(node, "ti,gpio-always-on"))
1128 			bank->loses_context = true;
1129 	} else {
1130 		bank->loses_context = pdata->loses_context;
1131 	}
1132 
1133 
1134 	bank->domain = irq_domain_add_linear(node, bank->width,
1135 					     &irq_domain_simple_ops, NULL);
1136 	if (!bank->domain)
1137 		return -ENODEV;
1138 
1139 	if (bank->regs->set_dataout && bank->regs->clr_dataout)
1140 		bank->set_dataout = _set_gpio_dataout_reg;
1141 	else
1142 		bank->set_dataout = _set_gpio_dataout_mask;
1143 
1144 	spin_lock_init(&bank->lock);
1145 
1146 	/* Static mapping, never released */
1147 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1148 	if (unlikely(!res)) {
1149 		dev_err(dev, "Invalid mem resource\n");
1150 		irq_domain_remove(bank->domain);
1151 		return -ENODEV;
1152 	}
1153 
1154 	if (!devm_request_mem_region(dev, res->start, resource_size(res),
1155 				     pdev->name)) {
1156 		dev_err(dev, "Region already claimed\n");
1157 		irq_domain_remove(bank->domain);
1158 		return -EBUSY;
1159 	}
1160 
1161 	bank->base = devm_ioremap(dev, res->start, resource_size(res));
1162 	if (!bank->base) {
1163 		dev_err(dev, "Could not ioremap\n");
1164 		irq_domain_remove(bank->domain);
1165 		return -ENOMEM;
1166 	}
1167 
1168 	platform_set_drvdata(pdev, bank);
1169 
1170 	pm_runtime_enable(bank->dev);
1171 	pm_runtime_irq_safe(bank->dev);
1172 	pm_runtime_get_sync(bank->dev);
1173 
1174 	if (bank->is_mpuio)
1175 		mpuio_init(bank);
1176 
1177 	omap_gpio_mod_init(bank);
1178 	omap_gpio_chip_init(bank);
1179 	omap_gpio_show_rev(bank);
1180 
1181 	if (bank->loses_context)
1182 		bank->get_context_loss_count = pdata->get_context_loss_count;
1183 
1184 	pm_runtime_put(bank->dev);
1185 
1186 	list_add_tail(&bank->node, &omap_gpio_list);
1187 
1188 	return 0;
1189 }
1190 
1191 #ifdef CONFIG_ARCH_OMAP2PLUS
1192 
1193 #if defined(CONFIG_PM_RUNTIME)
1194 static void omap_gpio_restore_context(struct gpio_bank *bank);
1195 
1196 static int omap_gpio_runtime_suspend(struct device *dev)
1197 {
1198 	struct platform_device *pdev = to_platform_device(dev);
1199 	struct gpio_bank *bank = platform_get_drvdata(pdev);
1200 	u32 l1 = 0, l2 = 0;
1201 	unsigned long flags;
1202 	u32 wake_low, wake_hi;
1203 
1204 	spin_lock_irqsave(&bank->lock, flags);
1205 
1206 	/*
1207 	 * Only edges can generate a wakeup event to the PRCM.
1208 	 *
1209 	 * Therefore, ensure any wake-up capable GPIOs have
1210 	 * edge-detection enabled before going idle to ensure a wakeup
1211 	 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1212 	 * NDA TRM 25.5.3.1)
1213 	 *
1214 	 * The normal values will be restored upon ->runtime_resume()
1215 	 * by writing back the values saved in bank->context.
1216 	 */
1217 	wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1218 	if (wake_low)
1219 		__raw_writel(wake_low | bank->context.fallingdetect,
1220 			     bank->base + bank->regs->fallingdetect);
1221 	wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1222 	if (wake_hi)
1223 		__raw_writel(wake_hi | bank->context.risingdetect,
1224 			     bank->base + bank->regs->risingdetect);
1225 
1226 	if (!bank->enabled_non_wakeup_gpios)
1227 		goto update_gpio_context_count;
1228 
1229 	if (bank->power_mode != OFF_MODE) {
1230 		bank->power_mode = 0;
1231 		goto update_gpio_context_count;
1232 	}
1233 	/*
1234 	 * If going to OFF, remove triggering for all
1235 	 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
1236 	 * generated.  See OMAP2420 Errata item 1.101.
1237 	 */
1238 	bank->saved_datain = __raw_readl(bank->base +
1239 						bank->regs->datain);
1240 	l1 = bank->context.fallingdetect;
1241 	l2 = bank->context.risingdetect;
1242 
1243 	l1 &= ~bank->enabled_non_wakeup_gpios;
1244 	l2 &= ~bank->enabled_non_wakeup_gpios;
1245 
1246 	__raw_writel(l1, bank->base + bank->regs->fallingdetect);
1247 	__raw_writel(l2, bank->base + bank->regs->risingdetect);
1248 
1249 	bank->workaround_enabled = true;
1250 
1251 update_gpio_context_count:
1252 	if (bank->get_context_loss_count)
1253 		bank->context_loss_count =
1254 				bank->get_context_loss_count(bank->dev);
1255 
1256 	_gpio_dbck_disable(bank);
1257 	spin_unlock_irqrestore(&bank->lock, flags);
1258 
1259 	return 0;
1260 }
1261 
1262 static int omap_gpio_runtime_resume(struct device *dev)
1263 {
1264 	struct platform_device *pdev = to_platform_device(dev);
1265 	struct gpio_bank *bank = platform_get_drvdata(pdev);
1266 	u32 l = 0, gen, gen0, gen1;
1267 	unsigned long flags;
1268 	int c;
1269 
1270 	spin_lock_irqsave(&bank->lock, flags);
1271 	_gpio_dbck_enable(bank);
1272 
1273 	/*
1274 	 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1275 	 * GPIOs were set to edge trigger also in order to be able to
1276 	 * generate a PRCM wakeup.  Here we restore the
1277 	 * pre-runtime_suspend() values for edge triggering.
1278 	 */
1279 	__raw_writel(bank->context.fallingdetect,
1280 		     bank->base + bank->regs->fallingdetect);
1281 	__raw_writel(bank->context.risingdetect,
1282 		     bank->base + bank->regs->risingdetect);
1283 
1284 	if (bank->loses_context) {
1285 		if (!bank->get_context_loss_count) {
1286 			omap_gpio_restore_context(bank);
1287 		} else {
1288 			c = bank->get_context_loss_count(bank->dev);
1289 			if (c != bank->context_loss_count) {
1290 				omap_gpio_restore_context(bank);
1291 			} else {
1292 				spin_unlock_irqrestore(&bank->lock, flags);
1293 				return 0;
1294 			}
1295 		}
1296 	}
1297 
1298 	if (!bank->workaround_enabled) {
1299 		spin_unlock_irqrestore(&bank->lock, flags);
1300 		return 0;
1301 	}
1302 
1303 	l = __raw_readl(bank->base + bank->regs->datain);
1304 
1305 	/*
1306 	 * Check if any of the non-wakeup interrupt GPIOs have changed
1307 	 * state.  If so, generate an IRQ by software.  This is
1308 	 * horribly racy, but it's the best we can do to work around
1309 	 * this silicon bug.
1310 	 */
1311 	l ^= bank->saved_datain;
1312 	l &= bank->enabled_non_wakeup_gpios;
1313 
1314 	/*
1315 	 * No need to generate IRQs for the rising edge for gpio IRQs
1316 	 * configured with falling edge only; and vice versa.
1317 	 */
1318 	gen0 = l & bank->context.fallingdetect;
1319 	gen0 &= bank->saved_datain;
1320 
1321 	gen1 = l & bank->context.risingdetect;
1322 	gen1 &= ~(bank->saved_datain);
1323 
1324 	/* FIXME: Consider GPIO IRQs with level detections properly! */
1325 	gen = l & (~(bank->context.fallingdetect) &
1326 					 ~(bank->context.risingdetect));
1327 	/* Consider all GPIO IRQs needed to be updated */
1328 	gen |= gen0 | gen1;
1329 
1330 	if (gen) {
1331 		u32 old0, old1;
1332 
1333 		old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
1334 		old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
1335 
1336 		if (!bank->regs->irqstatus_raw0) {
1337 			__raw_writel(old0 | gen, bank->base +
1338 						bank->regs->leveldetect0);
1339 			__raw_writel(old1 | gen, bank->base +
1340 						bank->regs->leveldetect1);
1341 		}
1342 
1343 		if (bank->regs->irqstatus_raw0) {
1344 			__raw_writel(old0 | l, bank->base +
1345 						bank->regs->leveldetect0);
1346 			__raw_writel(old1 | l, bank->base +
1347 						bank->regs->leveldetect1);
1348 		}
1349 		__raw_writel(old0, bank->base + bank->regs->leveldetect0);
1350 		__raw_writel(old1, bank->base + bank->regs->leveldetect1);
1351 	}
1352 
1353 	bank->workaround_enabled = false;
1354 	spin_unlock_irqrestore(&bank->lock, flags);
1355 
1356 	return 0;
1357 }
1358 #endif /* CONFIG_PM_RUNTIME */
1359 
1360 void omap2_gpio_prepare_for_idle(int pwr_mode)
1361 {
1362 	struct gpio_bank *bank;
1363 
1364 	list_for_each_entry(bank, &omap_gpio_list, node) {
1365 		if (!bank->mod_usage || !bank->loses_context)
1366 			continue;
1367 
1368 		bank->power_mode = pwr_mode;
1369 
1370 		pm_runtime_put_sync_suspend(bank->dev);
1371 	}
1372 }
1373 
1374 void omap2_gpio_resume_after_idle(void)
1375 {
1376 	struct gpio_bank *bank;
1377 
1378 	list_for_each_entry(bank, &omap_gpio_list, node) {
1379 		if (!bank->mod_usage || !bank->loses_context)
1380 			continue;
1381 
1382 		pm_runtime_get_sync(bank->dev);
1383 	}
1384 }
1385 
1386 #if defined(CONFIG_PM_RUNTIME)
1387 static void omap_gpio_restore_context(struct gpio_bank *bank)
1388 {
1389 	__raw_writel(bank->context.wake_en,
1390 				bank->base + bank->regs->wkup_en);
1391 	__raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
1392 	__raw_writel(bank->context.leveldetect0,
1393 				bank->base + bank->regs->leveldetect0);
1394 	__raw_writel(bank->context.leveldetect1,
1395 				bank->base + bank->regs->leveldetect1);
1396 	__raw_writel(bank->context.risingdetect,
1397 				bank->base + bank->regs->risingdetect);
1398 	__raw_writel(bank->context.fallingdetect,
1399 				bank->base + bank->regs->fallingdetect);
1400 	if (bank->regs->set_dataout && bank->regs->clr_dataout)
1401 		__raw_writel(bank->context.dataout,
1402 				bank->base + bank->regs->set_dataout);
1403 	else
1404 		__raw_writel(bank->context.dataout,
1405 				bank->base + bank->regs->dataout);
1406 	__raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1407 
1408 	if (bank->dbck_enable_mask) {
1409 		__raw_writel(bank->context.debounce, bank->base +
1410 					bank->regs->debounce);
1411 		__raw_writel(bank->context.debounce_en,
1412 					bank->base + bank->regs->debounce_en);
1413 	}
1414 
1415 	__raw_writel(bank->context.irqenable1,
1416 				bank->base + bank->regs->irqenable);
1417 	__raw_writel(bank->context.irqenable2,
1418 				bank->base + bank->regs->irqenable2);
1419 }
1420 #endif /* CONFIG_PM_RUNTIME */
1421 #else
1422 #define omap_gpio_runtime_suspend NULL
1423 #define omap_gpio_runtime_resume NULL
1424 #endif
1425 
1426 static const struct dev_pm_ops gpio_pm_ops = {
1427 	SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1428 									NULL)
1429 };
1430 
1431 #if defined(CONFIG_OF)
1432 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1433 	.revision =		OMAP24XX_GPIO_REVISION,
1434 	.direction =		OMAP24XX_GPIO_OE,
1435 	.datain =		OMAP24XX_GPIO_DATAIN,
1436 	.dataout =		OMAP24XX_GPIO_DATAOUT,
1437 	.set_dataout =		OMAP24XX_GPIO_SETDATAOUT,
1438 	.clr_dataout =		OMAP24XX_GPIO_CLEARDATAOUT,
1439 	.irqstatus =		OMAP24XX_GPIO_IRQSTATUS1,
1440 	.irqstatus2 =		OMAP24XX_GPIO_IRQSTATUS2,
1441 	.irqenable =		OMAP24XX_GPIO_IRQENABLE1,
1442 	.irqenable2 =		OMAP24XX_GPIO_IRQENABLE2,
1443 	.set_irqenable =	OMAP24XX_GPIO_SETIRQENABLE1,
1444 	.clr_irqenable =	OMAP24XX_GPIO_CLEARIRQENABLE1,
1445 	.debounce =		OMAP24XX_GPIO_DEBOUNCE_VAL,
1446 	.debounce_en =		OMAP24XX_GPIO_DEBOUNCE_EN,
1447 	.ctrl =			OMAP24XX_GPIO_CTRL,
1448 	.wkup_en =		OMAP24XX_GPIO_WAKE_EN,
1449 	.leveldetect0 =		OMAP24XX_GPIO_LEVELDETECT0,
1450 	.leveldetect1 =		OMAP24XX_GPIO_LEVELDETECT1,
1451 	.risingdetect =		OMAP24XX_GPIO_RISINGDETECT,
1452 	.fallingdetect =	OMAP24XX_GPIO_FALLINGDETECT,
1453 };
1454 
1455 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1456 	.revision =		OMAP4_GPIO_REVISION,
1457 	.direction =		OMAP4_GPIO_OE,
1458 	.datain =		OMAP4_GPIO_DATAIN,
1459 	.dataout =		OMAP4_GPIO_DATAOUT,
1460 	.set_dataout =		OMAP4_GPIO_SETDATAOUT,
1461 	.clr_dataout =		OMAP4_GPIO_CLEARDATAOUT,
1462 	.irqstatus =		OMAP4_GPIO_IRQSTATUS0,
1463 	.irqstatus2 =		OMAP4_GPIO_IRQSTATUS1,
1464 	.irqenable =		OMAP4_GPIO_IRQSTATUSSET0,
1465 	.irqenable2 =		OMAP4_GPIO_IRQSTATUSSET1,
1466 	.set_irqenable =	OMAP4_GPIO_IRQSTATUSSET0,
1467 	.clr_irqenable =	OMAP4_GPIO_IRQSTATUSCLR0,
1468 	.debounce =		OMAP4_GPIO_DEBOUNCINGTIME,
1469 	.debounce_en =		OMAP4_GPIO_DEBOUNCENABLE,
1470 	.ctrl =			OMAP4_GPIO_CTRL,
1471 	.wkup_en =		OMAP4_GPIO_IRQWAKEN0,
1472 	.leveldetect0 =		OMAP4_GPIO_LEVELDETECT0,
1473 	.leveldetect1 =		OMAP4_GPIO_LEVELDETECT1,
1474 	.risingdetect =		OMAP4_GPIO_RISINGDETECT,
1475 	.fallingdetect =	OMAP4_GPIO_FALLINGDETECT,
1476 };
1477 
1478 static const struct omap_gpio_platform_data omap2_pdata = {
1479 	.regs = &omap2_gpio_regs,
1480 	.bank_width = 32,
1481 	.dbck_flag = false,
1482 };
1483 
1484 static const struct omap_gpio_platform_data omap3_pdata = {
1485 	.regs = &omap2_gpio_regs,
1486 	.bank_width = 32,
1487 	.dbck_flag = true,
1488 };
1489 
1490 static const struct omap_gpio_platform_data omap4_pdata = {
1491 	.regs = &omap4_gpio_regs,
1492 	.bank_width = 32,
1493 	.dbck_flag = true,
1494 };
1495 
1496 static const struct of_device_id omap_gpio_match[] = {
1497 	{
1498 		.compatible = "ti,omap4-gpio",
1499 		.data = &omap4_pdata,
1500 	},
1501 	{
1502 		.compatible = "ti,omap3-gpio",
1503 		.data = &omap3_pdata,
1504 	},
1505 	{
1506 		.compatible = "ti,omap2-gpio",
1507 		.data = &omap2_pdata,
1508 	},
1509 	{ },
1510 };
1511 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1512 #endif
1513 
1514 static struct platform_driver omap_gpio_driver = {
1515 	.probe		= omap_gpio_probe,
1516 	.driver		= {
1517 		.name	= "omap_gpio",
1518 		.pm	= &gpio_pm_ops,
1519 		.of_match_table = of_match_ptr(omap_gpio_match),
1520 	},
1521 };
1522 
1523 /*
1524  * gpio driver register needs to be done before
1525  * machine_init functions access gpio APIs.
1526  * Hence omap_gpio_drv_reg() is a postcore_initcall.
1527  */
1528 static int __init omap_gpio_drv_reg(void)
1529 {
1530 	return platform_driver_register(&omap_gpio_driver);
1531 }
1532 postcore_initcall(omap_gpio_drv_reg);
1533