xref: /openbmc/linux/drivers/gpio/gpio-omap.c (revision 56d06fa2) 
1 /*
2  * Support functions for OMAP GPIO
3  *
4  * Copyright (C) 2003-2005 Nokia Corporation
5  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6  *
7  * Copyright (C) 2009 Texas Instruments
8  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  */
14 
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/gpio.h>
28 #include <linux/bitops.h>
29 #include <linux/platform_data/gpio-omap.h>
30 
31 #define OFF_MODE	1
32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
33 
34 static LIST_HEAD(omap_gpio_list);
35 
36 struct gpio_regs {
37 	u32 irqenable1;
38 	u32 irqenable2;
39 	u32 wake_en;
40 	u32 ctrl;
41 	u32 oe;
42 	u32 leveldetect0;
43 	u32 leveldetect1;
44 	u32 risingdetect;
45 	u32 fallingdetect;
46 	u32 dataout;
47 	u32 debounce;
48 	u32 debounce_en;
49 };
50 
51 struct gpio_bank {
52 	struct list_head node;
53 	void __iomem *base;
54 	int irq;
55 	u32 non_wakeup_gpios;
56 	u32 enabled_non_wakeup_gpios;
57 	struct gpio_regs context;
58 	u32 saved_datain;
59 	u32 level_mask;
60 	u32 toggle_mask;
61 	raw_spinlock_t lock;
62 	raw_spinlock_t wa_lock;
63 	struct gpio_chip chip;
64 	struct clk *dbck;
65 	u32 mod_usage;
66 	u32 irq_usage;
67 	u32 dbck_enable_mask;
68 	bool dbck_enabled;
69 	bool is_mpuio;
70 	bool dbck_flag;
71 	bool loses_context;
72 	bool context_valid;
73 	int stride;
74 	u32 width;
75 	int context_loss_count;
76 	int power_mode;
77 	bool workaround_enabled;
78 
79 	void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
80 	int (*get_context_loss_count)(struct device *dev);
81 
82 	struct omap_gpio_reg_offs *regs;
83 };
84 
85 #define GPIO_MOD_CTRL_BIT	BIT(0)
86 
87 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
88 #define LINE_USED(line, offset) (line & (BIT(offset)))
89 
90 static void omap_gpio_unmask_irq(struct irq_data *d);
91 
92 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
93 {
94 	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
95 	return gpiochip_get_data(chip);
96 }
97 
98 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
99 				    int is_input)
100 {
101 	void __iomem *reg = bank->base;
102 	u32 l;
103 
104 	reg += bank->regs->direction;
105 	l = readl_relaxed(reg);
106 	if (is_input)
107 		l |= BIT(gpio);
108 	else
109 		l &= ~(BIT(gpio));
110 	writel_relaxed(l, reg);
111 	bank->context.oe = l;
112 }
113 
114 
115 /* set data out value using dedicate set/clear register */
116 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
117 				      int enable)
118 {
119 	void __iomem *reg = bank->base;
120 	u32 l = BIT(offset);
121 
122 	if (enable) {
123 		reg += bank->regs->set_dataout;
124 		bank->context.dataout |= l;
125 	} else {
126 		reg += bank->regs->clr_dataout;
127 		bank->context.dataout &= ~l;
128 	}
129 
130 	writel_relaxed(l, reg);
131 }
132 
133 /* set data out value using mask register */
134 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
135 				       int enable)
136 {
137 	void __iomem *reg = bank->base + bank->regs->dataout;
138 	u32 gpio_bit = BIT(offset);
139 	u32 l;
140 
141 	l = readl_relaxed(reg);
142 	if (enable)
143 		l |= gpio_bit;
144 	else
145 		l &= ~gpio_bit;
146 	writel_relaxed(l, reg);
147 	bank->context.dataout = l;
148 }
149 
150 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
151 {
152 	void __iomem *reg = bank->base + bank->regs->datain;
153 
154 	return (readl_relaxed(reg) & (BIT(offset))) != 0;
155 }
156 
157 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
158 {
159 	void __iomem *reg = bank->base + bank->regs->dataout;
160 
161 	return (readl_relaxed(reg) & (BIT(offset))) != 0;
162 }
163 
164 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
165 {
166 	int l = readl_relaxed(base + reg);
167 
168 	if (set)
169 		l |= mask;
170 	else
171 		l &= ~mask;
172 
173 	writel_relaxed(l, base + reg);
174 }
175 
176 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
177 {
178 	if (bank->dbck_enable_mask && !bank->dbck_enabled) {
179 		clk_enable(bank->dbck);
180 		bank->dbck_enabled = true;
181 
182 		writel_relaxed(bank->dbck_enable_mask,
183 			     bank->base + bank->regs->debounce_en);
184 	}
185 }
186 
187 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
188 {
189 	if (bank->dbck_enable_mask && bank->dbck_enabled) {
190 		/*
191 		 * Disable debounce before cutting it's clock. If debounce is
192 		 * enabled but the clock is not, GPIO module seems to be unable
193 		 * to detect events and generate interrupts at least on OMAP3.
194 		 */
195 		writel_relaxed(0, bank->base + bank->regs->debounce_en);
196 
197 		clk_disable(bank->dbck);
198 		bank->dbck_enabled = false;
199 	}
200 }
201 
202 /**
203  * omap2_set_gpio_debounce - low level gpio debounce time
204  * @bank: the gpio bank we're acting upon
205  * @offset: the gpio number on this @bank
206  * @debounce: debounce time to use
207  *
208  * OMAP's debounce time is in 31us steps
209  *   <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
210  * so we need to convert and round up to the closest unit.
211  */
212 static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
213 				    unsigned debounce)
214 {
215 	void __iomem		*reg;
216 	u32			val;
217 	u32			l;
218 	bool			enable = !!debounce;
219 
220 	if (!bank->dbck_flag)
221 		return;
222 
223 	if (enable) {
224 		debounce = DIV_ROUND_UP(debounce, 31) - 1;
225 		debounce &= OMAP4_GPIO_DEBOUNCINGTIME_MASK;
226 	}
227 
228 	l = BIT(offset);
229 
230 	clk_enable(bank->dbck);
231 	reg = bank->base + bank->regs->debounce;
232 	writel_relaxed(debounce, reg);
233 
234 	reg = bank->base + bank->regs->debounce_en;
235 	val = readl_relaxed(reg);
236 
237 	if (enable)
238 		val |= l;
239 	else
240 		val &= ~l;
241 	bank->dbck_enable_mask = val;
242 
243 	writel_relaxed(val, reg);
244 	clk_disable(bank->dbck);
245 	/*
246 	 * Enable debounce clock per module.
247 	 * This call is mandatory because in omap_gpio_request() when
248 	 * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
249 	 * runtime callbck fails to turn on dbck because dbck_enable_mask
250 	 * used within _gpio_dbck_enable() is still not initialized at
251 	 * that point. Therefore we have to enable dbck here.
252 	 */
253 	omap_gpio_dbck_enable(bank);
254 	if (bank->dbck_enable_mask) {
255 		bank->context.debounce = debounce;
256 		bank->context.debounce_en = val;
257 	}
258 }
259 
260 /**
261  * omap_clear_gpio_debounce - clear debounce settings for a gpio
262  * @bank: the gpio bank we're acting upon
263  * @offset: the gpio number on this @bank
264  *
265  * If a gpio is using debounce, then clear the debounce enable bit and if
266  * this is the only gpio in this bank using debounce, then clear the debounce
267  * time too. The debounce clock will also be disabled when calling this function
268  * if this is the only gpio in the bank using debounce.
269  */
270 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
271 {
272 	u32 gpio_bit = BIT(offset);
273 
274 	if (!bank->dbck_flag)
275 		return;
276 
277 	if (!(bank->dbck_enable_mask & gpio_bit))
278 		return;
279 
280 	bank->dbck_enable_mask &= ~gpio_bit;
281 	bank->context.debounce_en &= ~gpio_bit;
282         writel_relaxed(bank->context.debounce_en,
283 		     bank->base + bank->regs->debounce_en);
284 
285 	if (!bank->dbck_enable_mask) {
286 		bank->context.debounce = 0;
287 		writel_relaxed(bank->context.debounce, bank->base +
288 			     bank->regs->debounce);
289 		clk_disable(bank->dbck);
290 		bank->dbck_enabled = false;
291 	}
292 }
293 
294 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
295 						unsigned trigger)
296 {
297 	void __iomem *base = bank->base;
298 	u32 gpio_bit = BIT(gpio);
299 
300 	omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
301 		      trigger & IRQ_TYPE_LEVEL_LOW);
302 	omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
303 		      trigger & IRQ_TYPE_LEVEL_HIGH);
304 	omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
305 		      trigger & IRQ_TYPE_EDGE_RISING);
306 	omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
307 		      trigger & IRQ_TYPE_EDGE_FALLING);
308 
309 	bank->context.leveldetect0 =
310 			readl_relaxed(bank->base + bank->regs->leveldetect0);
311 	bank->context.leveldetect1 =
312 			readl_relaxed(bank->base + bank->regs->leveldetect1);
313 	bank->context.risingdetect =
314 			readl_relaxed(bank->base + bank->regs->risingdetect);
315 	bank->context.fallingdetect =
316 			readl_relaxed(bank->base + bank->regs->fallingdetect);
317 
318 	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
319 		omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
320 		bank->context.wake_en =
321 			readl_relaxed(bank->base + bank->regs->wkup_en);
322 	}
323 
324 	/* This part needs to be executed always for OMAP{34xx, 44xx} */
325 	if (!bank->regs->irqctrl) {
326 		/* On omap24xx proceed only when valid GPIO bit is set */
327 		if (bank->non_wakeup_gpios) {
328 			if (!(bank->non_wakeup_gpios & gpio_bit))
329 				goto exit;
330 		}
331 
332 		/*
333 		 * Log the edge gpio and manually trigger the IRQ
334 		 * after resume if the input level changes
335 		 * to avoid irq lost during PER RET/OFF mode
336 		 * Applies for omap2 non-wakeup gpio and all omap3 gpios
337 		 */
338 		if (trigger & IRQ_TYPE_EDGE_BOTH)
339 			bank->enabled_non_wakeup_gpios |= gpio_bit;
340 		else
341 			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
342 	}
343 
344 exit:
345 	bank->level_mask =
346 		readl_relaxed(bank->base + bank->regs->leveldetect0) |
347 		readl_relaxed(bank->base + bank->regs->leveldetect1);
348 }
349 
350 #ifdef CONFIG_ARCH_OMAP1
351 /*
352  * This only applies to chips that can't do both rising and falling edge
353  * detection at once.  For all other chips, this function is a noop.
354  */
355 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
356 {
357 	void __iomem *reg = bank->base;
358 	u32 l = 0;
359 
360 	if (!bank->regs->irqctrl)
361 		return;
362 
363 	reg += bank->regs->irqctrl;
364 
365 	l = readl_relaxed(reg);
366 	if ((l >> gpio) & 1)
367 		l &= ~(BIT(gpio));
368 	else
369 		l |= BIT(gpio);
370 
371 	writel_relaxed(l, reg);
372 }
373 #else
374 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
375 #endif
376 
377 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
378 				    unsigned trigger)
379 {
380 	void __iomem *reg = bank->base;
381 	void __iomem *base = bank->base;
382 	u32 l = 0;
383 
384 	if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
385 		omap_set_gpio_trigger(bank, gpio, trigger);
386 	} else if (bank->regs->irqctrl) {
387 		reg += bank->regs->irqctrl;
388 
389 		l = readl_relaxed(reg);
390 		if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
391 			bank->toggle_mask |= BIT(gpio);
392 		if (trigger & IRQ_TYPE_EDGE_RISING)
393 			l |= BIT(gpio);
394 		else if (trigger & IRQ_TYPE_EDGE_FALLING)
395 			l &= ~(BIT(gpio));
396 		else
397 			return -EINVAL;
398 
399 		writel_relaxed(l, reg);
400 	} else if (bank->regs->edgectrl1) {
401 		if (gpio & 0x08)
402 			reg += bank->regs->edgectrl2;
403 		else
404 			reg += bank->regs->edgectrl1;
405 
406 		gpio &= 0x07;
407 		l = readl_relaxed(reg);
408 		l &= ~(3 << (gpio << 1));
409 		if (trigger & IRQ_TYPE_EDGE_RISING)
410 			l |= 2 << (gpio << 1);
411 		if (trigger & IRQ_TYPE_EDGE_FALLING)
412 			l |= BIT(gpio << 1);
413 
414 		/* Enable wake-up during idle for dynamic tick */
415 		omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
416 		bank->context.wake_en =
417 			readl_relaxed(bank->base + bank->regs->wkup_en);
418 		writel_relaxed(l, reg);
419 	}
420 	return 0;
421 }
422 
423 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
424 {
425 	if (bank->regs->pinctrl) {
426 		void __iomem *reg = bank->base + bank->regs->pinctrl;
427 
428 		/* Claim the pin for MPU */
429 		writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
430 	}
431 
432 	if (bank->regs->ctrl && !BANK_USED(bank)) {
433 		void __iomem *reg = bank->base + bank->regs->ctrl;
434 		u32 ctrl;
435 
436 		ctrl = readl_relaxed(reg);
437 		/* Module is enabled, clocks are not gated */
438 		ctrl &= ~GPIO_MOD_CTRL_BIT;
439 		writel_relaxed(ctrl, reg);
440 		bank->context.ctrl = ctrl;
441 	}
442 }
443 
444 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
445 {
446 	void __iomem *base = bank->base;
447 
448 	if (bank->regs->wkup_en &&
449 	    !LINE_USED(bank->mod_usage, offset) &&
450 	    !LINE_USED(bank->irq_usage, offset)) {
451 		/* Disable wake-up during idle for dynamic tick */
452 		omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
453 		bank->context.wake_en =
454 			readl_relaxed(bank->base + bank->regs->wkup_en);
455 	}
456 
457 	if (bank->regs->ctrl && !BANK_USED(bank)) {
458 		void __iomem *reg = bank->base + bank->regs->ctrl;
459 		u32 ctrl;
460 
461 		ctrl = readl_relaxed(reg);
462 		/* Module is disabled, clocks are gated */
463 		ctrl |= GPIO_MOD_CTRL_BIT;
464 		writel_relaxed(ctrl, reg);
465 		bank->context.ctrl = ctrl;
466 	}
467 }
468 
469 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
470 {
471 	void __iomem *reg = bank->base + bank->regs->direction;
472 
473 	return readl_relaxed(reg) & BIT(offset);
474 }
475 
476 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
477 {
478 	if (!LINE_USED(bank->mod_usage, offset)) {
479 		omap_enable_gpio_module(bank, offset);
480 		omap_set_gpio_direction(bank, offset, 1);
481 	}
482 	bank->irq_usage |= BIT(offset);
483 }
484 
485 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
486 {
487 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
488 	int retval;
489 	unsigned long flags;
490 	unsigned offset = d->hwirq;
491 
492 	if (type & ~IRQ_TYPE_SENSE_MASK)
493 		return -EINVAL;
494 
495 	if (!bank->regs->leveldetect0 &&
496 		(type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
497 		return -EINVAL;
498 
499 	raw_spin_lock_irqsave(&bank->lock, flags);
500 	retval = omap_set_gpio_triggering(bank, offset, type);
501 	if (retval) {
502 		raw_spin_unlock_irqrestore(&bank->lock, flags);
503 		goto error;
504 	}
505 	omap_gpio_init_irq(bank, offset);
506 	if (!omap_gpio_is_input(bank, offset)) {
507 		raw_spin_unlock_irqrestore(&bank->lock, flags);
508 		retval = -EINVAL;
509 		goto error;
510 	}
511 	raw_spin_unlock_irqrestore(&bank->lock, flags);
512 
513 	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
514 		irq_set_handler_locked(d, handle_level_irq);
515 	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
516 		irq_set_handler_locked(d, handle_edge_irq);
517 
518 	return 0;
519 
520 error:
521 	return retval;
522 }
523 
524 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
525 {
526 	void __iomem *reg = bank->base;
527 
528 	reg += bank->regs->irqstatus;
529 	writel_relaxed(gpio_mask, reg);
530 
531 	/* Workaround for clearing DSP GPIO interrupts to allow retention */
532 	if (bank->regs->irqstatus2) {
533 		reg = bank->base + bank->regs->irqstatus2;
534 		writel_relaxed(gpio_mask, reg);
535 	}
536 
537 	/* Flush posted write for the irq status to avoid spurious interrupts */
538 	readl_relaxed(reg);
539 }
540 
541 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
542 					     unsigned offset)
543 {
544 	omap_clear_gpio_irqbank(bank, BIT(offset));
545 }
546 
547 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
548 {
549 	void __iomem *reg = bank->base;
550 	u32 l;
551 	u32 mask = (BIT(bank->width)) - 1;
552 
553 	reg += bank->regs->irqenable;
554 	l = readl_relaxed(reg);
555 	if (bank->regs->irqenable_inv)
556 		l = ~l;
557 	l &= mask;
558 	return l;
559 }
560 
561 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
562 {
563 	void __iomem *reg = bank->base;
564 	u32 l;
565 
566 	if (bank->regs->set_irqenable) {
567 		reg += bank->regs->set_irqenable;
568 		l = gpio_mask;
569 		bank->context.irqenable1 |= gpio_mask;
570 	} else {
571 		reg += bank->regs->irqenable;
572 		l = readl_relaxed(reg);
573 		if (bank->regs->irqenable_inv)
574 			l &= ~gpio_mask;
575 		else
576 			l |= gpio_mask;
577 		bank->context.irqenable1 = l;
578 	}
579 
580 	writel_relaxed(l, reg);
581 }
582 
583 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
584 {
585 	void __iomem *reg = bank->base;
586 	u32 l;
587 
588 	if (bank->regs->clr_irqenable) {
589 		reg += bank->regs->clr_irqenable;
590 		l = gpio_mask;
591 		bank->context.irqenable1 &= ~gpio_mask;
592 	} else {
593 		reg += bank->regs->irqenable;
594 		l = readl_relaxed(reg);
595 		if (bank->regs->irqenable_inv)
596 			l |= gpio_mask;
597 		else
598 			l &= ~gpio_mask;
599 		bank->context.irqenable1 = l;
600 	}
601 
602 	writel_relaxed(l, reg);
603 }
604 
605 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
606 					   unsigned offset, int enable)
607 {
608 	if (enable)
609 		omap_enable_gpio_irqbank(bank, BIT(offset));
610 	else
611 		omap_disable_gpio_irqbank(bank, BIT(offset));
612 }
613 
614 /*
615  * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
616  * 1510 does not seem to have a wake-up register. If JTAG is connected
617  * to the target, system will wake up always on GPIO events. While
618  * system is running all registered GPIO interrupts need to have wake-up
619  * enabled. When system is suspended, only selected GPIO interrupts need
620  * to have wake-up enabled.
621  */
622 static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset,
623 				int enable)
624 {
625 	u32 gpio_bit = BIT(offset);
626 	unsigned long flags;
627 
628 	if (bank->non_wakeup_gpios & gpio_bit) {
629 		dev_err(bank->chip.parent,
630 			"Unable to modify wakeup on non-wakeup GPIO%d\n",
631 			offset);
632 		return -EINVAL;
633 	}
634 
635 	raw_spin_lock_irqsave(&bank->lock, flags);
636 	if (enable)
637 		bank->context.wake_en |= gpio_bit;
638 	else
639 		bank->context.wake_en &= ~gpio_bit;
640 
641 	writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
642 	raw_spin_unlock_irqrestore(&bank->lock, flags);
643 
644 	return 0;
645 }
646 
647 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
648 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
649 {
650 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
651 	unsigned offset = d->hwirq;
652 	int ret;
653 
654 	ret = omap_set_gpio_wakeup(bank, offset, enable);
655 	if (!ret)
656 		ret = irq_set_irq_wake(bank->irq, enable);
657 
658 	return ret;
659 }
660 
661 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
662 {
663 	struct gpio_bank *bank = gpiochip_get_data(chip);
664 	unsigned long flags;
665 
666 	/*
667 	 * If this is the first gpio_request for the bank,
668 	 * enable the bank module.
669 	 */
670 	if (!BANK_USED(bank))
671 		pm_runtime_get_sync(chip->parent);
672 
673 	raw_spin_lock_irqsave(&bank->lock, flags);
674 	omap_enable_gpio_module(bank, offset);
675 	bank->mod_usage |= BIT(offset);
676 	raw_spin_unlock_irqrestore(&bank->lock, flags);
677 
678 	return 0;
679 }
680 
681 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
682 {
683 	struct gpio_bank *bank = gpiochip_get_data(chip);
684 	unsigned long flags;
685 
686 	raw_spin_lock_irqsave(&bank->lock, flags);
687 	bank->mod_usage &= ~(BIT(offset));
688 	if (!LINE_USED(bank->irq_usage, offset)) {
689 		omap_set_gpio_direction(bank, offset, 1);
690 		omap_clear_gpio_debounce(bank, offset);
691 	}
692 	omap_disable_gpio_module(bank, offset);
693 	raw_spin_unlock_irqrestore(&bank->lock, flags);
694 
695 	/*
696 	 * If this is the last gpio to be freed in the bank,
697 	 * disable the bank module.
698 	 */
699 	if (!BANK_USED(bank))
700 		pm_runtime_put(chip->parent);
701 }
702 
703 /*
704  * We need to unmask the GPIO bank interrupt as soon as possible to
705  * avoid missing GPIO interrupts for other lines in the bank.
706  * Then we need to mask-read-clear-unmask the triggered GPIO lines
707  * in the bank to avoid missing nested interrupts for a GPIO line.
708  * If we wait to unmask individual GPIO lines in the bank after the
709  * line's interrupt handler has been run, we may miss some nested
710  * interrupts.
711  */
712 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
713 {
714 	void __iomem *isr_reg = NULL;
715 	u32 isr;
716 	unsigned int bit;
717 	struct gpio_bank *bank = gpiobank;
718 	unsigned long wa_lock_flags;
719 	unsigned long lock_flags;
720 
721 	isr_reg = bank->base + bank->regs->irqstatus;
722 	if (WARN_ON(!isr_reg))
723 		goto exit;
724 
725 	pm_runtime_get_sync(bank->chip.parent);
726 
727 	while (1) {
728 		u32 isr_saved, level_mask = 0;
729 		u32 enabled;
730 
731 		raw_spin_lock_irqsave(&bank->lock, lock_flags);
732 
733 		enabled = omap_get_gpio_irqbank_mask(bank);
734 		isr_saved = isr = readl_relaxed(isr_reg) & enabled;
735 
736 		if (bank->level_mask)
737 			level_mask = bank->level_mask & enabled;
738 
739 		/* clear edge sensitive interrupts before handler(s) are
740 		called so that we don't miss any interrupt occurred while
741 		executing them */
742 		omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
743 		omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
744 		omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
745 
746 		raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
747 
748 		if (!isr)
749 			break;
750 
751 		while (isr) {
752 			bit = __ffs(isr);
753 			isr &= ~(BIT(bit));
754 
755 			raw_spin_lock_irqsave(&bank->lock, lock_flags);
756 			/*
757 			 * Some chips can't respond to both rising and falling
758 			 * at the same time.  If this irq was requested with
759 			 * both flags, we need to flip the ICR data for the IRQ
760 			 * to respond to the IRQ for the opposite direction.
761 			 * This will be indicated in the bank toggle_mask.
762 			 */
763 			if (bank->toggle_mask & (BIT(bit)))
764 				omap_toggle_gpio_edge_triggering(bank, bit);
765 
766 			raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
767 
768 			raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
769 
770 			generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
771 							    bit));
772 
773 			raw_spin_unlock_irqrestore(&bank->wa_lock,
774 						   wa_lock_flags);
775 		}
776 	}
777 exit:
778 	pm_runtime_put(bank->chip.parent);
779 	return IRQ_HANDLED;
780 }
781 
782 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
783 {
784 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
785 	unsigned long flags;
786 	unsigned offset = d->hwirq;
787 
788 	raw_spin_lock_irqsave(&bank->lock, flags);
789 
790 	if (!LINE_USED(bank->mod_usage, offset))
791 		omap_set_gpio_direction(bank, offset, 1);
792 	else if (!omap_gpio_is_input(bank, offset))
793 		goto err;
794 	omap_enable_gpio_module(bank, offset);
795 	bank->irq_usage |= BIT(offset);
796 
797 	raw_spin_unlock_irqrestore(&bank->lock, flags);
798 	omap_gpio_unmask_irq(d);
799 
800 	return 0;
801 err:
802 	raw_spin_unlock_irqrestore(&bank->lock, flags);
803 	return -EINVAL;
804 }
805 
806 static void omap_gpio_irq_shutdown(struct irq_data *d)
807 {
808 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
809 	unsigned long flags;
810 	unsigned offset = d->hwirq;
811 
812 	raw_spin_lock_irqsave(&bank->lock, flags);
813 	bank->irq_usage &= ~(BIT(offset));
814 	omap_set_gpio_irqenable(bank, offset, 0);
815 	omap_clear_gpio_irqstatus(bank, offset);
816 	omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
817 	if (!LINE_USED(bank->mod_usage, offset))
818 		omap_clear_gpio_debounce(bank, offset);
819 	omap_disable_gpio_module(bank, offset);
820 	raw_spin_unlock_irqrestore(&bank->lock, flags);
821 }
822 
823 static void omap_gpio_irq_bus_lock(struct irq_data *data)
824 {
825 	struct gpio_bank *bank = omap_irq_data_get_bank(data);
826 
827 	if (!BANK_USED(bank))
828 		pm_runtime_get_sync(bank->chip.parent);
829 }
830 
831 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
832 {
833 	struct gpio_bank *bank = omap_irq_data_get_bank(data);
834 
835 	/*
836 	 * If this is the last IRQ to be freed in the bank,
837 	 * disable the bank module.
838 	 */
839 	if (!BANK_USED(bank))
840 		pm_runtime_put(bank->chip.parent);
841 }
842 
843 static void omap_gpio_ack_irq(struct irq_data *d)
844 {
845 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
846 	unsigned offset = d->hwirq;
847 
848 	omap_clear_gpio_irqstatus(bank, offset);
849 }
850 
851 static void omap_gpio_mask_irq(struct irq_data *d)
852 {
853 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
854 	unsigned offset = d->hwirq;
855 	unsigned long flags;
856 
857 	raw_spin_lock_irqsave(&bank->lock, flags);
858 	omap_set_gpio_irqenable(bank, offset, 0);
859 	omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
860 	raw_spin_unlock_irqrestore(&bank->lock, flags);
861 }
862 
863 static void omap_gpio_unmask_irq(struct irq_data *d)
864 {
865 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
866 	unsigned offset = d->hwirq;
867 	u32 trigger = irqd_get_trigger_type(d);
868 	unsigned long flags;
869 
870 	raw_spin_lock_irqsave(&bank->lock, flags);
871 	if (trigger)
872 		omap_set_gpio_triggering(bank, offset, trigger);
873 
874 	/* For level-triggered GPIOs, the clearing must be done after
875 	 * the HW source is cleared, thus after the handler has run */
876 	if (bank->level_mask & BIT(offset)) {
877 		omap_set_gpio_irqenable(bank, offset, 0);
878 		omap_clear_gpio_irqstatus(bank, offset);
879 	}
880 
881 	omap_set_gpio_irqenable(bank, offset, 1);
882 	raw_spin_unlock_irqrestore(&bank->lock, flags);
883 }
884 
885 /*---------------------------------------------------------------------*/
886 
887 static int omap_mpuio_suspend_noirq(struct device *dev)
888 {
889 	struct platform_device *pdev = to_platform_device(dev);
890 	struct gpio_bank	*bank = platform_get_drvdata(pdev);
891 	void __iomem		*mask_reg = bank->base +
892 					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
893 	unsigned long		flags;
894 
895 	raw_spin_lock_irqsave(&bank->lock, flags);
896 	writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
897 	raw_spin_unlock_irqrestore(&bank->lock, flags);
898 
899 	return 0;
900 }
901 
902 static int omap_mpuio_resume_noirq(struct device *dev)
903 {
904 	struct platform_device *pdev = to_platform_device(dev);
905 	struct gpio_bank	*bank = platform_get_drvdata(pdev);
906 	void __iomem		*mask_reg = bank->base +
907 					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
908 	unsigned long		flags;
909 
910 	raw_spin_lock_irqsave(&bank->lock, flags);
911 	writel_relaxed(bank->context.wake_en, mask_reg);
912 	raw_spin_unlock_irqrestore(&bank->lock, flags);
913 
914 	return 0;
915 }
916 
917 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
918 	.suspend_noirq = omap_mpuio_suspend_noirq,
919 	.resume_noirq = omap_mpuio_resume_noirq,
920 };
921 
922 /* use platform_driver for this. */
923 static struct platform_driver omap_mpuio_driver = {
924 	.driver		= {
925 		.name	= "mpuio",
926 		.pm	= &omap_mpuio_dev_pm_ops,
927 	},
928 };
929 
930 static struct platform_device omap_mpuio_device = {
931 	.name		= "mpuio",
932 	.id		= -1,
933 	.dev = {
934 		.driver = &omap_mpuio_driver.driver,
935 	}
936 	/* could list the /proc/iomem resources */
937 };
938 
939 static inline void omap_mpuio_init(struct gpio_bank *bank)
940 {
941 	platform_set_drvdata(&omap_mpuio_device, bank);
942 
943 	if (platform_driver_register(&omap_mpuio_driver) == 0)
944 		(void) platform_device_register(&omap_mpuio_device);
945 }
946 
947 /*---------------------------------------------------------------------*/
948 
949 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
950 {
951 	struct gpio_bank *bank;
952 	unsigned long flags;
953 	void __iomem *reg;
954 	int dir;
955 
956 	bank = gpiochip_get_data(chip);
957 	reg = bank->base + bank->regs->direction;
958 	raw_spin_lock_irqsave(&bank->lock, flags);
959 	dir = !!(readl_relaxed(reg) & BIT(offset));
960 	raw_spin_unlock_irqrestore(&bank->lock, flags);
961 	return dir;
962 }
963 
964 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
965 {
966 	struct gpio_bank *bank;
967 	unsigned long flags;
968 
969 	bank = gpiochip_get_data(chip);
970 	raw_spin_lock_irqsave(&bank->lock, flags);
971 	omap_set_gpio_direction(bank, offset, 1);
972 	raw_spin_unlock_irqrestore(&bank->lock, flags);
973 	return 0;
974 }
975 
976 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
977 {
978 	struct gpio_bank *bank;
979 
980 	bank = gpiochip_get_data(chip);
981 
982 	if (omap_gpio_is_input(bank, offset))
983 		return omap_get_gpio_datain(bank, offset);
984 	else
985 		return omap_get_gpio_dataout(bank, offset);
986 }
987 
988 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
989 {
990 	struct gpio_bank *bank;
991 	unsigned long flags;
992 
993 	bank = gpiochip_get_data(chip);
994 	raw_spin_lock_irqsave(&bank->lock, flags);
995 	bank->set_dataout(bank, offset, value);
996 	omap_set_gpio_direction(bank, offset, 0);
997 	raw_spin_unlock_irqrestore(&bank->lock, flags);
998 	return 0;
999 }
1000 
1001 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
1002 			      unsigned debounce)
1003 {
1004 	struct gpio_bank *bank;
1005 	unsigned long flags;
1006 
1007 	bank = gpiochip_get_data(chip);
1008 
1009 	raw_spin_lock_irqsave(&bank->lock, flags);
1010 	omap2_set_gpio_debounce(bank, offset, debounce);
1011 	raw_spin_unlock_irqrestore(&bank->lock, flags);
1012 
1013 	return 0;
1014 }
1015 
1016 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1017 {
1018 	struct gpio_bank *bank;
1019 	unsigned long flags;
1020 
1021 	bank = gpiochip_get_data(chip);
1022 	raw_spin_lock_irqsave(&bank->lock, flags);
1023 	bank->set_dataout(bank, offset, value);
1024 	raw_spin_unlock_irqrestore(&bank->lock, flags);
1025 }
1026 
1027 /*---------------------------------------------------------------------*/
1028 
1029 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1030 {
1031 	static bool called;
1032 	u32 rev;
1033 
1034 	if (called || bank->regs->revision == USHRT_MAX)
1035 		return;
1036 
1037 	rev = readw_relaxed(bank->base + bank->regs->revision);
1038 	pr_info("OMAP GPIO hardware version %d.%d\n",
1039 		(rev >> 4) & 0x0f, rev & 0x0f);
1040 
1041 	called = true;
1042 }
1043 
1044 static void omap_gpio_mod_init(struct gpio_bank *bank)
1045 {
1046 	void __iomem *base = bank->base;
1047 	u32 l = 0xffffffff;
1048 
1049 	if (bank->width == 16)
1050 		l = 0xffff;
1051 
1052 	if (bank->is_mpuio) {
1053 		writel_relaxed(l, bank->base + bank->regs->irqenable);
1054 		return;
1055 	}
1056 
1057 	omap_gpio_rmw(base, bank->regs->irqenable, l,
1058 		      bank->regs->irqenable_inv);
1059 	omap_gpio_rmw(base, bank->regs->irqstatus, l,
1060 		      !bank->regs->irqenable_inv);
1061 	if (bank->regs->debounce_en)
1062 		writel_relaxed(0, base + bank->regs->debounce_en);
1063 
1064 	/* Save OE default value (0xffffffff) in the context */
1065 	bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1066 	 /* Initialize interface clk ungated, module enabled */
1067 	if (bank->regs->ctrl)
1068 		writel_relaxed(0, base + bank->regs->ctrl);
1069 }
1070 
1071 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1072 {
1073 	static int gpio;
1074 	int irq_base = 0;
1075 	int ret;
1076 
1077 	/*
1078 	 * REVISIT eventually switch from OMAP-specific gpio structs
1079 	 * over to the generic ones
1080 	 */
1081 	bank->chip.request = omap_gpio_request;
1082 	bank->chip.free = omap_gpio_free;
1083 	bank->chip.get_direction = omap_gpio_get_direction;
1084 	bank->chip.direction_input = omap_gpio_input;
1085 	bank->chip.get = omap_gpio_get;
1086 	bank->chip.direction_output = omap_gpio_output;
1087 	bank->chip.set_debounce = omap_gpio_debounce;
1088 	bank->chip.set = omap_gpio_set;
1089 	if (bank->is_mpuio) {
1090 		bank->chip.label = "mpuio";
1091 		if (bank->regs->wkup_en)
1092 			bank->chip.parent = &omap_mpuio_device.dev;
1093 		bank->chip.base = OMAP_MPUIO(0);
1094 	} else {
1095 		bank->chip.label = "gpio";
1096 		bank->chip.base = gpio;
1097 	}
1098 	bank->chip.ngpio = bank->width;
1099 
1100 	ret = gpiochip_add_data(&bank->chip, bank);
1101 	if (ret) {
1102 		dev_err(bank->chip.parent,
1103 			"Could not register gpio chip %d\n", ret);
1104 		return ret;
1105 	}
1106 
1107 	if (!bank->is_mpuio)
1108 		gpio += bank->width;
1109 
1110 #ifdef CONFIG_ARCH_OMAP1
1111 	/*
1112 	 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1113 	 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1114 	 */
1115 	irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1116 	if (irq_base < 0) {
1117 		dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1118 		return -ENODEV;
1119 	}
1120 #endif
1121 
1122 	/* MPUIO is a bit different, reading IRQ status clears it */
1123 	if (bank->is_mpuio) {
1124 		irqc->irq_ack = dummy_irq_chip.irq_ack;
1125 		if (!bank->regs->wkup_en)
1126 			irqc->irq_set_wake = NULL;
1127 	}
1128 
1129 	ret = gpiochip_irqchip_add(&bank->chip, irqc,
1130 				   irq_base, handle_bad_irq,
1131 				   IRQ_TYPE_NONE);
1132 
1133 	if (ret) {
1134 		dev_err(bank->chip.parent,
1135 			"Couldn't add irqchip to gpiochip %d\n", ret);
1136 		gpiochip_remove(&bank->chip);
1137 		return -ENODEV;
1138 	}
1139 
1140 	gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL);
1141 
1142 	ret = devm_request_irq(bank->chip.parent, bank->irq,
1143 			       omap_gpio_irq_handler,
1144 			       0, dev_name(bank->chip.parent), bank);
1145 	if (ret)
1146 		gpiochip_remove(&bank->chip);
1147 
1148 	return ret;
1149 }
1150 
1151 static const struct of_device_id omap_gpio_match[];
1152 
1153 static int omap_gpio_probe(struct platform_device *pdev)
1154 {
1155 	struct device *dev = &pdev->dev;
1156 	struct device_node *node = dev->of_node;
1157 	const struct of_device_id *match;
1158 	const struct omap_gpio_platform_data *pdata;
1159 	struct resource *res;
1160 	struct gpio_bank *bank;
1161 	struct irq_chip *irqc;
1162 	int ret;
1163 
1164 	match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1165 
1166 	pdata = match ? match->data : dev_get_platdata(dev);
1167 	if (!pdata)
1168 		return -EINVAL;
1169 
1170 	bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1171 	if (!bank) {
1172 		dev_err(dev, "Memory alloc failed\n");
1173 		return -ENOMEM;
1174 	}
1175 
1176 	irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1177 	if (!irqc)
1178 		return -ENOMEM;
1179 
1180 	irqc->irq_startup = omap_gpio_irq_startup,
1181 	irqc->irq_shutdown = omap_gpio_irq_shutdown,
1182 	irqc->irq_ack = omap_gpio_ack_irq,
1183 	irqc->irq_mask = omap_gpio_mask_irq,
1184 	irqc->irq_unmask = omap_gpio_unmask_irq,
1185 	irqc->irq_set_type = omap_gpio_irq_type,
1186 	irqc->irq_set_wake = omap_gpio_wake_enable,
1187 	irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1188 	irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1189 	irqc->name = dev_name(&pdev->dev);
1190 
1191 	bank->irq = platform_get_irq(pdev, 0);
1192 	if (bank->irq <= 0) {
1193 		if (!bank->irq)
1194 			bank->irq = -ENXIO;
1195 		if (bank->irq != -EPROBE_DEFER)
1196 			dev_err(dev,
1197 				"can't get irq resource ret=%d\n", bank->irq);
1198 		return bank->irq;
1199 	}
1200 
1201 	bank->chip.parent = dev;
1202 	bank->chip.owner = THIS_MODULE;
1203 	bank->dbck_flag = pdata->dbck_flag;
1204 	bank->stride = pdata->bank_stride;
1205 	bank->width = pdata->bank_width;
1206 	bank->is_mpuio = pdata->is_mpuio;
1207 	bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1208 	bank->regs = pdata->regs;
1209 #ifdef CONFIG_OF_GPIO
1210 	bank->chip.of_node = of_node_get(node);
1211 #endif
1212 	if (node) {
1213 		if (!of_property_read_bool(node, "ti,gpio-always-on"))
1214 			bank->loses_context = true;
1215 	} else {
1216 		bank->loses_context = pdata->loses_context;
1217 
1218 		if (bank->loses_context)
1219 			bank->get_context_loss_count =
1220 				pdata->get_context_loss_count;
1221 	}
1222 
1223 	if (bank->regs->set_dataout && bank->regs->clr_dataout)
1224 		bank->set_dataout = omap_set_gpio_dataout_reg;
1225 	else
1226 		bank->set_dataout = omap_set_gpio_dataout_mask;
1227 
1228 	raw_spin_lock_init(&bank->lock);
1229 	raw_spin_lock_init(&bank->wa_lock);
1230 
1231 	/* Static mapping, never released */
1232 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1233 	bank->base = devm_ioremap_resource(dev, res);
1234 	if (IS_ERR(bank->base)) {
1235 		return PTR_ERR(bank->base);
1236 	}
1237 
1238 	if (bank->dbck_flag) {
1239 		bank->dbck = devm_clk_get(dev, "dbclk");
1240 		if (IS_ERR(bank->dbck)) {
1241 			dev_err(dev,
1242 				"Could not get gpio dbck. Disable debounce\n");
1243 			bank->dbck_flag = false;
1244 		} else {
1245 			clk_prepare(bank->dbck);
1246 		}
1247 	}
1248 
1249 	platform_set_drvdata(pdev, bank);
1250 
1251 	pm_runtime_enable(dev);
1252 	pm_runtime_irq_safe(dev);
1253 	pm_runtime_get_sync(dev);
1254 
1255 	if (bank->is_mpuio)
1256 		omap_mpuio_init(bank);
1257 
1258 	omap_gpio_mod_init(bank);
1259 
1260 	ret = omap_gpio_chip_init(bank, irqc);
1261 	if (ret) {
1262 		pm_runtime_put_sync(dev);
1263 		pm_runtime_disable(dev);
1264 		return ret;
1265 	}
1266 
1267 	omap_gpio_show_rev(bank);
1268 
1269 	pm_runtime_put(dev);
1270 
1271 	list_add_tail(&bank->node, &omap_gpio_list);
1272 
1273 	return 0;
1274 }
1275 
1276 static int omap_gpio_remove(struct platform_device *pdev)
1277 {
1278 	struct gpio_bank *bank = platform_get_drvdata(pdev);
1279 
1280 	list_del(&bank->node);
1281 	gpiochip_remove(&bank->chip);
1282 	pm_runtime_disable(&pdev->dev);
1283 	if (bank->dbck_flag)
1284 		clk_unprepare(bank->dbck);
1285 
1286 	return 0;
1287 }
1288 
1289 #ifdef CONFIG_ARCH_OMAP2PLUS
1290 
1291 #if defined(CONFIG_PM)
1292 static void omap_gpio_restore_context(struct gpio_bank *bank);
1293 
1294 static int omap_gpio_runtime_suspend(struct device *dev)
1295 {
1296 	struct platform_device *pdev = to_platform_device(dev);
1297 	struct gpio_bank *bank = platform_get_drvdata(pdev);
1298 	u32 l1 = 0, l2 = 0;
1299 	unsigned long flags;
1300 	u32 wake_low, wake_hi;
1301 
1302 	raw_spin_lock_irqsave(&bank->lock, flags);
1303 
1304 	/*
1305 	 * Only edges can generate a wakeup event to the PRCM.
1306 	 *
1307 	 * Therefore, ensure any wake-up capable GPIOs have
1308 	 * edge-detection enabled before going idle to ensure a wakeup
1309 	 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1310 	 * NDA TRM 25.5.3.1)
1311 	 *
1312 	 * The normal values will be restored upon ->runtime_resume()
1313 	 * by writing back the values saved in bank->context.
1314 	 */
1315 	wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1316 	if (wake_low)
1317 		writel_relaxed(wake_low | bank->context.fallingdetect,
1318 			     bank->base + bank->regs->fallingdetect);
1319 	wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1320 	if (wake_hi)
1321 		writel_relaxed(wake_hi | bank->context.risingdetect,
1322 			     bank->base + bank->regs->risingdetect);
1323 
1324 	if (!bank->enabled_non_wakeup_gpios)
1325 		goto update_gpio_context_count;
1326 
1327 	if (bank->power_mode != OFF_MODE) {
1328 		bank->power_mode = 0;
1329 		goto update_gpio_context_count;
1330 	}
1331 	/*
1332 	 * If going to OFF, remove triggering for all
1333 	 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
1334 	 * generated.  See OMAP2420 Errata item 1.101.
1335 	 */
1336 	bank->saved_datain = readl_relaxed(bank->base +
1337 						bank->regs->datain);
1338 	l1 = bank->context.fallingdetect;
1339 	l2 = bank->context.risingdetect;
1340 
1341 	l1 &= ~bank->enabled_non_wakeup_gpios;
1342 	l2 &= ~bank->enabled_non_wakeup_gpios;
1343 
1344 	writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1345 	writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1346 
1347 	bank->workaround_enabled = true;
1348 
1349 update_gpio_context_count:
1350 	if (bank->get_context_loss_count)
1351 		bank->context_loss_count =
1352 				bank->get_context_loss_count(dev);
1353 
1354 	omap_gpio_dbck_disable(bank);
1355 	raw_spin_unlock_irqrestore(&bank->lock, flags);
1356 
1357 	return 0;
1358 }
1359 
1360 static void omap_gpio_init_context(struct gpio_bank *p);
1361 
1362 static int omap_gpio_runtime_resume(struct device *dev)
1363 {
1364 	struct platform_device *pdev = to_platform_device(dev);
1365 	struct gpio_bank *bank = platform_get_drvdata(pdev);
1366 	u32 l = 0, gen, gen0, gen1;
1367 	unsigned long flags;
1368 	int c;
1369 
1370 	raw_spin_lock_irqsave(&bank->lock, flags);
1371 
1372 	/*
1373 	 * On the first resume during the probe, the context has not
1374 	 * been initialised and so initialise it now. Also initialise
1375 	 * the context loss count.
1376 	 */
1377 	if (bank->loses_context && !bank->context_valid) {
1378 		omap_gpio_init_context(bank);
1379 
1380 		if (bank->get_context_loss_count)
1381 			bank->context_loss_count =
1382 				bank->get_context_loss_count(dev);
1383 	}
1384 
1385 	omap_gpio_dbck_enable(bank);
1386 
1387 	/*
1388 	 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1389 	 * GPIOs were set to edge trigger also in order to be able to
1390 	 * generate a PRCM wakeup.  Here we restore the
1391 	 * pre-runtime_suspend() values for edge triggering.
1392 	 */
1393 	writel_relaxed(bank->context.fallingdetect,
1394 		     bank->base + bank->regs->fallingdetect);
1395 	writel_relaxed(bank->context.risingdetect,
1396 		     bank->base + bank->regs->risingdetect);
1397 
1398 	if (bank->loses_context) {
1399 		if (!bank->get_context_loss_count) {
1400 			omap_gpio_restore_context(bank);
1401 		} else {
1402 			c = bank->get_context_loss_count(dev);
1403 			if (c != bank->context_loss_count) {
1404 				omap_gpio_restore_context(bank);
1405 			} else {
1406 				raw_spin_unlock_irqrestore(&bank->lock, flags);
1407 				return 0;
1408 			}
1409 		}
1410 	}
1411 
1412 	if (!bank->workaround_enabled) {
1413 		raw_spin_unlock_irqrestore(&bank->lock, flags);
1414 		return 0;
1415 	}
1416 
1417 	l = readl_relaxed(bank->base + bank->regs->datain);
1418 
1419 	/*
1420 	 * Check if any of the non-wakeup interrupt GPIOs have changed
1421 	 * state.  If so, generate an IRQ by software.  This is
1422 	 * horribly racy, but it's the best we can do to work around
1423 	 * this silicon bug.
1424 	 */
1425 	l ^= bank->saved_datain;
1426 	l &= bank->enabled_non_wakeup_gpios;
1427 
1428 	/*
1429 	 * No need to generate IRQs for the rising edge for gpio IRQs
1430 	 * configured with falling edge only; and vice versa.
1431 	 */
1432 	gen0 = l & bank->context.fallingdetect;
1433 	gen0 &= bank->saved_datain;
1434 
1435 	gen1 = l & bank->context.risingdetect;
1436 	gen1 &= ~(bank->saved_datain);
1437 
1438 	/* FIXME: Consider GPIO IRQs with level detections properly! */
1439 	gen = l & (~(bank->context.fallingdetect) &
1440 					 ~(bank->context.risingdetect));
1441 	/* Consider all GPIO IRQs needed to be updated */
1442 	gen |= gen0 | gen1;
1443 
1444 	if (gen) {
1445 		u32 old0, old1;
1446 
1447 		old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1448 		old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1449 
1450 		if (!bank->regs->irqstatus_raw0) {
1451 			writel_relaxed(old0 | gen, bank->base +
1452 						bank->regs->leveldetect0);
1453 			writel_relaxed(old1 | gen, bank->base +
1454 						bank->regs->leveldetect1);
1455 		}
1456 
1457 		if (bank->regs->irqstatus_raw0) {
1458 			writel_relaxed(old0 | l, bank->base +
1459 						bank->regs->leveldetect0);
1460 			writel_relaxed(old1 | l, bank->base +
1461 						bank->regs->leveldetect1);
1462 		}
1463 		writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1464 		writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1465 	}
1466 
1467 	bank->workaround_enabled = false;
1468 	raw_spin_unlock_irqrestore(&bank->lock, flags);
1469 
1470 	return 0;
1471 }
1472 #endif /* CONFIG_PM */
1473 
1474 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
1475 void omap2_gpio_prepare_for_idle(int pwr_mode)
1476 {
1477 	struct gpio_bank *bank;
1478 
1479 	list_for_each_entry(bank, &omap_gpio_list, node) {
1480 		if (!BANK_USED(bank) || !bank->loses_context)
1481 			continue;
1482 
1483 		bank->power_mode = pwr_mode;
1484 
1485 		pm_runtime_put_sync_suspend(bank->chip.parent);
1486 	}
1487 }
1488 
1489 void omap2_gpio_resume_after_idle(void)
1490 {
1491 	struct gpio_bank *bank;
1492 
1493 	list_for_each_entry(bank, &omap_gpio_list, node) {
1494 		if (!BANK_USED(bank) || !bank->loses_context)
1495 			continue;
1496 
1497 		pm_runtime_get_sync(bank->chip.parent);
1498 	}
1499 }
1500 #endif
1501 
1502 #if defined(CONFIG_PM)
1503 static void omap_gpio_init_context(struct gpio_bank *p)
1504 {
1505 	struct omap_gpio_reg_offs *regs = p->regs;
1506 	void __iomem *base = p->base;
1507 
1508 	p->context.ctrl		= readl_relaxed(base + regs->ctrl);
1509 	p->context.oe		= readl_relaxed(base + regs->direction);
1510 	p->context.wake_en	= readl_relaxed(base + regs->wkup_en);
1511 	p->context.leveldetect0	= readl_relaxed(base + regs->leveldetect0);
1512 	p->context.leveldetect1	= readl_relaxed(base + regs->leveldetect1);
1513 	p->context.risingdetect	= readl_relaxed(base + regs->risingdetect);
1514 	p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1515 	p->context.irqenable1	= readl_relaxed(base + regs->irqenable);
1516 	p->context.irqenable2	= readl_relaxed(base + regs->irqenable2);
1517 
1518 	if (regs->set_dataout && p->regs->clr_dataout)
1519 		p->context.dataout = readl_relaxed(base + regs->set_dataout);
1520 	else
1521 		p->context.dataout = readl_relaxed(base + regs->dataout);
1522 
1523 	p->context_valid = true;
1524 }
1525 
1526 static void omap_gpio_restore_context(struct gpio_bank *bank)
1527 {
1528 	writel_relaxed(bank->context.wake_en,
1529 				bank->base + bank->regs->wkup_en);
1530 	writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1531 	writel_relaxed(bank->context.leveldetect0,
1532 				bank->base + bank->regs->leveldetect0);
1533 	writel_relaxed(bank->context.leveldetect1,
1534 				bank->base + bank->regs->leveldetect1);
1535 	writel_relaxed(bank->context.risingdetect,
1536 				bank->base + bank->regs->risingdetect);
1537 	writel_relaxed(bank->context.fallingdetect,
1538 				bank->base + bank->regs->fallingdetect);
1539 	if (bank->regs->set_dataout && bank->regs->clr_dataout)
1540 		writel_relaxed(bank->context.dataout,
1541 				bank->base + bank->regs->set_dataout);
1542 	else
1543 		writel_relaxed(bank->context.dataout,
1544 				bank->base + bank->regs->dataout);
1545 	writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1546 
1547 	if (bank->dbck_enable_mask) {
1548 		writel_relaxed(bank->context.debounce, bank->base +
1549 					bank->regs->debounce);
1550 		writel_relaxed(bank->context.debounce_en,
1551 					bank->base + bank->regs->debounce_en);
1552 	}
1553 
1554 	writel_relaxed(bank->context.irqenable1,
1555 				bank->base + bank->regs->irqenable);
1556 	writel_relaxed(bank->context.irqenable2,
1557 				bank->base + bank->regs->irqenable2);
1558 }
1559 #endif /* CONFIG_PM */
1560 #else
1561 #define omap_gpio_runtime_suspend NULL
1562 #define omap_gpio_runtime_resume NULL
1563 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1564 #endif
1565 
1566 static const struct dev_pm_ops gpio_pm_ops = {
1567 	SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1568 									NULL)
1569 };
1570 
1571 #if defined(CONFIG_OF)
1572 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1573 	.revision =		OMAP24XX_GPIO_REVISION,
1574 	.direction =		OMAP24XX_GPIO_OE,
1575 	.datain =		OMAP24XX_GPIO_DATAIN,
1576 	.dataout =		OMAP24XX_GPIO_DATAOUT,
1577 	.set_dataout =		OMAP24XX_GPIO_SETDATAOUT,
1578 	.clr_dataout =		OMAP24XX_GPIO_CLEARDATAOUT,
1579 	.irqstatus =		OMAP24XX_GPIO_IRQSTATUS1,
1580 	.irqstatus2 =		OMAP24XX_GPIO_IRQSTATUS2,
1581 	.irqenable =		OMAP24XX_GPIO_IRQENABLE1,
1582 	.irqenable2 =		OMAP24XX_GPIO_IRQENABLE2,
1583 	.set_irqenable =	OMAP24XX_GPIO_SETIRQENABLE1,
1584 	.clr_irqenable =	OMAP24XX_GPIO_CLEARIRQENABLE1,
1585 	.debounce =		OMAP24XX_GPIO_DEBOUNCE_VAL,
1586 	.debounce_en =		OMAP24XX_GPIO_DEBOUNCE_EN,
1587 	.ctrl =			OMAP24XX_GPIO_CTRL,
1588 	.wkup_en =		OMAP24XX_GPIO_WAKE_EN,
1589 	.leveldetect0 =		OMAP24XX_GPIO_LEVELDETECT0,
1590 	.leveldetect1 =		OMAP24XX_GPIO_LEVELDETECT1,
1591 	.risingdetect =		OMAP24XX_GPIO_RISINGDETECT,
1592 	.fallingdetect =	OMAP24XX_GPIO_FALLINGDETECT,
1593 };
1594 
1595 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1596 	.revision =		OMAP4_GPIO_REVISION,
1597 	.direction =		OMAP4_GPIO_OE,
1598 	.datain =		OMAP4_GPIO_DATAIN,
1599 	.dataout =		OMAP4_GPIO_DATAOUT,
1600 	.set_dataout =		OMAP4_GPIO_SETDATAOUT,
1601 	.clr_dataout =		OMAP4_GPIO_CLEARDATAOUT,
1602 	.irqstatus =		OMAP4_GPIO_IRQSTATUS0,
1603 	.irqstatus2 =		OMAP4_GPIO_IRQSTATUS1,
1604 	.irqenable =		OMAP4_GPIO_IRQSTATUSSET0,
1605 	.irqenable2 =		OMAP4_GPIO_IRQSTATUSSET1,
1606 	.set_irqenable =	OMAP4_GPIO_IRQSTATUSSET0,
1607 	.clr_irqenable =	OMAP4_GPIO_IRQSTATUSCLR0,
1608 	.debounce =		OMAP4_GPIO_DEBOUNCINGTIME,
1609 	.debounce_en =		OMAP4_GPIO_DEBOUNCENABLE,
1610 	.ctrl =			OMAP4_GPIO_CTRL,
1611 	.wkup_en =		OMAP4_GPIO_IRQWAKEN0,
1612 	.leveldetect0 =		OMAP4_GPIO_LEVELDETECT0,
1613 	.leveldetect1 =		OMAP4_GPIO_LEVELDETECT1,
1614 	.risingdetect =		OMAP4_GPIO_RISINGDETECT,
1615 	.fallingdetect =	OMAP4_GPIO_FALLINGDETECT,
1616 };
1617 
1618 static const struct omap_gpio_platform_data omap2_pdata = {
1619 	.regs = &omap2_gpio_regs,
1620 	.bank_width = 32,
1621 	.dbck_flag = false,
1622 };
1623 
1624 static const struct omap_gpio_platform_data omap3_pdata = {
1625 	.regs = &omap2_gpio_regs,
1626 	.bank_width = 32,
1627 	.dbck_flag = true,
1628 };
1629 
1630 static const struct omap_gpio_platform_data omap4_pdata = {
1631 	.regs = &omap4_gpio_regs,
1632 	.bank_width = 32,
1633 	.dbck_flag = true,
1634 };
1635 
1636 static const struct of_device_id omap_gpio_match[] = {
1637 	{
1638 		.compatible = "ti,omap4-gpio",
1639 		.data = &omap4_pdata,
1640 	},
1641 	{
1642 		.compatible = "ti,omap3-gpio",
1643 		.data = &omap3_pdata,
1644 	},
1645 	{
1646 		.compatible = "ti,omap2-gpio",
1647 		.data = &omap2_pdata,
1648 	},
1649 	{ },
1650 };
1651 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1652 #endif
1653 
1654 static struct platform_driver omap_gpio_driver = {
1655 	.probe		= omap_gpio_probe,
1656 	.remove		= omap_gpio_remove,
1657 	.driver		= {
1658 		.name	= "omap_gpio",
1659 		.pm	= &gpio_pm_ops,
1660 		.of_match_table = of_match_ptr(omap_gpio_match),
1661 	},
1662 };
1663 
1664 /*
1665  * gpio driver register needs to be done before
1666  * machine_init functions access gpio APIs.
1667  * Hence omap_gpio_drv_reg() is a postcore_initcall.
1668  */
1669 static int __init omap_gpio_drv_reg(void)
1670 {
1671 	return platform_driver_register(&omap_gpio_driver);
1672 }
1673 postcore_initcall(omap_gpio_drv_reg);
1674 
1675 static void __exit omap_gpio_exit(void)
1676 {
1677 	platform_driver_unregister(&omap_gpio_driver);
1678 }
1679 module_exit(omap_gpio_exit);
1680 
1681 MODULE_DESCRIPTION("omap gpio driver");
1682 MODULE_ALIAS("platform:gpio-omap");
1683 MODULE_LICENSE("GPL v2");
1684