1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Support functions for OMAP GPIO 4 * 5 * Copyright (C) 2003-2005 Nokia Corporation 6 * Written by Juha Yrjölä <juha.yrjola@nokia.com> 7 * 8 * Copyright (C) 2009 Texas Instruments 9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 10 */ 11 12 #include <linux/init.h> 13 #include <linux/module.h> 14 #include <linux/interrupt.h> 15 #include <linux/syscore_ops.h> 16 #include <linux/err.h> 17 #include <linux/clk.h> 18 #include <linux/io.h> 19 #include <linux/cpu_pm.h> 20 #include <linux/device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/pm.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/gpio/driver.h> 26 #include <linux/bitops.h> 27 #include <linux/platform_data/gpio-omap.h> 28 29 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF 30 31 struct gpio_regs { 32 u32 sysconfig; 33 u32 irqenable1; 34 u32 irqenable2; 35 u32 wake_en; 36 u32 ctrl; 37 u32 oe; 38 u32 leveldetect0; 39 u32 leveldetect1; 40 u32 risingdetect; 41 u32 fallingdetect; 42 u32 dataout; 43 u32 debounce; 44 u32 debounce_en; 45 }; 46 47 struct gpio_bank { 48 void __iomem *base; 49 const struct omap_gpio_reg_offs *regs; 50 51 int irq; 52 u32 non_wakeup_gpios; 53 u32 enabled_non_wakeup_gpios; 54 struct gpio_regs context; 55 u32 saved_datain; 56 u32 level_mask; 57 u32 toggle_mask; 58 raw_spinlock_t lock; 59 raw_spinlock_t wa_lock; 60 struct gpio_chip chip; 61 struct clk *dbck; 62 struct notifier_block nb; 63 unsigned int is_suspended:1; 64 unsigned int needs_resume:1; 65 u32 mod_usage; 66 u32 irq_usage; 67 u32 dbck_enable_mask; 68 bool dbck_enabled; 69 bool is_mpuio; 70 bool dbck_flag; 71 bool loses_context; 72 bool context_valid; 73 int stride; 74 u32 width; 75 int context_loss_count; 76 77 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); 78 int (*get_context_loss_count)(struct device *dev); 79 }; 80 81 #define GPIO_MOD_CTRL_BIT BIT(0) 82 83 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) 84 #define LINE_USED(line, offset) (line & (BIT(offset))) 85 86 static void omap_gpio_unmask_irq(struct irq_data *d); 87 88 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) 89 { 90 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 91 return gpiochip_get_data(chip); 92 } 93 94 static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set) 95 { 96 u32 val = readl_relaxed(reg); 97 98 if (set) 99 val |= mask; 100 else 101 val &= ~mask; 102 103 writel_relaxed(val, reg); 104 105 return val; 106 } 107 108 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, 109 int is_input) 110 { 111 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, 112 BIT(gpio), is_input); 113 } 114 115 116 /* set data out value using dedicate set/clear register */ 117 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, 118 int enable) 119 { 120 void __iomem *reg = bank->base; 121 u32 l = BIT(offset); 122 123 if (enable) { 124 reg += bank->regs->set_dataout; 125 bank->context.dataout |= l; 126 } else { 127 reg += bank->regs->clr_dataout; 128 bank->context.dataout &= ~l; 129 } 130 131 writel_relaxed(l, reg); 132 } 133 134 /* set data out value using mask register */ 135 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, 136 int enable) 137 { 138 bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout, 139 BIT(offset), enable); 140 } 141 142 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) 143 { 144 if (bank->dbck_enable_mask && !bank->dbck_enabled) { 145 clk_enable(bank->dbck); 146 bank->dbck_enabled = true; 147 148 writel_relaxed(bank->dbck_enable_mask, 149 bank->base + bank->regs->debounce_en); 150 } 151 } 152 153 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) 154 { 155 if (bank->dbck_enable_mask && bank->dbck_enabled) { 156 /* 157 * Disable debounce before cutting it's clock. If debounce is 158 * enabled but the clock is not, GPIO module seems to be unable 159 * to detect events and generate interrupts at least on OMAP3. 160 */ 161 writel_relaxed(0, bank->base + bank->regs->debounce_en); 162 163 clk_disable(bank->dbck); 164 bank->dbck_enabled = false; 165 } 166 } 167 168 /** 169 * omap2_set_gpio_debounce - low level gpio debounce time 170 * @bank: the gpio bank we're acting upon 171 * @offset: the gpio number on this @bank 172 * @debounce: debounce time to use 173 * 174 * OMAP's debounce time is in 31us steps 175 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31 176 * so we need to convert and round up to the closest unit. 177 * 178 * Return: 0 on success, negative error otherwise. 179 */ 180 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, 181 unsigned debounce) 182 { 183 u32 val; 184 u32 l; 185 bool enable = !!debounce; 186 187 if (!bank->dbck_flag) 188 return -ENOTSUPP; 189 190 if (enable) { 191 debounce = DIV_ROUND_UP(debounce, 31) - 1; 192 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce) 193 return -EINVAL; 194 } 195 196 l = BIT(offset); 197 198 clk_enable(bank->dbck); 199 writel_relaxed(debounce, bank->base + bank->regs->debounce); 200 201 val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable); 202 bank->dbck_enable_mask = val; 203 204 clk_disable(bank->dbck); 205 /* 206 * Enable debounce clock per module. 207 * This call is mandatory because in omap_gpio_request() when 208 * *_runtime_get_sync() is called, _gpio_dbck_enable() within 209 * runtime callbck fails to turn on dbck because dbck_enable_mask 210 * used within _gpio_dbck_enable() is still not initialized at 211 * that point. Therefore we have to enable dbck here. 212 */ 213 omap_gpio_dbck_enable(bank); 214 if (bank->dbck_enable_mask) { 215 bank->context.debounce = debounce; 216 bank->context.debounce_en = val; 217 } 218 219 return 0; 220 } 221 222 /** 223 * omap_clear_gpio_debounce - clear debounce settings for a gpio 224 * @bank: the gpio bank we're acting upon 225 * @offset: the gpio number on this @bank 226 * 227 * If a gpio is using debounce, then clear the debounce enable bit and if 228 * this is the only gpio in this bank using debounce, then clear the debounce 229 * time too. The debounce clock will also be disabled when calling this function 230 * if this is the only gpio in the bank using debounce. 231 */ 232 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) 233 { 234 u32 gpio_bit = BIT(offset); 235 236 if (!bank->dbck_flag) 237 return; 238 239 if (!(bank->dbck_enable_mask & gpio_bit)) 240 return; 241 242 bank->dbck_enable_mask &= ~gpio_bit; 243 bank->context.debounce_en &= ~gpio_bit; 244 writel_relaxed(bank->context.debounce_en, 245 bank->base + bank->regs->debounce_en); 246 247 if (!bank->dbck_enable_mask) { 248 bank->context.debounce = 0; 249 writel_relaxed(bank->context.debounce, bank->base + 250 bank->regs->debounce); 251 clk_disable(bank->dbck); 252 bank->dbck_enabled = false; 253 } 254 } 255 256 /* 257 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain. 258 * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs 259 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none 260 * are capable waking up the system from off mode. 261 */ 262 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask) 263 { 264 u32 no_wake = bank->non_wakeup_gpios; 265 266 if (no_wake) 267 return !!(~no_wake & gpio_mask); 268 269 return false; 270 } 271 272 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, 273 unsigned trigger) 274 { 275 void __iomem *base = bank->base; 276 u32 gpio_bit = BIT(gpio); 277 278 omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit, 279 trigger & IRQ_TYPE_LEVEL_LOW); 280 omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit, 281 trigger & IRQ_TYPE_LEVEL_HIGH); 282 283 /* 284 * We need the edge detection enabled for to allow the GPIO block 285 * to be woken from idle state. Set the appropriate edge detection 286 * in addition to the level detection. 287 */ 288 omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit, 289 trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)); 290 omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit, 291 trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)); 292 293 bank->context.leveldetect0 = 294 readl_relaxed(bank->base + bank->regs->leveldetect0); 295 bank->context.leveldetect1 = 296 readl_relaxed(bank->base + bank->regs->leveldetect1); 297 bank->context.risingdetect = 298 readl_relaxed(bank->base + bank->regs->risingdetect); 299 bank->context.fallingdetect = 300 readl_relaxed(bank->base + bank->regs->fallingdetect); 301 302 bank->level_mask = bank->context.leveldetect0 | 303 bank->context.leveldetect1; 304 305 /* This part needs to be executed always for OMAP{34xx, 44xx} */ 306 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) { 307 /* 308 * Log the edge gpio and manually trigger the IRQ 309 * after resume if the input level changes 310 * to avoid irq lost during PER RET/OFF mode 311 * Applies for omap2 non-wakeup gpio and all omap3 gpios 312 */ 313 if (trigger & IRQ_TYPE_EDGE_BOTH) 314 bank->enabled_non_wakeup_gpios |= gpio_bit; 315 else 316 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 317 } 318 } 319 320 /* 321 * This only applies to chips that can't do both rising and falling edge 322 * detection at once. For all other chips, this function is a noop. 323 */ 324 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) 325 { 326 if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) { 327 void __iomem *reg = bank->base + bank->regs->irqctrl; 328 329 writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg); 330 } 331 } 332 333 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, 334 unsigned trigger) 335 { 336 void __iomem *reg = bank->base; 337 u32 l = 0; 338 339 if (bank->regs->leveldetect0 && bank->regs->wkup_en) { 340 omap_set_gpio_trigger(bank, gpio, trigger); 341 } else if (bank->regs->irqctrl) { 342 reg += bank->regs->irqctrl; 343 344 l = readl_relaxed(reg); 345 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 346 bank->toggle_mask |= BIT(gpio); 347 if (trigger & IRQ_TYPE_EDGE_RISING) 348 l |= BIT(gpio); 349 else if (trigger & IRQ_TYPE_EDGE_FALLING) 350 l &= ~(BIT(gpio)); 351 else 352 return -EINVAL; 353 354 writel_relaxed(l, reg); 355 } else if (bank->regs->edgectrl1) { 356 if (gpio & 0x08) 357 reg += bank->regs->edgectrl2; 358 else 359 reg += bank->regs->edgectrl1; 360 361 gpio &= 0x07; 362 l = readl_relaxed(reg); 363 l &= ~(3 << (gpio << 1)); 364 if (trigger & IRQ_TYPE_EDGE_RISING) 365 l |= 2 << (gpio << 1); 366 if (trigger & IRQ_TYPE_EDGE_FALLING) 367 l |= BIT(gpio << 1); 368 writel_relaxed(l, reg); 369 } 370 return 0; 371 } 372 373 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) 374 { 375 if (bank->regs->pinctrl) { 376 void __iomem *reg = bank->base + bank->regs->pinctrl; 377 378 /* Claim the pin for MPU */ 379 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); 380 } 381 382 if (bank->regs->ctrl && !BANK_USED(bank)) { 383 void __iomem *reg = bank->base + bank->regs->ctrl; 384 u32 ctrl; 385 386 ctrl = readl_relaxed(reg); 387 /* Module is enabled, clocks are not gated */ 388 ctrl &= ~GPIO_MOD_CTRL_BIT; 389 writel_relaxed(ctrl, reg); 390 bank->context.ctrl = ctrl; 391 } 392 } 393 394 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) 395 { 396 if (bank->regs->ctrl && !BANK_USED(bank)) { 397 void __iomem *reg = bank->base + bank->regs->ctrl; 398 u32 ctrl; 399 400 ctrl = readl_relaxed(reg); 401 /* Module is disabled, clocks are gated */ 402 ctrl |= GPIO_MOD_CTRL_BIT; 403 writel_relaxed(ctrl, reg); 404 bank->context.ctrl = ctrl; 405 } 406 } 407 408 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) 409 { 410 void __iomem *reg = bank->base + bank->regs->direction; 411 412 return readl_relaxed(reg) & BIT(offset); 413 } 414 415 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) 416 { 417 if (!LINE_USED(bank->mod_usage, offset)) { 418 omap_enable_gpio_module(bank, offset); 419 omap_set_gpio_direction(bank, offset, 1); 420 } 421 bank->irq_usage |= BIT(offset); 422 } 423 424 static int omap_gpio_irq_type(struct irq_data *d, unsigned type) 425 { 426 struct gpio_bank *bank = omap_irq_data_get_bank(d); 427 int retval; 428 unsigned long flags; 429 unsigned offset = d->hwirq; 430 431 if (type & ~IRQ_TYPE_SENSE_MASK) 432 return -EINVAL; 433 434 if (!bank->regs->leveldetect0 && 435 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) 436 return -EINVAL; 437 438 raw_spin_lock_irqsave(&bank->lock, flags); 439 retval = omap_set_gpio_triggering(bank, offset, type); 440 if (retval) { 441 raw_spin_unlock_irqrestore(&bank->lock, flags); 442 goto error; 443 } 444 omap_gpio_init_irq(bank, offset); 445 if (!omap_gpio_is_input(bank, offset)) { 446 raw_spin_unlock_irqrestore(&bank->lock, flags); 447 retval = -EINVAL; 448 goto error; 449 } 450 raw_spin_unlock_irqrestore(&bank->lock, flags); 451 452 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 453 irq_set_handler_locked(d, handle_level_irq); 454 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 455 /* 456 * Edge IRQs are already cleared/acked in irq_handler and 457 * not need to be masked, as result handle_edge_irq() 458 * logic is excessed here and may cause lose of interrupts. 459 * So just use handle_simple_irq. 460 */ 461 irq_set_handler_locked(d, handle_simple_irq); 462 463 return 0; 464 465 error: 466 return retval; 467 } 468 469 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 470 { 471 void __iomem *reg = bank->base; 472 473 reg += bank->regs->irqstatus; 474 writel_relaxed(gpio_mask, reg); 475 476 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 477 if (bank->regs->irqstatus2) { 478 reg = bank->base + bank->regs->irqstatus2; 479 writel_relaxed(gpio_mask, reg); 480 } 481 482 /* Flush posted write for the irq status to avoid spurious interrupts */ 483 readl_relaxed(reg); 484 } 485 486 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, 487 unsigned offset) 488 { 489 omap_clear_gpio_irqbank(bank, BIT(offset)); 490 } 491 492 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) 493 { 494 void __iomem *reg = bank->base; 495 u32 l; 496 u32 mask = (BIT(bank->width)) - 1; 497 498 reg += bank->regs->irqenable; 499 l = readl_relaxed(reg); 500 if (bank->regs->irqenable_inv) 501 l = ~l; 502 l &= mask; 503 return l; 504 } 505 506 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, 507 unsigned offset, int enable) 508 { 509 void __iomem *reg = bank->base; 510 u32 gpio_mask = BIT(offset); 511 512 if (bank->regs->set_irqenable && bank->regs->clr_irqenable) { 513 if (enable) { 514 reg += bank->regs->set_irqenable; 515 bank->context.irqenable1 |= gpio_mask; 516 } else { 517 reg += bank->regs->clr_irqenable; 518 bank->context.irqenable1 &= ~gpio_mask; 519 } 520 writel_relaxed(gpio_mask, reg); 521 } else { 522 bank->context.irqenable1 = 523 omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask, 524 enable ^ bank->regs->irqenable_inv); 525 } 526 527 /* 528 * Program GPIO wakeup along with IRQ enable to satisfy OMAP4430 TRM 529 * note requiring correlation between the IRQ enable registers and 530 * the wakeup registers. In any case, we want wakeup from idle 531 * enabled for the GPIOs which support this feature. 532 */ 533 if (bank->regs->wkup_en && 534 (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) { 535 bank->context.wake_en = 536 omap_gpio_rmw(bank->base + bank->regs->wkup_en, 537 gpio_mask, enable); 538 } 539 } 540 541 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ 542 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) 543 { 544 struct gpio_bank *bank = omap_irq_data_get_bank(d); 545 546 return irq_set_irq_wake(bank->irq, enable); 547 } 548 549 /* 550 * We need to unmask the GPIO bank interrupt as soon as possible to 551 * avoid missing GPIO interrupts for other lines in the bank. 552 * Then we need to mask-read-clear-unmask the triggered GPIO lines 553 * in the bank to avoid missing nested interrupts for a GPIO line. 554 * If we wait to unmask individual GPIO lines in the bank after the 555 * line's interrupt handler has been run, we may miss some nested 556 * interrupts. 557 */ 558 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) 559 { 560 void __iomem *isr_reg = NULL; 561 u32 enabled, isr, edge; 562 unsigned int bit; 563 struct gpio_bank *bank = gpiobank; 564 unsigned long wa_lock_flags; 565 unsigned long lock_flags; 566 567 isr_reg = bank->base + bank->regs->irqstatus; 568 if (WARN_ON(!isr_reg)) 569 goto exit; 570 571 if (WARN_ONCE(!pm_runtime_active(bank->chip.parent), 572 "gpio irq%i while runtime suspended?\n", irq)) 573 return IRQ_NONE; 574 575 while (1) { 576 raw_spin_lock_irqsave(&bank->lock, lock_flags); 577 578 enabled = omap_get_gpio_irqbank_mask(bank); 579 isr = readl_relaxed(isr_reg) & enabled; 580 581 /* 582 * Clear edge sensitive interrupts before calling handler(s) 583 * so subsequent edge transitions are not missed while the 584 * handlers are running. 585 */ 586 edge = isr & ~bank->level_mask; 587 if (edge) 588 omap_clear_gpio_irqbank(bank, edge); 589 590 raw_spin_unlock_irqrestore(&bank->lock, lock_flags); 591 592 if (!isr) 593 break; 594 595 while (isr) { 596 bit = __ffs(isr); 597 isr &= ~(BIT(bit)); 598 599 raw_spin_lock_irqsave(&bank->lock, lock_flags); 600 /* 601 * Some chips can't respond to both rising and falling 602 * at the same time. If this irq was requested with 603 * both flags, we need to flip the ICR data for the IRQ 604 * to respond to the IRQ for the opposite direction. 605 * This will be indicated in the bank toggle_mask. 606 */ 607 if (bank->toggle_mask & (BIT(bit))) 608 omap_toggle_gpio_edge_triggering(bank, bit); 609 610 raw_spin_unlock_irqrestore(&bank->lock, lock_flags); 611 612 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); 613 614 generic_handle_domain_irq(bank->chip.irq.domain, bit); 615 616 raw_spin_unlock_irqrestore(&bank->wa_lock, 617 wa_lock_flags); 618 } 619 } 620 exit: 621 return IRQ_HANDLED; 622 } 623 624 static unsigned int omap_gpio_irq_startup(struct irq_data *d) 625 { 626 struct gpio_bank *bank = omap_irq_data_get_bank(d); 627 unsigned long flags; 628 unsigned offset = d->hwirq; 629 630 raw_spin_lock_irqsave(&bank->lock, flags); 631 632 if (!LINE_USED(bank->mod_usage, offset)) 633 omap_set_gpio_direction(bank, offset, 1); 634 omap_enable_gpio_module(bank, offset); 635 bank->irq_usage |= BIT(offset); 636 637 raw_spin_unlock_irqrestore(&bank->lock, flags); 638 omap_gpio_unmask_irq(d); 639 640 return 0; 641 } 642 643 static void omap_gpio_irq_shutdown(struct irq_data *d) 644 { 645 struct gpio_bank *bank = omap_irq_data_get_bank(d); 646 unsigned long flags; 647 unsigned offset = d->hwirq; 648 649 raw_spin_lock_irqsave(&bank->lock, flags); 650 bank->irq_usage &= ~(BIT(offset)); 651 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); 652 omap_clear_gpio_irqstatus(bank, offset); 653 omap_set_gpio_irqenable(bank, offset, 0); 654 if (!LINE_USED(bank->mod_usage, offset)) 655 omap_clear_gpio_debounce(bank, offset); 656 omap_disable_gpio_module(bank, offset); 657 raw_spin_unlock_irqrestore(&bank->lock, flags); 658 } 659 660 static void omap_gpio_irq_bus_lock(struct irq_data *data) 661 { 662 struct gpio_bank *bank = omap_irq_data_get_bank(data); 663 664 pm_runtime_get_sync(bank->chip.parent); 665 } 666 667 static void gpio_irq_bus_sync_unlock(struct irq_data *data) 668 { 669 struct gpio_bank *bank = omap_irq_data_get_bank(data); 670 671 pm_runtime_put(bank->chip.parent); 672 } 673 674 static void omap_gpio_mask_irq(struct irq_data *d) 675 { 676 struct gpio_bank *bank = omap_irq_data_get_bank(d); 677 unsigned offset = d->hwirq; 678 unsigned long flags; 679 680 raw_spin_lock_irqsave(&bank->lock, flags); 681 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); 682 omap_set_gpio_irqenable(bank, offset, 0); 683 raw_spin_unlock_irqrestore(&bank->lock, flags); 684 } 685 686 static void omap_gpio_unmask_irq(struct irq_data *d) 687 { 688 struct gpio_bank *bank = omap_irq_data_get_bank(d); 689 unsigned offset = d->hwirq; 690 u32 trigger = irqd_get_trigger_type(d); 691 unsigned long flags; 692 693 raw_spin_lock_irqsave(&bank->lock, flags); 694 omap_set_gpio_irqenable(bank, offset, 1); 695 696 /* 697 * For level-triggered GPIOs, clearing must be done after the source 698 * is cleared, thus after the handler has run. OMAP4 needs this done 699 * after enabing the interrupt to clear the wakeup status. 700 */ 701 if (bank->regs->leveldetect0 && bank->regs->wkup_en && 702 trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 703 omap_clear_gpio_irqstatus(bank, offset); 704 705 if (trigger) 706 omap_set_gpio_triggering(bank, offset, trigger); 707 708 raw_spin_unlock_irqrestore(&bank->lock, flags); 709 } 710 711 /*---------------------------------------------------------------------*/ 712 713 static int omap_mpuio_suspend_noirq(struct device *dev) 714 { 715 struct gpio_bank *bank = dev_get_drvdata(dev); 716 void __iomem *mask_reg = bank->base + 717 OMAP_MPUIO_GPIO_MASKIT / bank->stride; 718 unsigned long flags; 719 720 raw_spin_lock_irqsave(&bank->lock, flags); 721 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); 722 raw_spin_unlock_irqrestore(&bank->lock, flags); 723 724 return 0; 725 } 726 727 static int omap_mpuio_resume_noirq(struct device *dev) 728 { 729 struct gpio_bank *bank = dev_get_drvdata(dev); 730 void __iomem *mask_reg = bank->base + 731 OMAP_MPUIO_GPIO_MASKIT / bank->stride; 732 unsigned long flags; 733 734 raw_spin_lock_irqsave(&bank->lock, flags); 735 writel_relaxed(bank->context.wake_en, mask_reg); 736 raw_spin_unlock_irqrestore(&bank->lock, flags); 737 738 return 0; 739 } 740 741 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { 742 .suspend_noirq = omap_mpuio_suspend_noirq, 743 .resume_noirq = omap_mpuio_resume_noirq, 744 }; 745 746 /* use platform_driver for this. */ 747 static struct platform_driver omap_mpuio_driver = { 748 .driver = { 749 .name = "mpuio", 750 .pm = &omap_mpuio_dev_pm_ops, 751 }, 752 }; 753 754 static struct platform_device omap_mpuio_device = { 755 .name = "mpuio", 756 .id = -1, 757 .dev = { 758 .driver = &omap_mpuio_driver.driver, 759 } 760 /* could list the /proc/iomem resources */ 761 }; 762 763 static inline void omap_mpuio_init(struct gpio_bank *bank) 764 { 765 platform_set_drvdata(&omap_mpuio_device, bank); 766 767 if (platform_driver_register(&omap_mpuio_driver) == 0) 768 (void) platform_device_register(&omap_mpuio_device); 769 } 770 771 /*---------------------------------------------------------------------*/ 772 773 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) 774 { 775 struct gpio_bank *bank = gpiochip_get_data(chip); 776 unsigned long flags; 777 778 pm_runtime_get_sync(chip->parent); 779 780 raw_spin_lock_irqsave(&bank->lock, flags); 781 omap_enable_gpio_module(bank, offset); 782 bank->mod_usage |= BIT(offset); 783 raw_spin_unlock_irqrestore(&bank->lock, flags); 784 785 return 0; 786 } 787 788 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) 789 { 790 struct gpio_bank *bank = gpiochip_get_data(chip); 791 unsigned long flags; 792 793 raw_spin_lock_irqsave(&bank->lock, flags); 794 bank->mod_usage &= ~(BIT(offset)); 795 if (!LINE_USED(bank->irq_usage, offset)) { 796 omap_set_gpio_direction(bank, offset, 1); 797 omap_clear_gpio_debounce(bank, offset); 798 } 799 omap_disable_gpio_module(bank, offset); 800 raw_spin_unlock_irqrestore(&bank->lock, flags); 801 802 pm_runtime_put(chip->parent); 803 } 804 805 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 806 { 807 struct gpio_bank *bank = gpiochip_get_data(chip); 808 809 if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset)) 810 return GPIO_LINE_DIRECTION_IN; 811 812 return GPIO_LINE_DIRECTION_OUT; 813 } 814 815 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) 816 { 817 struct gpio_bank *bank; 818 unsigned long flags; 819 820 bank = gpiochip_get_data(chip); 821 raw_spin_lock_irqsave(&bank->lock, flags); 822 omap_set_gpio_direction(bank, offset, 1); 823 raw_spin_unlock_irqrestore(&bank->lock, flags); 824 return 0; 825 } 826 827 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) 828 { 829 struct gpio_bank *bank = gpiochip_get_data(chip); 830 void __iomem *reg; 831 832 if (omap_gpio_is_input(bank, offset)) 833 reg = bank->base + bank->regs->datain; 834 else 835 reg = bank->base + bank->regs->dataout; 836 837 return (readl_relaxed(reg) & BIT(offset)) != 0; 838 } 839 840 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) 841 { 842 struct gpio_bank *bank; 843 unsigned long flags; 844 845 bank = gpiochip_get_data(chip); 846 raw_spin_lock_irqsave(&bank->lock, flags); 847 bank->set_dataout(bank, offset, value); 848 omap_set_gpio_direction(bank, offset, 0); 849 raw_spin_unlock_irqrestore(&bank->lock, flags); 850 return 0; 851 } 852 853 static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, 854 unsigned long *bits) 855 { 856 struct gpio_bank *bank = gpiochip_get_data(chip); 857 void __iomem *base = bank->base; 858 u32 direction, m, val = 0; 859 860 direction = readl_relaxed(base + bank->regs->direction); 861 862 m = direction & *mask; 863 if (m) 864 val |= readl_relaxed(base + bank->regs->datain) & m; 865 866 m = ~direction & *mask; 867 if (m) 868 val |= readl_relaxed(base + bank->regs->dataout) & m; 869 870 *bits = val; 871 872 return 0; 873 } 874 875 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, 876 unsigned debounce) 877 { 878 struct gpio_bank *bank; 879 unsigned long flags; 880 int ret; 881 882 bank = gpiochip_get_data(chip); 883 884 raw_spin_lock_irqsave(&bank->lock, flags); 885 ret = omap2_set_gpio_debounce(bank, offset, debounce); 886 raw_spin_unlock_irqrestore(&bank->lock, flags); 887 888 if (ret) 889 dev_info(chip->parent, 890 "Could not set line %u debounce to %u microseconds (%d)", 891 offset, debounce, ret); 892 893 return ret; 894 } 895 896 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset, 897 unsigned long config) 898 { 899 u32 debounce; 900 int ret = -ENOTSUPP; 901 902 switch (pinconf_to_config_param(config)) { 903 case PIN_CONFIG_BIAS_DISABLE: 904 case PIN_CONFIG_BIAS_PULL_UP: 905 case PIN_CONFIG_BIAS_PULL_DOWN: 906 ret = gpiochip_generic_config(chip, offset, config); 907 break; 908 case PIN_CONFIG_INPUT_DEBOUNCE: 909 debounce = pinconf_to_config_argument(config); 910 ret = omap_gpio_debounce(chip, offset, debounce); 911 break; 912 default: 913 break; 914 } 915 916 return ret; 917 } 918 919 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 920 { 921 struct gpio_bank *bank; 922 unsigned long flags; 923 924 bank = gpiochip_get_data(chip); 925 raw_spin_lock_irqsave(&bank->lock, flags); 926 bank->set_dataout(bank, offset, value); 927 raw_spin_unlock_irqrestore(&bank->lock, flags); 928 } 929 930 static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, 931 unsigned long *bits) 932 { 933 struct gpio_bank *bank = gpiochip_get_data(chip); 934 void __iomem *reg = bank->base + bank->regs->dataout; 935 unsigned long flags; 936 u32 l; 937 938 raw_spin_lock_irqsave(&bank->lock, flags); 939 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask); 940 writel_relaxed(l, reg); 941 bank->context.dataout = l; 942 raw_spin_unlock_irqrestore(&bank->lock, flags); 943 } 944 945 /*---------------------------------------------------------------------*/ 946 947 static void omap_gpio_show_rev(struct gpio_bank *bank) 948 { 949 static bool called; 950 u32 rev; 951 952 if (called || bank->regs->revision == USHRT_MAX) 953 return; 954 955 rev = readw_relaxed(bank->base + bank->regs->revision); 956 pr_info("OMAP GPIO hardware version %d.%d\n", 957 (rev >> 4) & 0x0f, rev & 0x0f); 958 959 called = true; 960 } 961 962 static void omap_gpio_mod_init(struct gpio_bank *bank) 963 { 964 void __iomem *base = bank->base; 965 u32 l = 0xffffffff; 966 967 if (bank->width == 16) 968 l = 0xffff; 969 970 if (bank->is_mpuio) { 971 writel_relaxed(l, bank->base + bank->regs->irqenable); 972 return; 973 } 974 975 omap_gpio_rmw(base + bank->regs->irqenable, l, 976 bank->regs->irqenable_inv); 977 omap_gpio_rmw(base + bank->regs->irqstatus, l, 978 !bank->regs->irqenable_inv); 979 if (bank->regs->debounce_en) 980 writel_relaxed(0, base + bank->regs->debounce_en); 981 982 /* Save OE default value (0xffffffff) in the context */ 983 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); 984 /* Initialize interface clk ungated, module enabled */ 985 if (bank->regs->ctrl) 986 writel_relaxed(0, base + bank->regs->ctrl); 987 } 988 989 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc, 990 struct device *pm_dev) 991 { 992 struct gpio_irq_chip *irq; 993 static int gpio; 994 const char *label; 995 int irq_base = 0; 996 int ret; 997 998 /* 999 * REVISIT eventually switch from OMAP-specific gpio structs 1000 * over to the generic ones 1001 */ 1002 bank->chip.request = omap_gpio_request; 1003 bank->chip.free = omap_gpio_free; 1004 bank->chip.get_direction = omap_gpio_get_direction; 1005 bank->chip.direction_input = omap_gpio_input; 1006 bank->chip.get = omap_gpio_get; 1007 bank->chip.get_multiple = omap_gpio_get_multiple; 1008 bank->chip.direction_output = omap_gpio_output; 1009 bank->chip.set_config = omap_gpio_set_config; 1010 bank->chip.set = omap_gpio_set; 1011 bank->chip.set_multiple = omap_gpio_set_multiple; 1012 if (bank->is_mpuio) { 1013 bank->chip.label = "mpuio"; 1014 if (bank->regs->wkup_en) 1015 bank->chip.parent = &omap_mpuio_device.dev; 1016 bank->chip.base = OMAP_MPUIO(0); 1017 } else { 1018 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", 1019 gpio, gpio + bank->width - 1); 1020 if (!label) 1021 return -ENOMEM; 1022 bank->chip.label = label; 1023 bank->chip.base = -1; 1024 } 1025 bank->chip.ngpio = bank->width; 1026 1027 #ifdef CONFIG_ARCH_OMAP1 1028 /* 1029 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop 1030 * irq_alloc_descs() since a base IRQ offset will no longer be needed. 1031 */ 1032 irq_base = devm_irq_alloc_descs(bank->chip.parent, 1033 -1, 0, bank->width, 0); 1034 if (irq_base < 0) { 1035 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n"); 1036 return -ENODEV; 1037 } 1038 #endif 1039 1040 /* MPUIO is a bit different, reading IRQ status clears it */ 1041 if (bank->is_mpuio && !bank->regs->wkup_en) 1042 irqc->irq_set_wake = NULL; 1043 1044 irq = &bank->chip.irq; 1045 irq->chip = irqc; 1046 irq->handler = handle_bad_irq; 1047 irq->default_type = IRQ_TYPE_NONE; 1048 irq->num_parents = 1; 1049 irq->parents = &bank->irq; 1050 irq->first = irq_base; 1051 1052 ret = gpiochip_add_data(&bank->chip, bank); 1053 if (ret) 1054 return dev_err_probe(bank->chip.parent, ret, "Could not register gpio chip\n"); 1055 1056 irq_domain_set_pm_device(bank->chip.irq.domain, pm_dev); 1057 ret = devm_request_irq(bank->chip.parent, bank->irq, 1058 omap_gpio_irq_handler, 1059 0, dev_name(bank->chip.parent), bank); 1060 if (ret) 1061 gpiochip_remove(&bank->chip); 1062 1063 if (!bank->is_mpuio) 1064 gpio += bank->width; 1065 1066 return ret; 1067 } 1068 1069 static void omap_gpio_init_context(struct gpio_bank *p) 1070 { 1071 const struct omap_gpio_reg_offs *regs = p->regs; 1072 void __iomem *base = p->base; 1073 1074 p->context.sysconfig = readl_relaxed(base + regs->sysconfig); 1075 p->context.ctrl = readl_relaxed(base + regs->ctrl); 1076 p->context.oe = readl_relaxed(base + regs->direction); 1077 p->context.wake_en = readl_relaxed(base + regs->wkup_en); 1078 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); 1079 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); 1080 p->context.risingdetect = readl_relaxed(base + regs->risingdetect); 1081 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); 1082 p->context.irqenable1 = readl_relaxed(base + regs->irqenable); 1083 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); 1084 p->context.dataout = readl_relaxed(base + regs->dataout); 1085 1086 p->context_valid = true; 1087 } 1088 1089 static void omap_gpio_restore_context(struct gpio_bank *bank) 1090 { 1091 const struct omap_gpio_reg_offs *regs = bank->regs; 1092 void __iomem *base = bank->base; 1093 1094 writel_relaxed(bank->context.sysconfig, base + regs->sysconfig); 1095 writel_relaxed(bank->context.wake_en, base + regs->wkup_en); 1096 writel_relaxed(bank->context.ctrl, base + regs->ctrl); 1097 writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0); 1098 writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1); 1099 writel_relaxed(bank->context.risingdetect, base + regs->risingdetect); 1100 writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect); 1101 writel_relaxed(bank->context.dataout, base + regs->dataout); 1102 writel_relaxed(bank->context.oe, base + regs->direction); 1103 1104 if (bank->dbck_enable_mask) { 1105 writel_relaxed(bank->context.debounce, base + regs->debounce); 1106 writel_relaxed(bank->context.debounce_en, 1107 base + regs->debounce_en); 1108 } 1109 1110 writel_relaxed(bank->context.irqenable1, base + regs->irqenable); 1111 writel_relaxed(bank->context.irqenable2, base + regs->irqenable2); 1112 } 1113 1114 static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context) 1115 { 1116 struct device *dev = bank->chip.parent; 1117 void __iomem *base = bank->base; 1118 u32 mask, nowake; 1119 1120 bank->saved_datain = readl_relaxed(base + bank->regs->datain); 1121 1122 /* Save syconfig, it's runtime value can be different from init value */ 1123 if (bank->loses_context) 1124 bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig); 1125 1126 if (!bank->enabled_non_wakeup_gpios) 1127 goto update_gpio_context_count; 1128 1129 /* Check for pending EDGE_FALLING, ignore EDGE_BOTH */ 1130 mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect; 1131 mask &= ~bank->context.risingdetect; 1132 bank->saved_datain |= mask; 1133 1134 /* Check for pending EDGE_RISING, ignore EDGE_BOTH */ 1135 mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect; 1136 mask &= ~bank->context.fallingdetect; 1137 bank->saved_datain &= ~mask; 1138 1139 if (!may_lose_context) 1140 goto update_gpio_context_count; 1141 1142 /* 1143 * If going to OFF, remove triggering for all wkup domain 1144 * non-wakeup GPIOs. Otherwise spurious IRQs will be 1145 * generated. See OMAP2420 Errata item 1.101. 1146 */ 1147 if (!bank->loses_context && bank->enabled_non_wakeup_gpios) { 1148 nowake = bank->enabled_non_wakeup_gpios; 1149 omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake); 1150 omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake); 1151 } 1152 1153 update_gpio_context_count: 1154 if (bank->get_context_loss_count) 1155 bank->context_loss_count = 1156 bank->get_context_loss_count(dev); 1157 1158 omap_gpio_dbck_disable(bank); 1159 } 1160 1161 static void omap_gpio_unidle(struct gpio_bank *bank) 1162 { 1163 struct device *dev = bank->chip.parent; 1164 u32 l = 0, gen, gen0, gen1; 1165 int c; 1166 1167 /* 1168 * On the first resume during the probe, the context has not 1169 * been initialised and so initialise it now. Also initialise 1170 * the context loss count. 1171 */ 1172 if (bank->loses_context && !bank->context_valid) { 1173 omap_gpio_init_context(bank); 1174 1175 if (bank->get_context_loss_count) 1176 bank->context_loss_count = 1177 bank->get_context_loss_count(dev); 1178 } 1179 1180 omap_gpio_dbck_enable(bank); 1181 1182 if (bank->loses_context) { 1183 if (!bank->get_context_loss_count) { 1184 omap_gpio_restore_context(bank); 1185 } else { 1186 c = bank->get_context_loss_count(dev); 1187 if (c != bank->context_loss_count) { 1188 omap_gpio_restore_context(bank); 1189 } else { 1190 return; 1191 } 1192 } 1193 } else { 1194 /* Restore changes done for OMAP2420 errata 1.101 */ 1195 writel_relaxed(bank->context.fallingdetect, 1196 bank->base + bank->regs->fallingdetect); 1197 writel_relaxed(bank->context.risingdetect, 1198 bank->base + bank->regs->risingdetect); 1199 } 1200 1201 l = readl_relaxed(bank->base + bank->regs->datain); 1202 1203 /* 1204 * Check if any of the non-wakeup interrupt GPIOs have changed 1205 * state. If so, generate an IRQ by software. This is 1206 * horribly racy, but it's the best we can do to work around 1207 * this silicon bug. 1208 */ 1209 l ^= bank->saved_datain; 1210 l &= bank->enabled_non_wakeup_gpios; 1211 1212 /* 1213 * No need to generate IRQs for the rising edge for gpio IRQs 1214 * configured with falling edge only; and vice versa. 1215 */ 1216 gen0 = l & bank->context.fallingdetect; 1217 gen0 &= bank->saved_datain; 1218 1219 gen1 = l & bank->context.risingdetect; 1220 gen1 &= ~(bank->saved_datain); 1221 1222 /* FIXME: Consider GPIO IRQs with level detections properly! */ 1223 gen = l & (~(bank->context.fallingdetect) & 1224 ~(bank->context.risingdetect)); 1225 /* Consider all GPIO IRQs needed to be updated */ 1226 gen |= gen0 | gen1; 1227 1228 if (gen) { 1229 u32 old0, old1; 1230 1231 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); 1232 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); 1233 1234 if (!bank->regs->irqstatus_raw0) { 1235 writel_relaxed(old0 | gen, bank->base + 1236 bank->regs->leveldetect0); 1237 writel_relaxed(old1 | gen, bank->base + 1238 bank->regs->leveldetect1); 1239 } 1240 1241 if (bank->regs->irqstatus_raw0) { 1242 writel_relaxed(old0 | l, bank->base + 1243 bank->regs->leveldetect0); 1244 writel_relaxed(old1 | l, bank->base + 1245 bank->regs->leveldetect1); 1246 } 1247 writel_relaxed(old0, bank->base + bank->regs->leveldetect0); 1248 writel_relaxed(old1, bank->base + bank->regs->leveldetect1); 1249 } 1250 } 1251 1252 static int gpio_omap_cpu_notifier(struct notifier_block *nb, 1253 unsigned long cmd, void *v) 1254 { 1255 struct gpio_bank *bank; 1256 unsigned long flags; 1257 int ret = NOTIFY_OK; 1258 u32 isr, mask; 1259 1260 bank = container_of(nb, struct gpio_bank, nb); 1261 1262 raw_spin_lock_irqsave(&bank->lock, flags); 1263 if (bank->is_suspended) 1264 goto out_unlock; 1265 1266 switch (cmd) { 1267 case CPU_CLUSTER_PM_ENTER: 1268 mask = omap_get_gpio_irqbank_mask(bank); 1269 isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask; 1270 if (isr) { 1271 ret = NOTIFY_BAD; 1272 break; 1273 } 1274 omap_gpio_idle(bank, true); 1275 break; 1276 case CPU_CLUSTER_PM_ENTER_FAILED: 1277 case CPU_CLUSTER_PM_EXIT: 1278 omap_gpio_unidle(bank); 1279 break; 1280 } 1281 1282 out_unlock: 1283 raw_spin_unlock_irqrestore(&bank->lock, flags); 1284 1285 return ret; 1286 } 1287 1288 static const struct omap_gpio_reg_offs omap2_gpio_regs = { 1289 .revision = OMAP24XX_GPIO_REVISION, 1290 .sysconfig = OMAP24XX_GPIO_SYSCONFIG, 1291 .direction = OMAP24XX_GPIO_OE, 1292 .datain = OMAP24XX_GPIO_DATAIN, 1293 .dataout = OMAP24XX_GPIO_DATAOUT, 1294 .set_dataout = OMAP24XX_GPIO_SETDATAOUT, 1295 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, 1296 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, 1297 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, 1298 .irqenable = OMAP24XX_GPIO_IRQENABLE1, 1299 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, 1300 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, 1301 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, 1302 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, 1303 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, 1304 .ctrl = OMAP24XX_GPIO_CTRL, 1305 .wkup_en = OMAP24XX_GPIO_WAKE_EN, 1306 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, 1307 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, 1308 .risingdetect = OMAP24XX_GPIO_RISINGDETECT, 1309 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, 1310 }; 1311 1312 static const struct omap_gpio_reg_offs omap4_gpio_regs = { 1313 .revision = OMAP4_GPIO_REVISION, 1314 .sysconfig = OMAP4_GPIO_SYSCONFIG, 1315 .direction = OMAP4_GPIO_OE, 1316 .datain = OMAP4_GPIO_DATAIN, 1317 .dataout = OMAP4_GPIO_DATAOUT, 1318 .set_dataout = OMAP4_GPIO_SETDATAOUT, 1319 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, 1320 .irqstatus = OMAP4_GPIO_IRQSTATUS0, 1321 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, 1322 .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0, 1323 .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1, 1324 .irqenable = OMAP4_GPIO_IRQSTATUSSET0, 1325 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, 1326 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, 1327 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, 1328 .debounce = OMAP4_GPIO_DEBOUNCINGTIME, 1329 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, 1330 .ctrl = OMAP4_GPIO_CTRL, 1331 .wkup_en = OMAP4_GPIO_IRQWAKEN0, 1332 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, 1333 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, 1334 .risingdetect = OMAP4_GPIO_RISINGDETECT, 1335 .fallingdetect = OMAP4_GPIO_FALLINGDETECT, 1336 }; 1337 1338 static const struct omap_gpio_platform_data omap2_pdata = { 1339 .regs = &omap2_gpio_regs, 1340 .bank_width = 32, 1341 .dbck_flag = false, 1342 }; 1343 1344 static const struct omap_gpio_platform_data omap3_pdata = { 1345 .regs = &omap2_gpio_regs, 1346 .bank_width = 32, 1347 .dbck_flag = true, 1348 }; 1349 1350 static const struct omap_gpio_platform_data omap4_pdata = { 1351 .regs = &omap4_gpio_regs, 1352 .bank_width = 32, 1353 .dbck_flag = true, 1354 }; 1355 1356 static const struct of_device_id omap_gpio_match[] = { 1357 { 1358 .compatible = "ti,omap4-gpio", 1359 .data = &omap4_pdata, 1360 }, 1361 { 1362 .compatible = "ti,omap3-gpio", 1363 .data = &omap3_pdata, 1364 }, 1365 { 1366 .compatible = "ti,omap2-gpio", 1367 .data = &omap2_pdata, 1368 }, 1369 { }, 1370 }; 1371 MODULE_DEVICE_TABLE(of, omap_gpio_match); 1372 1373 static int omap_gpio_probe(struct platform_device *pdev) 1374 { 1375 struct device *dev = &pdev->dev; 1376 struct device_node *node = dev->of_node; 1377 const struct omap_gpio_platform_data *pdata; 1378 struct gpio_bank *bank; 1379 struct irq_chip *irqc; 1380 int ret; 1381 1382 pdata = device_get_match_data(dev); 1383 1384 pdata = pdata ?: dev_get_platdata(dev); 1385 if (!pdata) 1386 return -EINVAL; 1387 1388 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); 1389 if (!bank) 1390 return -ENOMEM; 1391 1392 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); 1393 if (!irqc) 1394 return -ENOMEM; 1395 1396 irqc->irq_startup = omap_gpio_irq_startup, 1397 irqc->irq_shutdown = omap_gpio_irq_shutdown, 1398 irqc->irq_ack = dummy_irq_chip.irq_ack, 1399 irqc->irq_mask = omap_gpio_mask_irq, 1400 irqc->irq_unmask = omap_gpio_unmask_irq, 1401 irqc->irq_set_type = omap_gpio_irq_type, 1402 irqc->irq_set_wake = omap_gpio_wake_enable, 1403 irqc->irq_bus_lock = omap_gpio_irq_bus_lock, 1404 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, 1405 irqc->name = dev_name(&pdev->dev); 1406 irqc->flags = IRQCHIP_MASK_ON_SUSPEND; 1407 1408 bank->irq = platform_get_irq(pdev, 0); 1409 if (bank->irq <= 0) { 1410 if (!bank->irq) 1411 bank->irq = -ENXIO; 1412 return dev_err_probe(dev, bank->irq, "can't get irq resource\n"); 1413 } 1414 1415 bank->chip.parent = dev; 1416 bank->chip.owner = THIS_MODULE; 1417 bank->dbck_flag = pdata->dbck_flag; 1418 bank->stride = pdata->bank_stride; 1419 bank->width = pdata->bank_width; 1420 bank->is_mpuio = pdata->is_mpuio; 1421 bank->non_wakeup_gpios = pdata->non_wakeup_gpios; 1422 bank->regs = pdata->regs; 1423 1424 if (node) { 1425 if (!of_property_read_bool(node, "ti,gpio-always-on")) 1426 bank->loses_context = true; 1427 } else { 1428 bank->loses_context = pdata->loses_context; 1429 1430 if (bank->loses_context) 1431 bank->get_context_loss_count = 1432 pdata->get_context_loss_count; 1433 } 1434 1435 if (bank->regs->set_dataout && bank->regs->clr_dataout) 1436 bank->set_dataout = omap_set_gpio_dataout_reg; 1437 else 1438 bank->set_dataout = omap_set_gpio_dataout_mask; 1439 1440 raw_spin_lock_init(&bank->lock); 1441 raw_spin_lock_init(&bank->wa_lock); 1442 1443 /* Static mapping, never released */ 1444 bank->base = devm_platform_ioremap_resource(pdev, 0); 1445 if (IS_ERR(bank->base)) { 1446 return PTR_ERR(bank->base); 1447 } 1448 1449 if (bank->dbck_flag) { 1450 bank->dbck = devm_clk_get(dev, "dbclk"); 1451 if (IS_ERR(bank->dbck)) { 1452 dev_err(dev, 1453 "Could not get gpio dbck. Disable debounce\n"); 1454 bank->dbck_flag = false; 1455 } else { 1456 clk_prepare(bank->dbck); 1457 } 1458 } 1459 1460 platform_set_drvdata(pdev, bank); 1461 1462 pm_runtime_enable(dev); 1463 pm_runtime_get_sync(dev); 1464 1465 if (bank->is_mpuio) 1466 omap_mpuio_init(bank); 1467 1468 omap_gpio_mod_init(bank); 1469 1470 ret = omap_gpio_chip_init(bank, irqc, dev); 1471 if (ret) { 1472 pm_runtime_put_sync(dev); 1473 pm_runtime_disable(dev); 1474 if (bank->dbck_flag) 1475 clk_unprepare(bank->dbck); 1476 return ret; 1477 } 1478 1479 omap_gpio_show_rev(bank); 1480 1481 bank->nb.notifier_call = gpio_omap_cpu_notifier; 1482 cpu_pm_register_notifier(&bank->nb); 1483 1484 pm_runtime_put(dev); 1485 1486 return 0; 1487 } 1488 1489 static int omap_gpio_remove(struct platform_device *pdev) 1490 { 1491 struct gpio_bank *bank = platform_get_drvdata(pdev); 1492 1493 cpu_pm_unregister_notifier(&bank->nb); 1494 gpiochip_remove(&bank->chip); 1495 pm_runtime_disable(&pdev->dev); 1496 if (bank->dbck_flag) 1497 clk_unprepare(bank->dbck); 1498 1499 return 0; 1500 } 1501 1502 static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev) 1503 { 1504 struct gpio_bank *bank = dev_get_drvdata(dev); 1505 unsigned long flags; 1506 1507 raw_spin_lock_irqsave(&bank->lock, flags); 1508 omap_gpio_idle(bank, true); 1509 bank->is_suspended = true; 1510 raw_spin_unlock_irqrestore(&bank->lock, flags); 1511 1512 return 0; 1513 } 1514 1515 static int __maybe_unused omap_gpio_runtime_resume(struct device *dev) 1516 { 1517 struct gpio_bank *bank = dev_get_drvdata(dev); 1518 unsigned long flags; 1519 1520 raw_spin_lock_irqsave(&bank->lock, flags); 1521 omap_gpio_unidle(bank); 1522 bank->is_suspended = false; 1523 raw_spin_unlock_irqrestore(&bank->lock, flags); 1524 1525 return 0; 1526 } 1527 1528 static int __maybe_unused omap_gpio_suspend(struct device *dev) 1529 { 1530 struct gpio_bank *bank = dev_get_drvdata(dev); 1531 1532 if (bank->is_suspended) 1533 return 0; 1534 1535 bank->needs_resume = 1; 1536 1537 return omap_gpio_runtime_suspend(dev); 1538 } 1539 1540 static int __maybe_unused omap_gpio_resume(struct device *dev) 1541 { 1542 struct gpio_bank *bank = dev_get_drvdata(dev); 1543 1544 if (!bank->needs_resume) 1545 return 0; 1546 1547 bank->needs_resume = 0; 1548 1549 return omap_gpio_runtime_resume(dev); 1550 } 1551 1552 static const struct dev_pm_ops gpio_pm_ops = { 1553 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, 1554 NULL) 1555 SET_LATE_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume) 1556 }; 1557 1558 static struct platform_driver omap_gpio_driver = { 1559 .probe = omap_gpio_probe, 1560 .remove = omap_gpio_remove, 1561 .driver = { 1562 .name = "omap_gpio", 1563 .pm = &gpio_pm_ops, 1564 .of_match_table = omap_gpio_match, 1565 }, 1566 }; 1567 1568 /* 1569 * gpio driver register needs to be done before 1570 * machine_init functions access gpio APIs. 1571 * Hence omap_gpio_drv_reg() is a postcore_initcall. 1572 */ 1573 static int __init omap_gpio_drv_reg(void) 1574 { 1575 return platform_driver_register(&omap_gpio_driver); 1576 } 1577 postcore_initcall(omap_gpio_drv_reg); 1578 1579 static void __exit omap_gpio_exit(void) 1580 { 1581 platform_driver_unregister(&omap_gpio_driver); 1582 } 1583 module_exit(omap_gpio_exit); 1584 1585 MODULE_DESCRIPTION("omap gpio driver"); 1586 MODULE_ALIAS("platform:gpio-omap"); 1587 MODULE_LICENSE("GPL v2"); 1588