1 /* 2 * Support functions for OMAP GPIO 3 * 4 * Copyright (C) 2003-2005 Nokia Corporation 5 * Written by Juha Yrjölä <juha.yrjola@nokia.com> 6 * 7 * Copyright (C) 2009 Texas Instruments 8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/interrupt.h> 18 #include <linux/syscore_ops.h> 19 #include <linux/err.h> 20 #include <linux/clk.h> 21 #include <linux/io.h> 22 #include <linux/cpu_pm.h> 23 #include <linux/device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/pm.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/gpio/driver.h> 29 #include <linux/bitops.h> 30 #include <linux/platform_data/gpio-omap.h> 31 32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF 33 34 #define OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER BIT(2) 35 36 struct gpio_regs { 37 u32 irqenable1; 38 u32 irqenable2; 39 u32 wake_en; 40 u32 ctrl; 41 u32 oe; 42 u32 leveldetect0; 43 u32 leveldetect1; 44 u32 risingdetect; 45 u32 fallingdetect; 46 u32 dataout; 47 u32 debounce; 48 u32 debounce_en; 49 }; 50 51 struct gpio_bank; 52 53 struct gpio_omap_funcs { 54 void (*idle_enable_level_quirk)(struct gpio_bank *bank); 55 void (*idle_disable_level_quirk)(struct gpio_bank *bank); 56 }; 57 58 struct gpio_bank { 59 struct list_head node; 60 void __iomem *base; 61 int irq; 62 u32 non_wakeup_gpios; 63 u32 enabled_non_wakeup_gpios; 64 struct gpio_regs context; 65 struct gpio_omap_funcs funcs; 66 u32 saved_datain; 67 u32 level_mask; 68 u32 toggle_mask; 69 raw_spinlock_t lock; 70 raw_spinlock_t wa_lock; 71 struct gpio_chip chip; 72 struct clk *dbck; 73 struct notifier_block nb; 74 unsigned int is_suspended:1; 75 u32 mod_usage; 76 u32 irq_usage; 77 u32 dbck_enable_mask; 78 bool dbck_enabled; 79 bool is_mpuio; 80 bool dbck_flag; 81 bool loses_context; 82 bool context_valid; 83 int stride; 84 u32 width; 85 int context_loss_count; 86 bool workaround_enabled; 87 u32 quirks; 88 89 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); 90 void (*set_dataout_multiple)(struct gpio_bank *bank, 91 unsigned long *mask, unsigned long *bits); 92 int (*get_context_loss_count)(struct device *dev); 93 94 struct omap_gpio_reg_offs *regs; 95 }; 96 97 #define GPIO_MOD_CTRL_BIT BIT(0) 98 99 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) 100 #define LINE_USED(line, offset) (line & (BIT(offset))) 101 102 static void omap_gpio_unmask_irq(struct irq_data *d); 103 104 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) 105 { 106 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 107 return gpiochip_get_data(chip); 108 } 109 110 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, 111 int is_input) 112 { 113 void __iomem *reg = bank->base; 114 u32 l; 115 116 reg += bank->regs->direction; 117 l = readl_relaxed(reg); 118 if (is_input) 119 l |= BIT(gpio); 120 else 121 l &= ~(BIT(gpio)); 122 writel_relaxed(l, reg); 123 bank->context.oe = l; 124 } 125 126 127 /* set data out value using dedicate set/clear register */ 128 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, 129 int enable) 130 { 131 void __iomem *reg = bank->base; 132 u32 l = BIT(offset); 133 134 if (enable) { 135 reg += bank->regs->set_dataout; 136 bank->context.dataout |= l; 137 } else { 138 reg += bank->regs->clr_dataout; 139 bank->context.dataout &= ~l; 140 } 141 142 writel_relaxed(l, reg); 143 } 144 145 /* set data out value using mask register */ 146 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, 147 int enable) 148 { 149 void __iomem *reg = bank->base + bank->regs->dataout; 150 u32 gpio_bit = BIT(offset); 151 u32 l; 152 153 l = readl_relaxed(reg); 154 if (enable) 155 l |= gpio_bit; 156 else 157 l &= ~gpio_bit; 158 writel_relaxed(l, reg); 159 bank->context.dataout = l; 160 } 161 162 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset) 163 { 164 void __iomem *reg = bank->base + bank->regs->datain; 165 166 return (readl_relaxed(reg) & (BIT(offset))) != 0; 167 } 168 169 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset) 170 { 171 void __iomem *reg = bank->base + bank->regs->dataout; 172 173 return (readl_relaxed(reg) & (BIT(offset))) != 0; 174 } 175 176 /* set multiple data out values using dedicate set/clear register */ 177 static void omap_set_gpio_dataout_reg_multiple(struct gpio_bank *bank, 178 unsigned long *mask, 179 unsigned long *bits) 180 { 181 void __iomem *reg = bank->base; 182 u32 l; 183 184 l = *bits & *mask; 185 writel_relaxed(l, reg + bank->regs->set_dataout); 186 bank->context.dataout |= l; 187 188 l = ~*bits & *mask; 189 writel_relaxed(l, reg + bank->regs->clr_dataout); 190 bank->context.dataout &= ~l; 191 } 192 193 /* set multiple data out values using mask register */ 194 static void omap_set_gpio_dataout_mask_multiple(struct gpio_bank *bank, 195 unsigned long *mask, 196 unsigned long *bits) 197 { 198 void __iomem *reg = bank->base + bank->regs->dataout; 199 u32 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask); 200 201 writel_relaxed(l, reg); 202 bank->context.dataout = l; 203 } 204 205 static unsigned long omap_get_gpio_datain_multiple(struct gpio_bank *bank, 206 unsigned long *mask) 207 { 208 void __iomem *reg = bank->base + bank->regs->datain; 209 210 return readl_relaxed(reg) & *mask; 211 } 212 213 static unsigned long omap_get_gpio_dataout_multiple(struct gpio_bank *bank, 214 unsigned long *mask) 215 { 216 void __iomem *reg = bank->base + bank->regs->dataout; 217 218 return readl_relaxed(reg) & *mask; 219 } 220 221 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) 222 { 223 int l = readl_relaxed(base + reg); 224 225 if (set) 226 l |= mask; 227 else 228 l &= ~mask; 229 230 writel_relaxed(l, base + reg); 231 } 232 233 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) 234 { 235 if (bank->dbck_enable_mask && !bank->dbck_enabled) { 236 clk_enable(bank->dbck); 237 bank->dbck_enabled = true; 238 239 writel_relaxed(bank->dbck_enable_mask, 240 bank->base + bank->regs->debounce_en); 241 } 242 } 243 244 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) 245 { 246 if (bank->dbck_enable_mask && bank->dbck_enabled) { 247 /* 248 * Disable debounce before cutting it's clock. If debounce is 249 * enabled but the clock is not, GPIO module seems to be unable 250 * to detect events and generate interrupts at least on OMAP3. 251 */ 252 writel_relaxed(0, bank->base + bank->regs->debounce_en); 253 254 clk_disable(bank->dbck); 255 bank->dbck_enabled = false; 256 } 257 } 258 259 /** 260 * omap2_set_gpio_debounce - low level gpio debounce time 261 * @bank: the gpio bank we're acting upon 262 * @offset: the gpio number on this @bank 263 * @debounce: debounce time to use 264 * 265 * OMAP's debounce time is in 31us steps 266 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31 267 * so we need to convert and round up to the closest unit. 268 * 269 * Return: 0 on success, negative error otherwise. 270 */ 271 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, 272 unsigned debounce) 273 { 274 void __iomem *reg; 275 u32 val; 276 u32 l; 277 bool enable = !!debounce; 278 279 if (!bank->dbck_flag) 280 return -ENOTSUPP; 281 282 if (enable) { 283 debounce = DIV_ROUND_UP(debounce, 31) - 1; 284 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce) 285 return -EINVAL; 286 } 287 288 l = BIT(offset); 289 290 clk_enable(bank->dbck); 291 reg = bank->base + bank->regs->debounce; 292 writel_relaxed(debounce, reg); 293 294 reg = bank->base + bank->regs->debounce_en; 295 val = readl_relaxed(reg); 296 297 if (enable) 298 val |= l; 299 else 300 val &= ~l; 301 bank->dbck_enable_mask = val; 302 303 writel_relaxed(val, reg); 304 clk_disable(bank->dbck); 305 /* 306 * Enable debounce clock per module. 307 * This call is mandatory because in omap_gpio_request() when 308 * *_runtime_get_sync() is called, _gpio_dbck_enable() within 309 * runtime callbck fails to turn on dbck because dbck_enable_mask 310 * used within _gpio_dbck_enable() is still not initialized at 311 * that point. Therefore we have to enable dbck here. 312 */ 313 omap_gpio_dbck_enable(bank); 314 if (bank->dbck_enable_mask) { 315 bank->context.debounce = debounce; 316 bank->context.debounce_en = val; 317 } 318 319 return 0; 320 } 321 322 /** 323 * omap_clear_gpio_debounce - clear debounce settings for a gpio 324 * @bank: the gpio bank we're acting upon 325 * @offset: the gpio number on this @bank 326 * 327 * If a gpio is using debounce, then clear the debounce enable bit and if 328 * this is the only gpio in this bank using debounce, then clear the debounce 329 * time too. The debounce clock will also be disabled when calling this function 330 * if this is the only gpio in the bank using debounce. 331 */ 332 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) 333 { 334 u32 gpio_bit = BIT(offset); 335 336 if (!bank->dbck_flag) 337 return; 338 339 if (!(bank->dbck_enable_mask & gpio_bit)) 340 return; 341 342 bank->dbck_enable_mask &= ~gpio_bit; 343 bank->context.debounce_en &= ~gpio_bit; 344 writel_relaxed(bank->context.debounce_en, 345 bank->base + bank->regs->debounce_en); 346 347 if (!bank->dbck_enable_mask) { 348 bank->context.debounce = 0; 349 writel_relaxed(bank->context.debounce, bank->base + 350 bank->regs->debounce); 351 clk_disable(bank->dbck); 352 bank->dbck_enabled = false; 353 } 354 } 355 356 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, 357 unsigned trigger) 358 { 359 void __iomem *base = bank->base; 360 u32 gpio_bit = BIT(gpio); 361 362 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, 363 trigger & IRQ_TYPE_LEVEL_LOW); 364 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, 365 trigger & IRQ_TYPE_LEVEL_HIGH); 366 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, 367 trigger & IRQ_TYPE_EDGE_RISING); 368 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, 369 trigger & IRQ_TYPE_EDGE_FALLING); 370 371 bank->context.leveldetect0 = 372 readl_relaxed(bank->base + bank->regs->leveldetect0); 373 bank->context.leveldetect1 = 374 readl_relaxed(bank->base + bank->regs->leveldetect1); 375 bank->context.risingdetect = 376 readl_relaxed(bank->base + bank->regs->risingdetect); 377 bank->context.fallingdetect = 378 readl_relaxed(bank->base + bank->regs->fallingdetect); 379 380 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { 381 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); 382 bank->context.wake_en = 383 readl_relaxed(bank->base + bank->regs->wkup_en); 384 } 385 386 /* This part needs to be executed always for OMAP{34xx, 44xx} */ 387 if (!bank->regs->irqctrl) { 388 /* On omap24xx proceed only when valid GPIO bit is set */ 389 if (bank->non_wakeup_gpios) { 390 if (!(bank->non_wakeup_gpios & gpio_bit)) 391 goto exit; 392 } 393 394 /* 395 * Log the edge gpio and manually trigger the IRQ 396 * after resume if the input level changes 397 * to avoid irq lost during PER RET/OFF mode 398 * Applies for omap2 non-wakeup gpio and all omap3 gpios 399 */ 400 if (trigger & IRQ_TYPE_EDGE_BOTH) 401 bank->enabled_non_wakeup_gpios |= gpio_bit; 402 else 403 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 404 } 405 406 exit: 407 bank->level_mask = 408 readl_relaxed(bank->base + bank->regs->leveldetect0) | 409 readl_relaxed(bank->base + bank->regs->leveldetect1); 410 } 411 412 #ifdef CONFIG_ARCH_OMAP1 413 /* 414 * This only applies to chips that can't do both rising and falling edge 415 * detection at once. For all other chips, this function is a noop. 416 */ 417 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) 418 { 419 void __iomem *reg = bank->base; 420 u32 l = 0; 421 422 if (!bank->regs->irqctrl) 423 return; 424 425 reg += bank->regs->irqctrl; 426 427 l = readl_relaxed(reg); 428 if ((l >> gpio) & 1) 429 l &= ~(BIT(gpio)); 430 else 431 l |= BIT(gpio); 432 433 writel_relaxed(l, reg); 434 } 435 #else 436 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} 437 #endif 438 439 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, 440 unsigned trigger) 441 { 442 void __iomem *reg = bank->base; 443 void __iomem *base = bank->base; 444 u32 l = 0; 445 446 if (bank->regs->leveldetect0 && bank->regs->wkup_en) { 447 omap_set_gpio_trigger(bank, gpio, trigger); 448 } else if (bank->regs->irqctrl) { 449 reg += bank->regs->irqctrl; 450 451 l = readl_relaxed(reg); 452 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 453 bank->toggle_mask |= BIT(gpio); 454 if (trigger & IRQ_TYPE_EDGE_RISING) 455 l |= BIT(gpio); 456 else if (trigger & IRQ_TYPE_EDGE_FALLING) 457 l &= ~(BIT(gpio)); 458 else 459 return -EINVAL; 460 461 writel_relaxed(l, reg); 462 } else if (bank->regs->edgectrl1) { 463 if (gpio & 0x08) 464 reg += bank->regs->edgectrl2; 465 else 466 reg += bank->regs->edgectrl1; 467 468 gpio &= 0x07; 469 l = readl_relaxed(reg); 470 l &= ~(3 << (gpio << 1)); 471 if (trigger & IRQ_TYPE_EDGE_RISING) 472 l |= 2 << (gpio << 1); 473 if (trigger & IRQ_TYPE_EDGE_FALLING) 474 l |= BIT(gpio << 1); 475 476 /* Enable wake-up during idle for dynamic tick */ 477 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); 478 bank->context.wake_en = 479 readl_relaxed(bank->base + bank->regs->wkup_en); 480 writel_relaxed(l, reg); 481 } 482 return 0; 483 } 484 485 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) 486 { 487 if (bank->regs->pinctrl) { 488 void __iomem *reg = bank->base + bank->regs->pinctrl; 489 490 /* Claim the pin for MPU */ 491 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); 492 } 493 494 if (bank->regs->ctrl && !BANK_USED(bank)) { 495 void __iomem *reg = bank->base + bank->regs->ctrl; 496 u32 ctrl; 497 498 ctrl = readl_relaxed(reg); 499 /* Module is enabled, clocks are not gated */ 500 ctrl &= ~GPIO_MOD_CTRL_BIT; 501 writel_relaxed(ctrl, reg); 502 bank->context.ctrl = ctrl; 503 } 504 } 505 506 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) 507 { 508 void __iomem *base = bank->base; 509 510 if (bank->regs->wkup_en && 511 !LINE_USED(bank->mod_usage, offset) && 512 !LINE_USED(bank->irq_usage, offset)) { 513 /* Disable wake-up during idle for dynamic tick */ 514 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); 515 bank->context.wake_en = 516 readl_relaxed(bank->base + bank->regs->wkup_en); 517 } 518 519 if (bank->regs->ctrl && !BANK_USED(bank)) { 520 void __iomem *reg = bank->base + bank->regs->ctrl; 521 u32 ctrl; 522 523 ctrl = readl_relaxed(reg); 524 /* Module is disabled, clocks are gated */ 525 ctrl |= GPIO_MOD_CTRL_BIT; 526 writel_relaxed(ctrl, reg); 527 bank->context.ctrl = ctrl; 528 } 529 } 530 531 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) 532 { 533 void __iomem *reg = bank->base + bank->regs->direction; 534 535 return readl_relaxed(reg) & BIT(offset); 536 } 537 538 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) 539 { 540 if (!LINE_USED(bank->mod_usage, offset)) { 541 omap_enable_gpio_module(bank, offset); 542 omap_set_gpio_direction(bank, offset, 1); 543 } 544 bank->irq_usage |= BIT(offset); 545 } 546 547 static int omap_gpio_irq_type(struct irq_data *d, unsigned type) 548 { 549 struct gpio_bank *bank = omap_irq_data_get_bank(d); 550 int retval; 551 unsigned long flags; 552 unsigned offset = d->hwirq; 553 554 if (type & ~IRQ_TYPE_SENSE_MASK) 555 return -EINVAL; 556 557 if (!bank->regs->leveldetect0 && 558 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) 559 return -EINVAL; 560 561 raw_spin_lock_irqsave(&bank->lock, flags); 562 retval = omap_set_gpio_triggering(bank, offset, type); 563 if (retval) { 564 raw_spin_unlock_irqrestore(&bank->lock, flags); 565 goto error; 566 } 567 omap_gpio_init_irq(bank, offset); 568 if (!omap_gpio_is_input(bank, offset)) { 569 raw_spin_unlock_irqrestore(&bank->lock, flags); 570 retval = -EINVAL; 571 goto error; 572 } 573 raw_spin_unlock_irqrestore(&bank->lock, flags); 574 575 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 576 irq_set_handler_locked(d, handle_level_irq); 577 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 578 /* 579 * Edge IRQs are already cleared/acked in irq_handler and 580 * not need to be masked, as result handle_edge_irq() 581 * logic is excessed here and may cause lose of interrupts. 582 * So just use handle_simple_irq. 583 */ 584 irq_set_handler_locked(d, handle_simple_irq); 585 586 return 0; 587 588 error: 589 return retval; 590 } 591 592 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 593 { 594 void __iomem *reg = bank->base; 595 596 reg += bank->regs->irqstatus; 597 writel_relaxed(gpio_mask, reg); 598 599 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 600 if (bank->regs->irqstatus2) { 601 reg = bank->base + bank->regs->irqstatus2; 602 writel_relaxed(gpio_mask, reg); 603 } 604 605 /* Flush posted write for the irq status to avoid spurious interrupts */ 606 readl_relaxed(reg); 607 } 608 609 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, 610 unsigned offset) 611 { 612 omap_clear_gpio_irqbank(bank, BIT(offset)); 613 } 614 615 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) 616 { 617 void __iomem *reg = bank->base; 618 u32 l; 619 u32 mask = (BIT(bank->width)) - 1; 620 621 reg += bank->regs->irqenable; 622 l = readl_relaxed(reg); 623 if (bank->regs->irqenable_inv) 624 l = ~l; 625 l &= mask; 626 return l; 627 } 628 629 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 630 { 631 void __iomem *reg = bank->base; 632 u32 l; 633 634 if (bank->regs->set_irqenable) { 635 reg += bank->regs->set_irqenable; 636 l = gpio_mask; 637 bank->context.irqenable1 |= gpio_mask; 638 } else { 639 reg += bank->regs->irqenable; 640 l = readl_relaxed(reg); 641 if (bank->regs->irqenable_inv) 642 l &= ~gpio_mask; 643 else 644 l |= gpio_mask; 645 bank->context.irqenable1 = l; 646 } 647 648 writel_relaxed(l, reg); 649 } 650 651 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 652 { 653 void __iomem *reg = bank->base; 654 u32 l; 655 656 if (bank->regs->clr_irqenable) { 657 reg += bank->regs->clr_irqenable; 658 l = gpio_mask; 659 bank->context.irqenable1 &= ~gpio_mask; 660 } else { 661 reg += bank->regs->irqenable; 662 l = readl_relaxed(reg); 663 if (bank->regs->irqenable_inv) 664 l |= gpio_mask; 665 else 666 l &= ~gpio_mask; 667 bank->context.irqenable1 = l; 668 } 669 670 writel_relaxed(l, reg); 671 } 672 673 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, 674 unsigned offset, int enable) 675 { 676 if (enable) 677 omap_enable_gpio_irqbank(bank, BIT(offset)); 678 else 679 omap_disable_gpio_irqbank(bank, BIT(offset)); 680 } 681 682 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ 683 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) 684 { 685 struct gpio_bank *bank = omap_irq_data_get_bank(d); 686 687 return irq_set_irq_wake(bank->irq, enable); 688 } 689 690 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) 691 { 692 struct gpio_bank *bank = gpiochip_get_data(chip); 693 unsigned long flags; 694 695 pm_runtime_get_sync(chip->parent); 696 697 raw_spin_lock_irqsave(&bank->lock, flags); 698 omap_enable_gpio_module(bank, offset); 699 bank->mod_usage |= BIT(offset); 700 raw_spin_unlock_irqrestore(&bank->lock, flags); 701 702 return 0; 703 } 704 705 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) 706 { 707 struct gpio_bank *bank = gpiochip_get_data(chip); 708 unsigned long flags; 709 710 raw_spin_lock_irqsave(&bank->lock, flags); 711 bank->mod_usage &= ~(BIT(offset)); 712 if (!LINE_USED(bank->irq_usage, offset)) { 713 omap_set_gpio_direction(bank, offset, 1); 714 omap_clear_gpio_debounce(bank, offset); 715 } 716 omap_disable_gpio_module(bank, offset); 717 raw_spin_unlock_irqrestore(&bank->lock, flags); 718 719 pm_runtime_put(chip->parent); 720 } 721 722 /* 723 * We need to unmask the GPIO bank interrupt as soon as possible to 724 * avoid missing GPIO interrupts for other lines in the bank. 725 * Then we need to mask-read-clear-unmask the triggered GPIO lines 726 * in the bank to avoid missing nested interrupts for a GPIO line. 727 * If we wait to unmask individual GPIO lines in the bank after the 728 * line's interrupt handler has been run, we may miss some nested 729 * interrupts. 730 */ 731 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) 732 { 733 void __iomem *isr_reg = NULL; 734 u32 enabled, isr, level_mask; 735 unsigned int bit; 736 struct gpio_bank *bank = gpiobank; 737 unsigned long wa_lock_flags; 738 unsigned long lock_flags; 739 740 isr_reg = bank->base + bank->regs->irqstatus; 741 if (WARN_ON(!isr_reg)) 742 goto exit; 743 744 if (WARN_ONCE(!pm_runtime_active(bank->chip.parent), 745 "gpio irq%i while runtime suspended?\n", irq)) 746 return IRQ_NONE; 747 748 while (1) { 749 raw_spin_lock_irqsave(&bank->lock, lock_flags); 750 751 enabled = omap_get_gpio_irqbank_mask(bank); 752 isr = readl_relaxed(isr_reg) & enabled; 753 754 if (bank->level_mask) 755 level_mask = bank->level_mask & enabled; 756 else 757 level_mask = 0; 758 759 /* clear edge sensitive interrupts before handler(s) are 760 called so that we don't miss any interrupt occurred while 761 executing them */ 762 if (isr & ~level_mask) 763 omap_clear_gpio_irqbank(bank, isr & ~level_mask); 764 765 raw_spin_unlock_irqrestore(&bank->lock, lock_flags); 766 767 if (!isr) 768 break; 769 770 while (isr) { 771 bit = __ffs(isr); 772 isr &= ~(BIT(bit)); 773 774 raw_spin_lock_irqsave(&bank->lock, lock_flags); 775 /* 776 * Some chips can't respond to both rising and falling 777 * at the same time. If this irq was requested with 778 * both flags, we need to flip the ICR data for the IRQ 779 * to respond to the IRQ for the opposite direction. 780 * This will be indicated in the bank toggle_mask. 781 */ 782 if (bank->toggle_mask & (BIT(bit))) 783 omap_toggle_gpio_edge_triggering(bank, bit); 784 785 raw_spin_unlock_irqrestore(&bank->lock, lock_flags); 786 787 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); 788 789 generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, 790 bit)); 791 792 raw_spin_unlock_irqrestore(&bank->wa_lock, 793 wa_lock_flags); 794 } 795 } 796 exit: 797 return IRQ_HANDLED; 798 } 799 800 static unsigned int omap_gpio_irq_startup(struct irq_data *d) 801 { 802 struct gpio_bank *bank = omap_irq_data_get_bank(d); 803 unsigned long flags; 804 unsigned offset = d->hwirq; 805 806 raw_spin_lock_irqsave(&bank->lock, flags); 807 808 if (!LINE_USED(bank->mod_usage, offset)) 809 omap_set_gpio_direction(bank, offset, 1); 810 else if (!omap_gpio_is_input(bank, offset)) 811 goto err; 812 omap_enable_gpio_module(bank, offset); 813 bank->irq_usage |= BIT(offset); 814 815 raw_spin_unlock_irqrestore(&bank->lock, flags); 816 omap_gpio_unmask_irq(d); 817 818 return 0; 819 err: 820 raw_spin_unlock_irqrestore(&bank->lock, flags); 821 return -EINVAL; 822 } 823 824 static void omap_gpio_irq_shutdown(struct irq_data *d) 825 { 826 struct gpio_bank *bank = omap_irq_data_get_bank(d); 827 unsigned long flags; 828 unsigned offset = d->hwirq; 829 830 raw_spin_lock_irqsave(&bank->lock, flags); 831 bank->irq_usage &= ~(BIT(offset)); 832 omap_set_gpio_irqenable(bank, offset, 0); 833 omap_clear_gpio_irqstatus(bank, offset); 834 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); 835 if (!LINE_USED(bank->mod_usage, offset)) 836 omap_clear_gpio_debounce(bank, offset); 837 omap_disable_gpio_module(bank, offset); 838 raw_spin_unlock_irqrestore(&bank->lock, flags); 839 } 840 841 static void omap_gpio_irq_bus_lock(struct irq_data *data) 842 { 843 struct gpio_bank *bank = omap_irq_data_get_bank(data); 844 845 pm_runtime_get_sync(bank->chip.parent); 846 } 847 848 static void gpio_irq_bus_sync_unlock(struct irq_data *data) 849 { 850 struct gpio_bank *bank = omap_irq_data_get_bank(data); 851 852 pm_runtime_put(bank->chip.parent); 853 } 854 855 static void omap_gpio_ack_irq(struct irq_data *d) 856 { 857 struct gpio_bank *bank = omap_irq_data_get_bank(d); 858 unsigned offset = d->hwirq; 859 860 omap_clear_gpio_irqstatus(bank, offset); 861 } 862 863 static void omap_gpio_mask_irq(struct irq_data *d) 864 { 865 struct gpio_bank *bank = omap_irq_data_get_bank(d); 866 unsigned offset = d->hwirq; 867 unsigned long flags; 868 869 raw_spin_lock_irqsave(&bank->lock, flags); 870 omap_set_gpio_irqenable(bank, offset, 0); 871 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); 872 raw_spin_unlock_irqrestore(&bank->lock, flags); 873 } 874 875 static void omap_gpio_unmask_irq(struct irq_data *d) 876 { 877 struct gpio_bank *bank = omap_irq_data_get_bank(d); 878 unsigned offset = d->hwirq; 879 u32 trigger = irqd_get_trigger_type(d); 880 unsigned long flags; 881 882 raw_spin_lock_irqsave(&bank->lock, flags); 883 if (trigger) 884 omap_set_gpio_triggering(bank, offset, trigger); 885 886 omap_set_gpio_irqenable(bank, offset, 1); 887 888 /* 889 * For level-triggered GPIOs, clearing must be done after the source 890 * is cleared, thus after the handler has run. OMAP4 needs this done 891 * after enabing the interrupt to clear the wakeup status. 892 */ 893 if (bank->level_mask & BIT(offset)) 894 omap_clear_gpio_irqstatus(bank, offset); 895 896 raw_spin_unlock_irqrestore(&bank->lock, flags); 897 } 898 899 /* 900 * Only edges can generate a wakeup event to the PRCM. 901 * 902 * Therefore, ensure any wake-up capable GPIOs have 903 * edge-detection enabled before going idle to ensure a wakeup 904 * to the PRCM is generated on a GPIO transition. (c.f. 34xx 905 * NDA TRM 25.5.3.1) 906 * 907 * The normal values will be restored upon ->runtime_resume() 908 * by writing back the values saved in bank->context. 909 */ 910 static void __maybe_unused 911 omap2_gpio_enable_level_quirk(struct gpio_bank *bank) 912 { 913 u32 wake_low, wake_hi; 914 915 /* Enable additional edge detection for level gpios for idle */ 916 wake_low = bank->context.leveldetect0 & bank->context.wake_en; 917 if (wake_low) 918 writel_relaxed(wake_low | bank->context.fallingdetect, 919 bank->base + bank->regs->fallingdetect); 920 921 wake_hi = bank->context.leveldetect1 & bank->context.wake_en; 922 if (wake_hi) 923 writel_relaxed(wake_hi | bank->context.risingdetect, 924 bank->base + bank->regs->risingdetect); 925 } 926 927 static void __maybe_unused 928 omap2_gpio_disable_level_quirk(struct gpio_bank *bank) 929 { 930 /* Disable edge detection for level gpios after idle */ 931 writel_relaxed(bank->context.fallingdetect, 932 bank->base + bank->regs->fallingdetect); 933 writel_relaxed(bank->context.risingdetect, 934 bank->base + bank->regs->risingdetect); 935 } 936 937 /*---------------------------------------------------------------------*/ 938 939 static int omap_mpuio_suspend_noirq(struct device *dev) 940 { 941 struct gpio_bank *bank = dev_get_drvdata(dev); 942 void __iomem *mask_reg = bank->base + 943 OMAP_MPUIO_GPIO_MASKIT / bank->stride; 944 unsigned long flags; 945 946 raw_spin_lock_irqsave(&bank->lock, flags); 947 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); 948 raw_spin_unlock_irqrestore(&bank->lock, flags); 949 950 return 0; 951 } 952 953 static int omap_mpuio_resume_noirq(struct device *dev) 954 { 955 struct gpio_bank *bank = dev_get_drvdata(dev); 956 void __iomem *mask_reg = bank->base + 957 OMAP_MPUIO_GPIO_MASKIT / bank->stride; 958 unsigned long flags; 959 960 raw_spin_lock_irqsave(&bank->lock, flags); 961 writel_relaxed(bank->context.wake_en, mask_reg); 962 raw_spin_unlock_irqrestore(&bank->lock, flags); 963 964 return 0; 965 } 966 967 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { 968 .suspend_noirq = omap_mpuio_suspend_noirq, 969 .resume_noirq = omap_mpuio_resume_noirq, 970 }; 971 972 /* use platform_driver for this. */ 973 static struct platform_driver omap_mpuio_driver = { 974 .driver = { 975 .name = "mpuio", 976 .pm = &omap_mpuio_dev_pm_ops, 977 }, 978 }; 979 980 static struct platform_device omap_mpuio_device = { 981 .name = "mpuio", 982 .id = -1, 983 .dev = { 984 .driver = &omap_mpuio_driver.driver, 985 } 986 /* could list the /proc/iomem resources */ 987 }; 988 989 static inline void omap_mpuio_init(struct gpio_bank *bank) 990 { 991 platform_set_drvdata(&omap_mpuio_device, bank); 992 993 if (platform_driver_register(&omap_mpuio_driver) == 0) 994 (void) platform_device_register(&omap_mpuio_device); 995 } 996 997 /*---------------------------------------------------------------------*/ 998 999 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 1000 { 1001 struct gpio_bank *bank; 1002 unsigned long flags; 1003 void __iomem *reg; 1004 int dir; 1005 1006 bank = gpiochip_get_data(chip); 1007 reg = bank->base + bank->regs->direction; 1008 raw_spin_lock_irqsave(&bank->lock, flags); 1009 dir = !!(readl_relaxed(reg) & BIT(offset)); 1010 raw_spin_unlock_irqrestore(&bank->lock, flags); 1011 return dir; 1012 } 1013 1014 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) 1015 { 1016 struct gpio_bank *bank; 1017 unsigned long flags; 1018 1019 bank = gpiochip_get_data(chip); 1020 raw_spin_lock_irqsave(&bank->lock, flags); 1021 omap_set_gpio_direction(bank, offset, 1); 1022 raw_spin_unlock_irqrestore(&bank->lock, flags); 1023 return 0; 1024 } 1025 1026 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) 1027 { 1028 struct gpio_bank *bank; 1029 1030 bank = gpiochip_get_data(chip); 1031 1032 if (omap_gpio_is_input(bank, offset)) 1033 return omap_get_gpio_datain(bank, offset); 1034 else 1035 return omap_get_gpio_dataout(bank, offset); 1036 } 1037 1038 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) 1039 { 1040 struct gpio_bank *bank; 1041 unsigned long flags; 1042 1043 bank = gpiochip_get_data(chip); 1044 raw_spin_lock_irqsave(&bank->lock, flags); 1045 bank->set_dataout(bank, offset, value); 1046 omap_set_gpio_direction(bank, offset, 0); 1047 raw_spin_unlock_irqrestore(&bank->lock, flags); 1048 return 0; 1049 } 1050 1051 static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, 1052 unsigned long *bits) 1053 { 1054 struct gpio_bank *bank = gpiochip_get_data(chip); 1055 void __iomem *reg = bank->base + bank->regs->direction; 1056 unsigned long in = readl_relaxed(reg), l; 1057 1058 *bits = 0; 1059 1060 l = in & *mask; 1061 if (l) 1062 *bits |= omap_get_gpio_datain_multiple(bank, &l); 1063 1064 l = ~in & *mask; 1065 if (l) 1066 *bits |= omap_get_gpio_dataout_multiple(bank, &l); 1067 1068 return 0; 1069 } 1070 1071 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, 1072 unsigned debounce) 1073 { 1074 struct gpio_bank *bank; 1075 unsigned long flags; 1076 int ret; 1077 1078 bank = gpiochip_get_data(chip); 1079 1080 raw_spin_lock_irqsave(&bank->lock, flags); 1081 ret = omap2_set_gpio_debounce(bank, offset, debounce); 1082 raw_spin_unlock_irqrestore(&bank->lock, flags); 1083 1084 if (ret) 1085 dev_info(chip->parent, 1086 "Could not set line %u debounce to %u microseconds (%d)", 1087 offset, debounce, ret); 1088 1089 return ret; 1090 } 1091 1092 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset, 1093 unsigned long config) 1094 { 1095 u32 debounce; 1096 1097 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 1098 return -ENOTSUPP; 1099 1100 debounce = pinconf_to_config_argument(config); 1101 return omap_gpio_debounce(chip, offset, debounce); 1102 } 1103 1104 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1105 { 1106 struct gpio_bank *bank; 1107 unsigned long flags; 1108 1109 bank = gpiochip_get_data(chip); 1110 raw_spin_lock_irqsave(&bank->lock, flags); 1111 bank->set_dataout(bank, offset, value); 1112 raw_spin_unlock_irqrestore(&bank->lock, flags); 1113 } 1114 1115 static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, 1116 unsigned long *bits) 1117 { 1118 struct gpio_bank *bank = gpiochip_get_data(chip); 1119 unsigned long flags; 1120 1121 raw_spin_lock_irqsave(&bank->lock, flags); 1122 bank->set_dataout_multiple(bank, mask, bits); 1123 raw_spin_unlock_irqrestore(&bank->lock, flags); 1124 } 1125 1126 /*---------------------------------------------------------------------*/ 1127 1128 static void omap_gpio_show_rev(struct gpio_bank *bank) 1129 { 1130 static bool called; 1131 u32 rev; 1132 1133 if (called || bank->regs->revision == USHRT_MAX) 1134 return; 1135 1136 rev = readw_relaxed(bank->base + bank->regs->revision); 1137 pr_info("OMAP GPIO hardware version %d.%d\n", 1138 (rev >> 4) & 0x0f, rev & 0x0f); 1139 1140 called = true; 1141 } 1142 1143 static void omap_gpio_mod_init(struct gpio_bank *bank) 1144 { 1145 void __iomem *base = bank->base; 1146 u32 l = 0xffffffff; 1147 1148 if (bank->width == 16) 1149 l = 0xffff; 1150 1151 if (bank->is_mpuio) { 1152 writel_relaxed(l, bank->base + bank->regs->irqenable); 1153 return; 1154 } 1155 1156 omap_gpio_rmw(base, bank->regs->irqenable, l, 1157 bank->regs->irqenable_inv); 1158 omap_gpio_rmw(base, bank->regs->irqstatus, l, 1159 !bank->regs->irqenable_inv); 1160 if (bank->regs->debounce_en) 1161 writel_relaxed(0, base + bank->regs->debounce_en); 1162 1163 /* Save OE default value (0xffffffff) in the context */ 1164 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); 1165 /* Initialize interface clk ungated, module enabled */ 1166 if (bank->regs->ctrl) 1167 writel_relaxed(0, base + bank->regs->ctrl); 1168 } 1169 1170 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) 1171 { 1172 struct gpio_irq_chip *irq; 1173 static int gpio; 1174 const char *label; 1175 int irq_base = 0; 1176 int ret; 1177 1178 /* 1179 * REVISIT eventually switch from OMAP-specific gpio structs 1180 * over to the generic ones 1181 */ 1182 bank->chip.request = omap_gpio_request; 1183 bank->chip.free = omap_gpio_free; 1184 bank->chip.get_direction = omap_gpio_get_direction; 1185 bank->chip.direction_input = omap_gpio_input; 1186 bank->chip.get = omap_gpio_get; 1187 bank->chip.get_multiple = omap_gpio_get_multiple; 1188 bank->chip.direction_output = omap_gpio_output; 1189 bank->chip.set_config = omap_gpio_set_config; 1190 bank->chip.set = omap_gpio_set; 1191 bank->chip.set_multiple = omap_gpio_set_multiple; 1192 if (bank->is_mpuio) { 1193 bank->chip.label = "mpuio"; 1194 if (bank->regs->wkup_en) 1195 bank->chip.parent = &omap_mpuio_device.dev; 1196 bank->chip.base = OMAP_MPUIO(0); 1197 } else { 1198 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", 1199 gpio, gpio + bank->width - 1); 1200 if (!label) 1201 return -ENOMEM; 1202 bank->chip.label = label; 1203 bank->chip.base = gpio; 1204 } 1205 bank->chip.ngpio = bank->width; 1206 1207 #ifdef CONFIG_ARCH_OMAP1 1208 /* 1209 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop 1210 * irq_alloc_descs() since a base IRQ offset will no longer be needed. 1211 */ 1212 irq_base = devm_irq_alloc_descs(bank->chip.parent, 1213 -1, 0, bank->width, 0); 1214 if (irq_base < 0) { 1215 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n"); 1216 return -ENODEV; 1217 } 1218 #endif 1219 1220 /* MPUIO is a bit different, reading IRQ status clears it */ 1221 if (bank->is_mpuio) { 1222 irqc->irq_ack = dummy_irq_chip.irq_ack; 1223 if (!bank->regs->wkup_en) 1224 irqc->irq_set_wake = NULL; 1225 } 1226 1227 irq = &bank->chip.irq; 1228 irq->chip = irqc; 1229 irq->handler = handle_bad_irq; 1230 irq->default_type = IRQ_TYPE_NONE; 1231 irq->num_parents = 1; 1232 irq->parents = &bank->irq; 1233 irq->first = irq_base; 1234 1235 ret = gpiochip_add_data(&bank->chip, bank); 1236 if (ret) { 1237 dev_err(bank->chip.parent, 1238 "Could not register gpio chip %d\n", ret); 1239 return ret; 1240 } 1241 1242 ret = devm_request_irq(bank->chip.parent, bank->irq, 1243 omap_gpio_irq_handler, 1244 0, dev_name(bank->chip.parent), bank); 1245 if (ret) 1246 gpiochip_remove(&bank->chip); 1247 1248 if (!bank->is_mpuio) 1249 gpio += bank->width; 1250 1251 return ret; 1252 } 1253 1254 static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context); 1255 static void omap_gpio_unidle(struct gpio_bank *bank); 1256 1257 static int gpio_omap_cpu_notifier(struct notifier_block *nb, 1258 unsigned long cmd, void *v) 1259 { 1260 struct gpio_bank *bank; 1261 unsigned long flags; 1262 1263 bank = container_of(nb, struct gpio_bank, nb); 1264 1265 raw_spin_lock_irqsave(&bank->lock, flags); 1266 switch (cmd) { 1267 case CPU_CLUSTER_PM_ENTER: 1268 if (bank->is_suspended) 1269 break; 1270 omap_gpio_idle(bank, true); 1271 break; 1272 case CPU_CLUSTER_PM_ENTER_FAILED: 1273 case CPU_CLUSTER_PM_EXIT: 1274 if (bank->is_suspended) 1275 break; 1276 omap_gpio_unidle(bank); 1277 break; 1278 } 1279 raw_spin_unlock_irqrestore(&bank->lock, flags); 1280 1281 return NOTIFY_OK; 1282 } 1283 1284 static const struct of_device_id omap_gpio_match[]; 1285 1286 static int omap_gpio_probe(struct platform_device *pdev) 1287 { 1288 struct device *dev = &pdev->dev; 1289 struct device_node *node = dev->of_node; 1290 const struct of_device_id *match; 1291 const struct omap_gpio_platform_data *pdata; 1292 struct resource *res; 1293 struct gpio_bank *bank; 1294 struct irq_chip *irqc; 1295 int ret; 1296 1297 match = of_match_device(of_match_ptr(omap_gpio_match), dev); 1298 1299 pdata = match ? match->data : dev_get_platdata(dev); 1300 if (!pdata) 1301 return -EINVAL; 1302 1303 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); 1304 if (!bank) 1305 return -ENOMEM; 1306 1307 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); 1308 if (!irqc) 1309 return -ENOMEM; 1310 1311 irqc->irq_startup = omap_gpio_irq_startup, 1312 irqc->irq_shutdown = omap_gpio_irq_shutdown, 1313 irqc->irq_ack = omap_gpio_ack_irq, 1314 irqc->irq_mask = omap_gpio_mask_irq, 1315 irqc->irq_unmask = omap_gpio_unmask_irq, 1316 irqc->irq_set_type = omap_gpio_irq_type, 1317 irqc->irq_set_wake = omap_gpio_wake_enable, 1318 irqc->irq_bus_lock = omap_gpio_irq_bus_lock, 1319 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, 1320 irqc->name = dev_name(&pdev->dev); 1321 irqc->flags = IRQCHIP_MASK_ON_SUSPEND; 1322 irqc->parent_device = dev; 1323 1324 bank->irq = platform_get_irq(pdev, 0); 1325 if (bank->irq <= 0) { 1326 if (!bank->irq) 1327 bank->irq = -ENXIO; 1328 if (bank->irq != -EPROBE_DEFER) 1329 dev_err(dev, 1330 "can't get irq resource ret=%d\n", bank->irq); 1331 return bank->irq; 1332 } 1333 1334 bank->chip.parent = dev; 1335 bank->chip.owner = THIS_MODULE; 1336 bank->dbck_flag = pdata->dbck_flag; 1337 bank->quirks = pdata->quirks; 1338 bank->stride = pdata->bank_stride; 1339 bank->width = pdata->bank_width; 1340 bank->is_mpuio = pdata->is_mpuio; 1341 bank->non_wakeup_gpios = pdata->non_wakeup_gpios; 1342 bank->regs = pdata->regs; 1343 #ifdef CONFIG_OF_GPIO 1344 bank->chip.of_node = of_node_get(node); 1345 #endif 1346 1347 if (node) { 1348 if (!of_property_read_bool(node, "ti,gpio-always-on")) 1349 bank->loses_context = true; 1350 } else { 1351 bank->loses_context = pdata->loses_context; 1352 1353 if (bank->loses_context) 1354 bank->get_context_loss_count = 1355 pdata->get_context_loss_count; 1356 } 1357 1358 if (bank->regs->set_dataout && bank->regs->clr_dataout) { 1359 bank->set_dataout = omap_set_gpio_dataout_reg; 1360 bank->set_dataout_multiple = omap_set_gpio_dataout_reg_multiple; 1361 } else { 1362 bank->set_dataout = omap_set_gpio_dataout_mask; 1363 bank->set_dataout_multiple = 1364 omap_set_gpio_dataout_mask_multiple; 1365 } 1366 1367 if (bank->quirks & OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER) { 1368 bank->funcs.idle_enable_level_quirk = 1369 omap2_gpio_enable_level_quirk; 1370 bank->funcs.idle_disable_level_quirk = 1371 omap2_gpio_disable_level_quirk; 1372 } 1373 1374 raw_spin_lock_init(&bank->lock); 1375 raw_spin_lock_init(&bank->wa_lock); 1376 1377 /* Static mapping, never released */ 1378 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1379 bank->base = devm_ioremap_resource(dev, res); 1380 if (IS_ERR(bank->base)) { 1381 return PTR_ERR(bank->base); 1382 } 1383 1384 if (bank->dbck_flag) { 1385 bank->dbck = devm_clk_get(dev, "dbclk"); 1386 if (IS_ERR(bank->dbck)) { 1387 dev_err(dev, 1388 "Could not get gpio dbck. Disable debounce\n"); 1389 bank->dbck_flag = false; 1390 } else { 1391 clk_prepare(bank->dbck); 1392 } 1393 } 1394 1395 platform_set_drvdata(pdev, bank); 1396 1397 pm_runtime_enable(dev); 1398 pm_runtime_get_sync(dev); 1399 1400 if (bank->is_mpuio) 1401 omap_mpuio_init(bank); 1402 1403 omap_gpio_mod_init(bank); 1404 1405 ret = omap_gpio_chip_init(bank, irqc); 1406 if (ret) { 1407 pm_runtime_put_sync(dev); 1408 pm_runtime_disable(dev); 1409 if (bank->dbck_flag) 1410 clk_unprepare(bank->dbck); 1411 return ret; 1412 } 1413 1414 omap_gpio_show_rev(bank); 1415 1416 if (bank->funcs.idle_enable_level_quirk && 1417 bank->funcs.idle_disable_level_quirk) { 1418 bank->nb.notifier_call = gpio_omap_cpu_notifier; 1419 cpu_pm_register_notifier(&bank->nb); 1420 } 1421 1422 pm_runtime_put(dev); 1423 1424 return 0; 1425 } 1426 1427 static int omap_gpio_remove(struct platform_device *pdev) 1428 { 1429 struct gpio_bank *bank = platform_get_drvdata(pdev); 1430 1431 if (bank->nb.notifier_call) 1432 cpu_pm_unregister_notifier(&bank->nb); 1433 list_del(&bank->node); 1434 gpiochip_remove(&bank->chip); 1435 pm_runtime_disable(&pdev->dev); 1436 if (bank->dbck_flag) 1437 clk_unprepare(bank->dbck); 1438 1439 return 0; 1440 } 1441 1442 static void omap_gpio_restore_context(struct gpio_bank *bank); 1443 1444 static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context) 1445 { 1446 struct device *dev = bank->chip.parent; 1447 u32 l1 = 0, l2 = 0; 1448 1449 if (bank->funcs.idle_enable_level_quirk) 1450 bank->funcs.idle_enable_level_quirk(bank); 1451 1452 if (!bank->enabled_non_wakeup_gpios) 1453 goto update_gpio_context_count; 1454 1455 if (!may_lose_context) 1456 goto update_gpio_context_count; 1457 1458 /* 1459 * If going to OFF, remove triggering for all 1460 * non-wakeup GPIOs. Otherwise spurious IRQs will be 1461 * generated. See OMAP2420 Errata item 1.101. 1462 */ 1463 bank->saved_datain = readl_relaxed(bank->base + 1464 bank->regs->datain); 1465 l1 = bank->context.fallingdetect; 1466 l2 = bank->context.risingdetect; 1467 1468 l1 &= ~bank->enabled_non_wakeup_gpios; 1469 l2 &= ~bank->enabled_non_wakeup_gpios; 1470 1471 writel_relaxed(l1, bank->base + bank->regs->fallingdetect); 1472 writel_relaxed(l2, bank->base + bank->regs->risingdetect); 1473 1474 bank->workaround_enabled = true; 1475 1476 update_gpio_context_count: 1477 if (bank->get_context_loss_count) 1478 bank->context_loss_count = 1479 bank->get_context_loss_count(dev); 1480 1481 omap_gpio_dbck_disable(bank); 1482 } 1483 1484 static void omap_gpio_init_context(struct gpio_bank *p); 1485 1486 static void omap_gpio_unidle(struct gpio_bank *bank) 1487 { 1488 struct device *dev = bank->chip.parent; 1489 u32 l = 0, gen, gen0, gen1; 1490 int c; 1491 1492 /* 1493 * On the first resume during the probe, the context has not 1494 * been initialised and so initialise it now. Also initialise 1495 * the context loss count. 1496 */ 1497 if (bank->loses_context && !bank->context_valid) { 1498 omap_gpio_init_context(bank); 1499 1500 if (bank->get_context_loss_count) 1501 bank->context_loss_count = 1502 bank->get_context_loss_count(dev); 1503 } 1504 1505 omap_gpio_dbck_enable(bank); 1506 1507 if (bank->funcs.idle_disable_level_quirk) 1508 bank->funcs.idle_disable_level_quirk(bank); 1509 1510 if (bank->loses_context) { 1511 if (!bank->get_context_loss_count) { 1512 omap_gpio_restore_context(bank); 1513 } else { 1514 c = bank->get_context_loss_count(dev); 1515 if (c != bank->context_loss_count) { 1516 omap_gpio_restore_context(bank); 1517 } else { 1518 return; 1519 } 1520 } 1521 } 1522 1523 if (!bank->workaround_enabled) 1524 return; 1525 1526 l = readl_relaxed(bank->base + bank->regs->datain); 1527 1528 /* 1529 * Check if any of the non-wakeup interrupt GPIOs have changed 1530 * state. If so, generate an IRQ by software. This is 1531 * horribly racy, but it's the best we can do to work around 1532 * this silicon bug. 1533 */ 1534 l ^= bank->saved_datain; 1535 l &= bank->enabled_non_wakeup_gpios; 1536 1537 /* 1538 * No need to generate IRQs for the rising edge for gpio IRQs 1539 * configured with falling edge only; and vice versa. 1540 */ 1541 gen0 = l & bank->context.fallingdetect; 1542 gen0 &= bank->saved_datain; 1543 1544 gen1 = l & bank->context.risingdetect; 1545 gen1 &= ~(bank->saved_datain); 1546 1547 /* FIXME: Consider GPIO IRQs with level detections properly! */ 1548 gen = l & (~(bank->context.fallingdetect) & 1549 ~(bank->context.risingdetect)); 1550 /* Consider all GPIO IRQs needed to be updated */ 1551 gen |= gen0 | gen1; 1552 1553 if (gen) { 1554 u32 old0, old1; 1555 1556 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); 1557 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); 1558 1559 if (!bank->regs->irqstatus_raw0) { 1560 writel_relaxed(old0 | gen, bank->base + 1561 bank->regs->leveldetect0); 1562 writel_relaxed(old1 | gen, bank->base + 1563 bank->regs->leveldetect1); 1564 } 1565 1566 if (bank->regs->irqstatus_raw0) { 1567 writel_relaxed(old0 | l, bank->base + 1568 bank->regs->leveldetect0); 1569 writel_relaxed(old1 | l, bank->base + 1570 bank->regs->leveldetect1); 1571 } 1572 writel_relaxed(old0, bank->base + bank->regs->leveldetect0); 1573 writel_relaxed(old1, bank->base + bank->regs->leveldetect1); 1574 } 1575 1576 bank->workaround_enabled = false; 1577 } 1578 1579 static void omap_gpio_init_context(struct gpio_bank *p) 1580 { 1581 struct omap_gpio_reg_offs *regs = p->regs; 1582 void __iomem *base = p->base; 1583 1584 p->context.ctrl = readl_relaxed(base + regs->ctrl); 1585 p->context.oe = readl_relaxed(base + regs->direction); 1586 p->context.wake_en = readl_relaxed(base + regs->wkup_en); 1587 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); 1588 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); 1589 p->context.risingdetect = readl_relaxed(base + regs->risingdetect); 1590 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); 1591 p->context.irqenable1 = readl_relaxed(base + regs->irqenable); 1592 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); 1593 1594 if (regs->set_dataout && p->regs->clr_dataout) 1595 p->context.dataout = readl_relaxed(base + regs->set_dataout); 1596 else 1597 p->context.dataout = readl_relaxed(base + regs->dataout); 1598 1599 p->context_valid = true; 1600 } 1601 1602 static void omap_gpio_restore_context(struct gpio_bank *bank) 1603 { 1604 writel_relaxed(bank->context.wake_en, 1605 bank->base + bank->regs->wkup_en); 1606 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); 1607 writel_relaxed(bank->context.leveldetect0, 1608 bank->base + bank->regs->leveldetect0); 1609 writel_relaxed(bank->context.leveldetect1, 1610 bank->base + bank->regs->leveldetect1); 1611 writel_relaxed(bank->context.risingdetect, 1612 bank->base + bank->regs->risingdetect); 1613 writel_relaxed(bank->context.fallingdetect, 1614 bank->base + bank->regs->fallingdetect); 1615 if (bank->regs->set_dataout && bank->regs->clr_dataout) 1616 writel_relaxed(bank->context.dataout, 1617 bank->base + bank->regs->set_dataout); 1618 else 1619 writel_relaxed(bank->context.dataout, 1620 bank->base + bank->regs->dataout); 1621 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); 1622 1623 if (bank->dbck_enable_mask) { 1624 writel_relaxed(bank->context.debounce, bank->base + 1625 bank->regs->debounce); 1626 writel_relaxed(bank->context.debounce_en, 1627 bank->base + bank->regs->debounce_en); 1628 } 1629 1630 writel_relaxed(bank->context.irqenable1, 1631 bank->base + bank->regs->irqenable); 1632 writel_relaxed(bank->context.irqenable2, 1633 bank->base + bank->regs->irqenable2); 1634 } 1635 1636 static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev) 1637 { 1638 struct gpio_bank *bank = dev_get_drvdata(dev); 1639 unsigned long flags; 1640 int error = 0; 1641 1642 raw_spin_lock_irqsave(&bank->lock, flags); 1643 /* Must be idled only by CPU_CLUSTER_PM_ENTER? */ 1644 if (bank->irq_usage) { 1645 error = -EBUSY; 1646 goto unlock; 1647 } 1648 omap_gpio_idle(bank, true); 1649 bank->is_suspended = true; 1650 unlock: 1651 raw_spin_unlock_irqrestore(&bank->lock, flags); 1652 1653 return error; 1654 } 1655 1656 static int __maybe_unused omap_gpio_runtime_resume(struct device *dev) 1657 { 1658 struct gpio_bank *bank = dev_get_drvdata(dev); 1659 unsigned long flags; 1660 int error = 0; 1661 1662 raw_spin_lock_irqsave(&bank->lock, flags); 1663 /* Must be unidled only by CPU_CLUSTER_PM_ENTER? */ 1664 if (bank->irq_usage) { 1665 error = -EBUSY; 1666 goto unlock; 1667 } 1668 omap_gpio_unidle(bank); 1669 bank->is_suspended = false; 1670 unlock: 1671 raw_spin_unlock_irqrestore(&bank->lock, flags); 1672 1673 return error; 1674 } 1675 1676 #ifdef CONFIG_ARCH_OMAP2PLUS 1677 static const struct dev_pm_ops gpio_pm_ops = { 1678 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, 1679 NULL) 1680 }; 1681 #else 1682 static const struct dev_pm_ops gpio_pm_ops; 1683 #endif /* CONFIG_ARCH_OMAP2PLUS */ 1684 1685 #if defined(CONFIG_OF) 1686 static struct omap_gpio_reg_offs omap2_gpio_regs = { 1687 .revision = OMAP24XX_GPIO_REVISION, 1688 .direction = OMAP24XX_GPIO_OE, 1689 .datain = OMAP24XX_GPIO_DATAIN, 1690 .dataout = OMAP24XX_GPIO_DATAOUT, 1691 .set_dataout = OMAP24XX_GPIO_SETDATAOUT, 1692 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, 1693 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, 1694 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, 1695 .irqenable = OMAP24XX_GPIO_IRQENABLE1, 1696 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, 1697 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, 1698 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, 1699 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, 1700 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, 1701 .ctrl = OMAP24XX_GPIO_CTRL, 1702 .wkup_en = OMAP24XX_GPIO_WAKE_EN, 1703 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, 1704 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, 1705 .risingdetect = OMAP24XX_GPIO_RISINGDETECT, 1706 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, 1707 }; 1708 1709 static struct omap_gpio_reg_offs omap4_gpio_regs = { 1710 .revision = OMAP4_GPIO_REVISION, 1711 .direction = OMAP4_GPIO_OE, 1712 .datain = OMAP4_GPIO_DATAIN, 1713 .dataout = OMAP4_GPIO_DATAOUT, 1714 .set_dataout = OMAP4_GPIO_SETDATAOUT, 1715 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, 1716 .irqstatus = OMAP4_GPIO_IRQSTATUS0, 1717 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, 1718 .irqenable = OMAP4_GPIO_IRQSTATUSSET0, 1719 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, 1720 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, 1721 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, 1722 .debounce = OMAP4_GPIO_DEBOUNCINGTIME, 1723 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, 1724 .ctrl = OMAP4_GPIO_CTRL, 1725 .wkup_en = OMAP4_GPIO_IRQWAKEN0, 1726 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, 1727 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, 1728 .risingdetect = OMAP4_GPIO_RISINGDETECT, 1729 .fallingdetect = OMAP4_GPIO_FALLINGDETECT, 1730 }; 1731 1732 /* 1733 * Note that omap2 does not currently support idle modes with context loss so 1734 * no need to add OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER quirk flag to save 1735 * and restore context. 1736 */ 1737 static const struct omap_gpio_platform_data omap2_pdata = { 1738 .regs = &omap2_gpio_regs, 1739 .bank_width = 32, 1740 .dbck_flag = false, 1741 }; 1742 1743 static const struct omap_gpio_platform_data omap3_pdata = { 1744 .regs = &omap2_gpio_regs, 1745 .bank_width = 32, 1746 .dbck_flag = true, 1747 .quirks = OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER, 1748 }; 1749 1750 static const struct omap_gpio_platform_data omap4_pdata = { 1751 .regs = &omap4_gpio_regs, 1752 .bank_width = 32, 1753 .dbck_flag = true, 1754 .quirks = OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER, 1755 }; 1756 1757 static const struct of_device_id omap_gpio_match[] = { 1758 { 1759 .compatible = "ti,omap4-gpio", 1760 .data = &omap4_pdata, 1761 }, 1762 { 1763 .compatible = "ti,omap3-gpio", 1764 .data = &omap3_pdata, 1765 }, 1766 { 1767 .compatible = "ti,omap2-gpio", 1768 .data = &omap2_pdata, 1769 }, 1770 { }, 1771 }; 1772 MODULE_DEVICE_TABLE(of, omap_gpio_match); 1773 #endif 1774 1775 static struct platform_driver omap_gpio_driver = { 1776 .probe = omap_gpio_probe, 1777 .remove = omap_gpio_remove, 1778 .driver = { 1779 .name = "omap_gpio", 1780 .pm = &gpio_pm_ops, 1781 .of_match_table = of_match_ptr(omap_gpio_match), 1782 }, 1783 }; 1784 1785 /* 1786 * gpio driver register needs to be done before 1787 * machine_init functions access gpio APIs. 1788 * Hence omap_gpio_drv_reg() is a postcore_initcall. 1789 */ 1790 static int __init omap_gpio_drv_reg(void) 1791 { 1792 return platform_driver_register(&omap_gpio_driver); 1793 } 1794 postcore_initcall(omap_gpio_drv_reg); 1795 1796 static void __exit omap_gpio_exit(void) 1797 { 1798 platform_driver_unregister(&omap_gpio_driver); 1799 } 1800 module_exit(omap_gpio_exit); 1801 1802 MODULE_DESCRIPTION("omap gpio driver"); 1803 MODULE_ALIAS("platform:gpio-omap"); 1804 MODULE_LICENSE("GPL v2"); 1805