xref: /openbmc/linux/drivers/gpio/gpio-mxs.c (revision 965f22bc) 
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
4 // Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5 //
6 // Based on code from Freescale,
7 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8 
9 #include <linux/err.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/gpio/driver.h>
21 /* FIXME: for gpio_get_value(), replace this by direct register read */
22 #include <linux/gpio.h>
23 #include <linux/module.h>
24 
25 #define MXS_SET		0x4
26 #define MXS_CLR		0x8
27 
28 #define PINCTRL_DOUT(p)		((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
29 #define PINCTRL_DIN(p)		((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
30 #define PINCTRL_DOE(p)		((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
31 #define PINCTRL_PIN2IRQ(p)	((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
32 #define PINCTRL_IRQEN(p)	((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
33 #define PINCTRL_IRQLEV(p)	((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
34 #define PINCTRL_IRQPOL(p)	((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
35 #define PINCTRL_IRQSTAT(p)	((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
36 
37 #define GPIO_INT_FALL_EDGE	0x0
38 #define GPIO_INT_LOW_LEV	0x1
39 #define GPIO_INT_RISE_EDGE	0x2
40 #define GPIO_INT_HIGH_LEV	0x3
41 #define GPIO_INT_LEV_MASK	(1 << 0)
42 #define GPIO_INT_POL_MASK	(1 << 1)
43 
44 enum mxs_gpio_id {
45 	IMX23_GPIO,
46 	IMX28_GPIO,
47 };
48 
49 struct mxs_gpio_port {
50 	void __iomem *base;
51 	int id;
52 	int irq;
53 	struct irq_domain *domain;
54 	struct gpio_chip gc;
55 	struct device *dev;
56 	enum mxs_gpio_id devid;
57 	u32 both_edges;
58 };
59 
60 static inline int is_imx23_gpio(struct mxs_gpio_port *port)
61 {
62 	return port->devid == IMX23_GPIO;
63 }
64 
65 static inline int is_imx28_gpio(struct mxs_gpio_port *port)
66 {
67 	return port->devid == IMX28_GPIO;
68 }
69 
70 /* Note: This driver assumes 32 GPIOs are handled in one register */
71 
72 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
73 {
74 	u32 val;
75 	u32 pin_mask = 1 << d->hwirq;
76 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
77 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
78 	struct mxs_gpio_port *port = gc->private;
79 	void __iomem *pin_addr;
80 	int edge;
81 
82 	if (!(ct->type & type))
83 		if (irq_setup_alt_chip(d, type))
84 			return -EINVAL;
85 
86 	port->both_edges &= ~pin_mask;
87 	switch (type) {
88 	case IRQ_TYPE_EDGE_BOTH:
89 		val = gpio_get_value(port->gc.base + d->hwirq);
90 		if (val)
91 			edge = GPIO_INT_FALL_EDGE;
92 		else
93 			edge = GPIO_INT_RISE_EDGE;
94 		port->both_edges |= pin_mask;
95 		break;
96 	case IRQ_TYPE_EDGE_RISING:
97 		edge = GPIO_INT_RISE_EDGE;
98 		break;
99 	case IRQ_TYPE_EDGE_FALLING:
100 		edge = GPIO_INT_FALL_EDGE;
101 		break;
102 	case IRQ_TYPE_LEVEL_LOW:
103 		edge = GPIO_INT_LOW_LEV;
104 		break;
105 	case IRQ_TYPE_LEVEL_HIGH:
106 		edge = GPIO_INT_HIGH_LEV;
107 		break;
108 	default:
109 		return -EINVAL;
110 	}
111 
112 	/* set level or edge */
113 	pin_addr = port->base + PINCTRL_IRQLEV(port);
114 	if (edge & GPIO_INT_LEV_MASK) {
115 		writel(pin_mask, pin_addr + MXS_SET);
116 		writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
117 	} else {
118 		writel(pin_mask, pin_addr + MXS_CLR);
119 		writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
120 	}
121 
122 	/* set polarity */
123 	pin_addr = port->base + PINCTRL_IRQPOL(port);
124 	if (edge & GPIO_INT_POL_MASK)
125 		writel(pin_mask, pin_addr + MXS_SET);
126 	else
127 		writel(pin_mask, pin_addr + MXS_CLR);
128 
129 	writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
130 
131 	return 0;
132 }
133 
134 static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
135 {
136 	u32 bit, val, edge;
137 	void __iomem *pin_addr;
138 
139 	bit = 1 << gpio;
140 
141 	pin_addr = port->base + PINCTRL_IRQPOL(port);
142 	val = readl(pin_addr);
143 	edge = val & bit;
144 
145 	if (edge)
146 		writel(bit, pin_addr + MXS_CLR);
147 	else
148 		writel(bit, pin_addr + MXS_SET);
149 }
150 
151 /* MXS has one interrupt *per* gpio port */
152 static void mxs_gpio_irq_handler(struct irq_desc *desc)
153 {
154 	u32 irq_stat;
155 	struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
156 
157 	desc->irq_data.chip->irq_ack(&desc->irq_data);
158 
159 	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
160 			readl(port->base + PINCTRL_IRQEN(port));
161 
162 	while (irq_stat != 0) {
163 		int irqoffset = fls(irq_stat) - 1;
164 		if (port->both_edges & (1 << irqoffset))
165 			mxs_flip_edge(port, irqoffset);
166 
167 		generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
168 		irq_stat &= ~(1 << irqoffset);
169 	}
170 }
171 
172 /*
173  * Set interrupt number "irq" in the GPIO as a wake-up source.
174  * While system is running, all registered GPIO interrupts need to have
175  * wake-up enabled. When system is suspended, only selected GPIO interrupts
176  * need to have wake-up enabled.
177  * @param  irq          interrupt source number
178  * @param  enable       enable as wake-up if equal to non-zero
179  * @return       This function returns 0 on success.
180  */
181 static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
182 {
183 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
184 	struct mxs_gpio_port *port = gc->private;
185 
186 	if (enable)
187 		enable_irq_wake(port->irq);
188 	else
189 		disable_irq_wake(port->irq);
190 
191 	return 0;
192 }
193 
194 static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
195 {
196 	struct irq_chip_generic *gc;
197 	struct irq_chip_type *ct;
198 	int rv;
199 
200 	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
201 					 port->base, handle_level_irq);
202 	if (!gc)
203 		return -ENOMEM;
204 
205 	gc->private = port;
206 
207 	ct = &gc->chip_types[0];
208 	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
209 	ct->chip.irq_ack = irq_gc_ack_set_bit;
210 	ct->chip.irq_mask = irq_gc_mask_disable_reg;
211 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
212 	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
213 	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
214 	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
215 	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
216 	ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
217 	ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
218 
219 	ct = &gc->chip_types[1];
220 	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
221 	ct->chip.irq_ack = irq_gc_ack_set_bit;
222 	ct->chip.irq_mask = irq_gc_mask_disable_reg;
223 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
224 	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
225 	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
226 	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
227 	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
228 	ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
229 	ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
230 	ct->handler = handle_level_irq;
231 
232 	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
233 					 IRQ_GC_INIT_NESTED_LOCK,
234 					 IRQ_NOREQUEST, 0);
235 
236 	return rv;
237 }
238 
239 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
240 {
241 	struct mxs_gpio_port *port = gpiochip_get_data(gc);
242 
243 	return irq_find_mapping(port->domain, offset);
244 }
245 
246 static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
247 {
248 	struct mxs_gpio_port *port = gpiochip_get_data(gc);
249 	u32 mask = 1 << offset;
250 	u32 dir;
251 
252 	dir = readl(port->base + PINCTRL_DOE(port));
253 	return !(dir & mask);
254 }
255 
256 static const struct platform_device_id mxs_gpio_ids[] = {
257 	{
258 		.name = "imx23-gpio",
259 		.driver_data = IMX23_GPIO,
260 	}, {
261 		.name = "imx28-gpio",
262 		.driver_data = IMX28_GPIO,
263 	}, {
264 		/* sentinel */
265 	}
266 };
267 MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
268 
269 static const struct of_device_id mxs_gpio_dt_ids[] = {
270 	{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
271 	{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
272 	{ /* sentinel */ }
273 };
274 MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
275 
276 static int mxs_gpio_probe(struct platform_device *pdev)
277 {
278 	struct device_node *np = pdev->dev.of_node;
279 	struct device_node *parent;
280 	static void __iomem *base;
281 	struct mxs_gpio_port *port;
282 	int irq_base;
283 	int err;
284 
285 	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
286 	if (!port)
287 		return -ENOMEM;
288 
289 	port->id = of_alias_get_id(np, "gpio");
290 	if (port->id < 0)
291 		return port->id;
292 	port->devid = (enum mxs_gpio_id)of_device_get_match_data(&pdev->dev);
293 	port->dev = &pdev->dev;
294 	port->irq = platform_get_irq(pdev, 0);
295 	if (port->irq < 0)
296 		return port->irq;
297 
298 	/*
299 	 * map memory region only once, as all the gpio ports
300 	 * share the same one
301 	 */
302 	if (!base) {
303 		parent = of_get_parent(np);
304 		base = of_iomap(parent, 0);
305 		of_node_put(parent);
306 		if (!base)
307 			return -EADDRNOTAVAIL;
308 	}
309 	port->base = base;
310 
311 	/* initially disable the interrupts */
312 	writel(0, port->base + PINCTRL_PIN2IRQ(port));
313 	writel(0, port->base + PINCTRL_IRQEN(port));
314 
315 	/* clear address has to be used to clear IRQSTAT bits */
316 	writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
317 
318 	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
319 	if (irq_base < 0) {
320 		err = irq_base;
321 		goto out_iounmap;
322 	}
323 
324 	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
325 					     &irq_domain_simple_ops, NULL);
326 	if (!port->domain) {
327 		err = -ENODEV;
328 		goto out_iounmap;
329 	}
330 
331 	/* gpio-mxs can be a generic irq chip */
332 	err = mxs_gpio_init_gc(port, irq_base);
333 	if (err < 0)
334 		goto out_irqdomain_remove;
335 
336 	/* setup one handler for each entry */
337 	irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
338 					 port);
339 
340 	err = bgpio_init(&port->gc, &pdev->dev, 4,
341 			 port->base + PINCTRL_DIN(port),
342 			 port->base + PINCTRL_DOUT(port) + MXS_SET,
343 			 port->base + PINCTRL_DOUT(port) + MXS_CLR,
344 			 port->base + PINCTRL_DOE(port), NULL, 0);
345 	if (err)
346 		goto out_irqdomain_remove;
347 
348 	port->gc.to_irq = mxs_gpio_to_irq;
349 	port->gc.get_direction = mxs_gpio_get_direction;
350 	port->gc.base = port->id * 32;
351 
352 	err = gpiochip_add_data(&port->gc, port);
353 	if (err)
354 		goto out_irqdomain_remove;
355 
356 	return 0;
357 
358 out_irqdomain_remove:
359 	irq_domain_remove(port->domain);
360 out_iounmap:
361 	iounmap(port->base);
362 	return err;
363 }
364 
365 static struct platform_driver mxs_gpio_driver = {
366 	.driver		= {
367 		.name	= "gpio-mxs",
368 		.of_match_table = mxs_gpio_dt_ids,
369 		.suppress_bind_attrs = true,
370 	},
371 	.probe		= mxs_gpio_probe,
372 	.id_table	= mxs_gpio_ids,
373 };
374 
375 static int __init mxs_gpio_init(void)
376 {
377 	return platform_driver_register(&mxs_gpio_driver);
378 }
379 postcore_initcall(mxs_gpio_init);
380 
381 MODULE_AUTHOR("Freescale Semiconductor, "
382 	      "Daniel Mack <danielncaiaq.de>, "
383 	      "Juergen Beisert <kernel@pengutronix.de>");
384 MODULE_DESCRIPTION("Freescale MXS GPIO");
385 MODULE_LICENSE("GPL");
386