1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 4 // Copyright 2008 Juergen Beisert, kernel@pengutronix.de 5 // 6 // Based on code from Freescale Semiconductor, 7 // Authors: Daniel Mack, Juergen Beisert. 8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9 10 #include <linux/clk.h> 11 #include <linux/err.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/syscore_ops.h> 22 #include <linux/gpio/driver.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/bug.h> 26 27 /* device type dependent stuff */ 28 struct mxc_gpio_hwdata { 29 unsigned dr_reg; 30 unsigned gdir_reg; 31 unsigned psr_reg; 32 unsigned icr1_reg; 33 unsigned icr2_reg; 34 unsigned imr_reg; 35 unsigned isr_reg; 36 int edge_sel_reg; 37 unsigned low_level; 38 unsigned high_level; 39 unsigned rise_edge; 40 unsigned fall_edge; 41 }; 42 43 struct mxc_gpio_reg_saved { 44 u32 icr1; 45 u32 icr2; 46 u32 imr; 47 u32 gdir; 48 u32 edge_sel; 49 u32 dr; 50 }; 51 52 struct mxc_gpio_port { 53 struct list_head node; 54 void __iomem *base; 55 struct clk *clk; 56 int irq; 57 int irq_high; 58 struct irq_domain *domain; 59 struct gpio_chip gc; 60 struct device *dev; 61 u32 both_edges; 62 struct mxc_gpio_reg_saved gpio_saved_reg; 63 bool power_off; 64 const struct mxc_gpio_hwdata *hwdata; 65 }; 66 67 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 68 .dr_reg = 0x1c, 69 .gdir_reg = 0x00, 70 .psr_reg = 0x24, 71 .icr1_reg = 0x28, 72 .icr2_reg = 0x2c, 73 .imr_reg = 0x30, 74 .isr_reg = 0x34, 75 .edge_sel_reg = -EINVAL, 76 .low_level = 0x03, 77 .high_level = 0x02, 78 .rise_edge = 0x00, 79 .fall_edge = 0x01, 80 }; 81 82 static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 83 .dr_reg = 0x00, 84 .gdir_reg = 0x04, 85 .psr_reg = 0x08, 86 .icr1_reg = 0x0c, 87 .icr2_reg = 0x10, 88 .imr_reg = 0x14, 89 .isr_reg = 0x18, 90 .edge_sel_reg = -EINVAL, 91 .low_level = 0x00, 92 .high_level = 0x01, 93 .rise_edge = 0x02, 94 .fall_edge = 0x03, 95 }; 96 97 static struct mxc_gpio_hwdata imx35_gpio_hwdata = { 98 .dr_reg = 0x00, 99 .gdir_reg = 0x04, 100 .psr_reg = 0x08, 101 .icr1_reg = 0x0c, 102 .icr2_reg = 0x10, 103 .imr_reg = 0x14, 104 .isr_reg = 0x18, 105 .edge_sel_reg = 0x1c, 106 .low_level = 0x00, 107 .high_level = 0x01, 108 .rise_edge = 0x02, 109 .fall_edge = 0x03, 110 }; 111 112 #define GPIO_DR (port->hwdata->dr_reg) 113 #define GPIO_GDIR (port->hwdata->gdir_reg) 114 #define GPIO_PSR (port->hwdata->psr_reg) 115 #define GPIO_ICR1 (port->hwdata->icr1_reg) 116 #define GPIO_ICR2 (port->hwdata->icr2_reg) 117 #define GPIO_IMR (port->hwdata->imr_reg) 118 #define GPIO_ISR (port->hwdata->isr_reg) 119 #define GPIO_EDGE_SEL (port->hwdata->edge_sel_reg) 120 121 #define GPIO_INT_LOW_LEV (port->hwdata->low_level) 122 #define GPIO_INT_HIGH_LEV (port->hwdata->high_level) 123 #define GPIO_INT_RISE_EDGE (port->hwdata->rise_edge) 124 #define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge) 125 #define GPIO_INT_BOTH_EDGES 0x4 126 127 static const struct of_device_id mxc_gpio_dt_ids[] = { 128 { .compatible = "fsl,imx1-gpio", .data = &imx1_imx21_gpio_hwdata }, 129 { .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata }, 130 { .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata }, 131 { .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata }, 132 { .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata }, 133 { /* sentinel */ } 134 }; 135 MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids); 136 137 /* 138 * MX2 has one interrupt *for all* gpio ports. The list is used 139 * to save the references to all ports, so that mx2_gpio_irq_handler 140 * can walk through all interrupt status registers. 141 */ 142 static LIST_HEAD(mxc_gpio_ports); 143 144 /* Note: This driver assumes 32 GPIOs are handled in one register */ 145 146 static int gpio_set_irq_type(struct irq_data *d, u32 type) 147 { 148 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 149 struct mxc_gpio_port *port = gc->private; 150 u32 bit, val; 151 u32 gpio_idx = d->hwirq; 152 int edge; 153 void __iomem *reg = port->base; 154 155 port->both_edges &= ~(1 << gpio_idx); 156 switch (type) { 157 case IRQ_TYPE_EDGE_RISING: 158 edge = GPIO_INT_RISE_EDGE; 159 break; 160 case IRQ_TYPE_EDGE_FALLING: 161 edge = GPIO_INT_FALL_EDGE; 162 break; 163 case IRQ_TYPE_EDGE_BOTH: 164 if (GPIO_EDGE_SEL >= 0) { 165 edge = GPIO_INT_BOTH_EDGES; 166 } else { 167 val = port->gc.get(&port->gc, gpio_idx); 168 if (val) { 169 edge = GPIO_INT_LOW_LEV; 170 pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx); 171 } else { 172 edge = GPIO_INT_HIGH_LEV; 173 pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx); 174 } 175 port->both_edges |= 1 << gpio_idx; 176 } 177 break; 178 case IRQ_TYPE_LEVEL_LOW: 179 edge = GPIO_INT_LOW_LEV; 180 break; 181 case IRQ_TYPE_LEVEL_HIGH: 182 edge = GPIO_INT_HIGH_LEV; 183 break; 184 default: 185 return -EINVAL; 186 } 187 188 if (GPIO_EDGE_SEL >= 0) { 189 val = readl(port->base + GPIO_EDGE_SEL); 190 if (edge == GPIO_INT_BOTH_EDGES) 191 writel(val | (1 << gpio_idx), 192 port->base + GPIO_EDGE_SEL); 193 else 194 writel(val & ~(1 << gpio_idx), 195 port->base + GPIO_EDGE_SEL); 196 } 197 198 if (edge != GPIO_INT_BOTH_EDGES) { 199 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ 200 bit = gpio_idx & 0xf; 201 val = readl(reg) & ~(0x3 << (bit << 1)); 202 writel(val | (edge << (bit << 1)), reg); 203 } 204 205 writel(1 << gpio_idx, port->base + GPIO_ISR); 206 207 return 0; 208 } 209 210 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 211 { 212 void __iomem *reg = port->base; 213 u32 bit, val; 214 int edge; 215 216 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 217 bit = gpio & 0xf; 218 val = readl(reg); 219 edge = (val >> (bit << 1)) & 3; 220 val &= ~(0x3 << (bit << 1)); 221 if (edge == GPIO_INT_HIGH_LEV) { 222 edge = GPIO_INT_LOW_LEV; 223 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 224 } else if (edge == GPIO_INT_LOW_LEV) { 225 edge = GPIO_INT_HIGH_LEV; 226 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 227 } else { 228 pr_err("mxc: invalid configuration for GPIO %d: %x\n", 229 gpio, edge); 230 return; 231 } 232 writel(val | (edge << (bit << 1)), reg); 233 } 234 235 /* handle 32 interrupts in one status register */ 236 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 237 { 238 while (irq_stat != 0) { 239 int irqoffset = fls(irq_stat) - 1; 240 241 if (port->both_edges & (1 << irqoffset)) 242 mxc_flip_edge(port, irqoffset); 243 244 generic_handle_domain_irq(port->domain, irqoffset); 245 246 irq_stat &= ~(1 << irqoffset); 247 } 248 } 249 250 /* MX1 and MX3 has one interrupt *per* gpio port */ 251 static void mx3_gpio_irq_handler(struct irq_desc *desc) 252 { 253 u32 irq_stat; 254 struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); 255 struct irq_chip *chip = irq_desc_get_chip(desc); 256 257 chained_irq_enter(chip, desc); 258 259 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 260 261 mxc_gpio_irq_handler(port, irq_stat); 262 263 chained_irq_exit(chip, desc); 264 } 265 266 /* MX2 has one interrupt *for all* gpio ports */ 267 static void mx2_gpio_irq_handler(struct irq_desc *desc) 268 { 269 u32 irq_msk, irq_stat; 270 struct mxc_gpio_port *port; 271 struct irq_chip *chip = irq_desc_get_chip(desc); 272 273 chained_irq_enter(chip, desc); 274 275 /* walk through all interrupt status registers */ 276 list_for_each_entry(port, &mxc_gpio_ports, node) { 277 irq_msk = readl(port->base + GPIO_IMR); 278 if (!irq_msk) 279 continue; 280 281 irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 282 if (irq_stat) 283 mxc_gpio_irq_handler(port, irq_stat); 284 } 285 chained_irq_exit(chip, desc); 286 } 287 288 /* 289 * Set interrupt number "irq" in the GPIO as a wake-up source. 290 * While system is running, all registered GPIO interrupts need to have 291 * wake-up enabled. When system is suspended, only selected GPIO interrupts 292 * need to have wake-up enabled. 293 * @param irq interrupt source number 294 * @param enable enable as wake-up if equal to non-zero 295 * @return This function returns 0 on success. 296 */ 297 static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 298 { 299 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 300 struct mxc_gpio_port *port = gc->private; 301 u32 gpio_idx = d->hwirq; 302 int ret; 303 304 if (enable) { 305 if (port->irq_high && (gpio_idx >= 16)) 306 ret = enable_irq_wake(port->irq_high); 307 else 308 ret = enable_irq_wake(port->irq); 309 } else { 310 if (port->irq_high && (gpio_idx >= 16)) 311 ret = disable_irq_wake(port->irq_high); 312 else 313 ret = disable_irq_wake(port->irq); 314 } 315 316 return ret; 317 } 318 319 static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) 320 { 321 struct irq_chip_generic *gc; 322 struct irq_chip_type *ct; 323 int rv; 324 325 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base, 326 port->base, handle_level_irq); 327 if (!gc) 328 return -ENOMEM; 329 gc->private = port; 330 331 ct = gc->chip_types; 332 ct->chip.irq_ack = irq_gc_ack_set_bit; 333 ct->chip.irq_mask = irq_gc_mask_clr_bit; 334 ct->chip.irq_unmask = irq_gc_mask_set_bit; 335 ct->chip.irq_set_type = gpio_set_irq_type; 336 ct->chip.irq_set_wake = gpio_set_wake_irq; 337 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND; 338 ct->regs.ack = GPIO_ISR; 339 ct->regs.mask = GPIO_IMR; 340 341 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), 342 IRQ_GC_INIT_NESTED_LOCK, 343 IRQ_NOREQUEST, 0); 344 345 return rv; 346 } 347 348 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 349 { 350 struct mxc_gpio_port *port = gpiochip_get_data(gc); 351 352 return irq_find_mapping(port->domain, offset); 353 } 354 355 static int mxc_gpio_probe(struct platform_device *pdev) 356 { 357 struct device_node *np = pdev->dev.of_node; 358 struct mxc_gpio_port *port; 359 int irq_count; 360 int irq_base; 361 int err; 362 363 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 364 if (!port) 365 return -ENOMEM; 366 367 port->dev = &pdev->dev; 368 369 port->hwdata = device_get_match_data(&pdev->dev); 370 371 port->base = devm_platform_ioremap_resource(pdev, 0); 372 if (IS_ERR(port->base)) 373 return PTR_ERR(port->base); 374 375 irq_count = platform_irq_count(pdev); 376 if (irq_count < 0) 377 return irq_count; 378 379 if (irq_count > 1) { 380 port->irq_high = platform_get_irq(pdev, 1); 381 if (port->irq_high < 0) 382 port->irq_high = 0; 383 } 384 385 port->irq = platform_get_irq(pdev, 0); 386 if (port->irq < 0) 387 return port->irq; 388 389 /* the controller clock is optional */ 390 port->clk = devm_clk_get_optional(&pdev->dev, NULL); 391 if (IS_ERR(port->clk)) 392 return PTR_ERR(port->clk); 393 394 err = clk_prepare_enable(port->clk); 395 if (err) { 396 dev_err(&pdev->dev, "Unable to enable clock.\n"); 397 return err; 398 } 399 400 if (of_device_is_compatible(np, "fsl,imx7d-gpio")) 401 port->power_off = true; 402 403 /* disable the interrupt and clear the status */ 404 writel(0, port->base + GPIO_IMR); 405 writel(~0, port->base + GPIO_ISR); 406 407 if (of_device_is_compatible(np, "fsl,imx21-gpio")) { 408 /* 409 * Setup one handler for all GPIO interrupts. Actually setting 410 * the handler is needed only once, but doing it for every port 411 * is more robust and easier. 412 */ 413 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); 414 } else { 415 /* setup one handler for each entry */ 416 irq_set_chained_handler_and_data(port->irq, 417 mx3_gpio_irq_handler, port); 418 if (port->irq_high > 0) 419 /* setup handler for GPIO 16 to 31 */ 420 irq_set_chained_handler_and_data(port->irq_high, 421 mx3_gpio_irq_handler, 422 port); 423 } 424 425 err = bgpio_init(&port->gc, &pdev->dev, 4, 426 port->base + GPIO_PSR, 427 port->base + GPIO_DR, NULL, 428 port->base + GPIO_GDIR, NULL, 429 BGPIOF_READ_OUTPUT_REG_SET); 430 if (err) 431 goto out_bgio; 432 433 port->gc.request = gpiochip_generic_request; 434 port->gc.free = gpiochip_generic_free; 435 port->gc.to_irq = mxc_gpio_to_irq; 436 port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : 437 pdev->id * 32; 438 439 err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port); 440 if (err) 441 goto out_bgio; 442 443 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); 444 if (irq_base < 0) { 445 err = irq_base; 446 goto out_bgio; 447 } 448 449 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, 450 &irq_domain_simple_ops, NULL); 451 if (!port->domain) { 452 err = -ENODEV; 453 goto out_bgio; 454 } 455 456 /* gpio-mxc can be a generic irq chip */ 457 err = mxc_gpio_init_gc(port, irq_base); 458 if (err < 0) 459 goto out_irqdomain_remove; 460 461 list_add_tail(&port->node, &mxc_gpio_ports); 462 463 platform_set_drvdata(pdev, port); 464 465 return 0; 466 467 out_irqdomain_remove: 468 irq_domain_remove(port->domain); 469 out_bgio: 470 clk_disable_unprepare(port->clk); 471 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 472 return err; 473 } 474 475 static void mxc_gpio_save_regs(struct mxc_gpio_port *port) 476 { 477 if (!port->power_off) 478 return; 479 480 port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1); 481 port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2); 482 port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR); 483 port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR); 484 port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL); 485 port->gpio_saved_reg.dr = readl(port->base + GPIO_DR); 486 } 487 488 static void mxc_gpio_restore_regs(struct mxc_gpio_port *port) 489 { 490 if (!port->power_off) 491 return; 492 493 writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1); 494 writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2); 495 writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR); 496 writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR); 497 writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL); 498 writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); 499 } 500 501 static int mxc_gpio_syscore_suspend(void) 502 { 503 struct mxc_gpio_port *port; 504 505 /* walk through all ports */ 506 list_for_each_entry(port, &mxc_gpio_ports, node) { 507 mxc_gpio_save_regs(port); 508 clk_disable_unprepare(port->clk); 509 } 510 511 return 0; 512 } 513 514 static void mxc_gpio_syscore_resume(void) 515 { 516 struct mxc_gpio_port *port; 517 int ret; 518 519 /* walk through all ports */ 520 list_for_each_entry(port, &mxc_gpio_ports, node) { 521 ret = clk_prepare_enable(port->clk); 522 if (ret) { 523 pr_err("mxc: failed to enable gpio clock %d\n", ret); 524 return; 525 } 526 mxc_gpio_restore_regs(port); 527 } 528 } 529 530 static struct syscore_ops mxc_gpio_syscore_ops = { 531 .suspend = mxc_gpio_syscore_suspend, 532 .resume = mxc_gpio_syscore_resume, 533 }; 534 535 static struct platform_driver mxc_gpio_driver = { 536 .driver = { 537 .name = "gpio-mxc", 538 .of_match_table = mxc_gpio_dt_ids, 539 .suppress_bind_attrs = true, 540 }, 541 .probe = mxc_gpio_probe, 542 }; 543 544 static int __init gpio_mxc_init(void) 545 { 546 register_syscore_ops(&mxc_gpio_syscore_ops); 547 548 return platform_driver_register(&mxc_gpio_driver); 549 } 550 subsys_initcall(gpio_mxc_init); 551 552 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 553 MODULE_DESCRIPTION("i.MX GPIO Driver"); 554 MODULE_LICENSE("GPL"); 555