1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 4 // Copyright 2008 Juergen Beisert, kernel@pengutronix.de 5 // 6 // Based on code from Freescale Semiconductor, 7 // Authors: Daniel Mack, Juergen Beisert. 8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9 10 #include <linux/clk.h> 11 #include <linux/err.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/platform_device.h> 19 #include <linux/slab.h> 20 #include <linux/gpio/driver.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/bug.h> 24 25 enum mxc_gpio_hwtype { 26 IMX1_GPIO, /* runs on i.mx1 */ 27 IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ 28 IMX31_GPIO, /* runs on i.mx31 */ 29 IMX35_GPIO, /* runs on all other i.mx */ 30 }; 31 32 /* device type dependent stuff */ 33 struct mxc_gpio_hwdata { 34 unsigned dr_reg; 35 unsigned gdir_reg; 36 unsigned psr_reg; 37 unsigned icr1_reg; 38 unsigned icr2_reg; 39 unsigned imr_reg; 40 unsigned isr_reg; 41 int edge_sel_reg; 42 unsigned low_level; 43 unsigned high_level; 44 unsigned rise_edge; 45 unsigned fall_edge; 46 }; 47 48 struct mxc_gpio_port { 49 struct list_head node; 50 void __iomem *base; 51 struct clk *clk; 52 int irq; 53 int irq_high; 54 struct irq_domain *domain; 55 struct gpio_chip gc; 56 struct device *dev; 57 u32 both_edges; 58 }; 59 60 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 61 .dr_reg = 0x1c, 62 .gdir_reg = 0x00, 63 .psr_reg = 0x24, 64 .icr1_reg = 0x28, 65 .icr2_reg = 0x2c, 66 .imr_reg = 0x30, 67 .isr_reg = 0x34, 68 .edge_sel_reg = -EINVAL, 69 .low_level = 0x03, 70 .high_level = 0x02, 71 .rise_edge = 0x00, 72 .fall_edge = 0x01, 73 }; 74 75 static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 76 .dr_reg = 0x00, 77 .gdir_reg = 0x04, 78 .psr_reg = 0x08, 79 .icr1_reg = 0x0c, 80 .icr2_reg = 0x10, 81 .imr_reg = 0x14, 82 .isr_reg = 0x18, 83 .edge_sel_reg = -EINVAL, 84 .low_level = 0x00, 85 .high_level = 0x01, 86 .rise_edge = 0x02, 87 .fall_edge = 0x03, 88 }; 89 90 static struct mxc_gpio_hwdata imx35_gpio_hwdata = { 91 .dr_reg = 0x00, 92 .gdir_reg = 0x04, 93 .psr_reg = 0x08, 94 .icr1_reg = 0x0c, 95 .icr2_reg = 0x10, 96 .imr_reg = 0x14, 97 .isr_reg = 0x18, 98 .edge_sel_reg = 0x1c, 99 .low_level = 0x00, 100 .high_level = 0x01, 101 .rise_edge = 0x02, 102 .fall_edge = 0x03, 103 }; 104 105 static enum mxc_gpio_hwtype mxc_gpio_hwtype; 106 static struct mxc_gpio_hwdata *mxc_gpio_hwdata; 107 108 #define GPIO_DR (mxc_gpio_hwdata->dr_reg) 109 #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg) 110 #define GPIO_PSR (mxc_gpio_hwdata->psr_reg) 111 #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg) 112 #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg) 113 #define GPIO_IMR (mxc_gpio_hwdata->imr_reg) 114 #define GPIO_ISR (mxc_gpio_hwdata->isr_reg) 115 #define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg) 116 117 #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level) 118 #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level) 119 #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge) 120 #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge) 121 #define GPIO_INT_BOTH_EDGES 0x4 122 123 static const struct platform_device_id mxc_gpio_devtype[] = { 124 { 125 .name = "imx1-gpio", 126 .driver_data = IMX1_GPIO, 127 }, { 128 .name = "imx21-gpio", 129 .driver_data = IMX21_GPIO, 130 }, { 131 .name = "imx31-gpio", 132 .driver_data = IMX31_GPIO, 133 }, { 134 .name = "imx35-gpio", 135 .driver_data = IMX35_GPIO, 136 }, { 137 /* sentinel */ 138 } 139 }; 140 141 static const struct of_device_id mxc_gpio_dt_ids[] = { 142 { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], }, 143 { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], }, 144 { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], }, 145 { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], }, 146 { /* sentinel */ } 147 }; 148 149 /* 150 * MX2 has one interrupt *for all* gpio ports. The list is used 151 * to save the references to all ports, so that mx2_gpio_irq_handler 152 * can walk through all interrupt status registers. 153 */ 154 static LIST_HEAD(mxc_gpio_ports); 155 156 /* Note: This driver assumes 32 GPIOs are handled in one register */ 157 158 static int gpio_set_irq_type(struct irq_data *d, u32 type) 159 { 160 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 161 struct mxc_gpio_port *port = gc->private; 162 u32 bit, val; 163 u32 gpio_idx = d->hwirq; 164 int edge; 165 void __iomem *reg = port->base; 166 167 port->both_edges &= ~(1 << gpio_idx); 168 switch (type) { 169 case IRQ_TYPE_EDGE_RISING: 170 edge = GPIO_INT_RISE_EDGE; 171 break; 172 case IRQ_TYPE_EDGE_FALLING: 173 edge = GPIO_INT_FALL_EDGE; 174 break; 175 case IRQ_TYPE_EDGE_BOTH: 176 if (GPIO_EDGE_SEL >= 0) { 177 edge = GPIO_INT_BOTH_EDGES; 178 } else { 179 val = port->gc.get(&port->gc, gpio_idx); 180 if (val) { 181 edge = GPIO_INT_LOW_LEV; 182 pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx); 183 } else { 184 edge = GPIO_INT_HIGH_LEV; 185 pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx); 186 } 187 port->both_edges |= 1 << gpio_idx; 188 } 189 break; 190 case IRQ_TYPE_LEVEL_LOW: 191 edge = GPIO_INT_LOW_LEV; 192 break; 193 case IRQ_TYPE_LEVEL_HIGH: 194 edge = GPIO_INT_HIGH_LEV; 195 break; 196 default: 197 return -EINVAL; 198 } 199 200 if (GPIO_EDGE_SEL >= 0) { 201 val = readl(port->base + GPIO_EDGE_SEL); 202 if (edge == GPIO_INT_BOTH_EDGES) 203 writel(val | (1 << gpio_idx), 204 port->base + GPIO_EDGE_SEL); 205 else 206 writel(val & ~(1 << gpio_idx), 207 port->base + GPIO_EDGE_SEL); 208 } 209 210 if (edge != GPIO_INT_BOTH_EDGES) { 211 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ 212 bit = gpio_idx & 0xf; 213 val = readl(reg) & ~(0x3 << (bit << 1)); 214 writel(val | (edge << (bit << 1)), reg); 215 } 216 217 writel(1 << gpio_idx, port->base + GPIO_ISR); 218 219 return 0; 220 } 221 222 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 223 { 224 void __iomem *reg = port->base; 225 u32 bit, val; 226 int edge; 227 228 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 229 bit = gpio & 0xf; 230 val = readl(reg); 231 edge = (val >> (bit << 1)) & 3; 232 val &= ~(0x3 << (bit << 1)); 233 if (edge == GPIO_INT_HIGH_LEV) { 234 edge = GPIO_INT_LOW_LEV; 235 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 236 } else if (edge == GPIO_INT_LOW_LEV) { 237 edge = GPIO_INT_HIGH_LEV; 238 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 239 } else { 240 pr_err("mxc: invalid configuration for GPIO %d: %x\n", 241 gpio, edge); 242 return; 243 } 244 writel(val | (edge << (bit << 1)), reg); 245 } 246 247 /* handle 32 interrupts in one status register */ 248 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 249 { 250 while (irq_stat != 0) { 251 int irqoffset = fls(irq_stat) - 1; 252 253 if (port->both_edges & (1 << irqoffset)) 254 mxc_flip_edge(port, irqoffset); 255 256 generic_handle_irq(irq_find_mapping(port->domain, irqoffset)); 257 258 irq_stat &= ~(1 << irqoffset); 259 } 260 } 261 262 /* MX1 and MX3 has one interrupt *per* gpio port */ 263 static void mx3_gpio_irq_handler(struct irq_desc *desc) 264 { 265 u32 irq_stat; 266 struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); 267 struct irq_chip *chip = irq_desc_get_chip(desc); 268 269 chained_irq_enter(chip, desc); 270 271 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 272 273 mxc_gpio_irq_handler(port, irq_stat); 274 275 chained_irq_exit(chip, desc); 276 } 277 278 /* MX2 has one interrupt *for all* gpio ports */ 279 static void mx2_gpio_irq_handler(struct irq_desc *desc) 280 { 281 u32 irq_msk, irq_stat; 282 struct mxc_gpio_port *port; 283 struct irq_chip *chip = irq_desc_get_chip(desc); 284 285 chained_irq_enter(chip, desc); 286 287 /* walk through all interrupt status registers */ 288 list_for_each_entry(port, &mxc_gpio_ports, node) { 289 irq_msk = readl(port->base + GPIO_IMR); 290 if (!irq_msk) 291 continue; 292 293 irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 294 if (irq_stat) 295 mxc_gpio_irq_handler(port, irq_stat); 296 } 297 chained_irq_exit(chip, desc); 298 } 299 300 /* 301 * Set interrupt number "irq" in the GPIO as a wake-up source. 302 * While system is running, all registered GPIO interrupts need to have 303 * wake-up enabled. When system is suspended, only selected GPIO interrupts 304 * need to have wake-up enabled. 305 * @param irq interrupt source number 306 * @param enable enable as wake-up if equal to non-zero 307 * @return This function returns 0 on success. 308 */ 309 static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 310 { 311 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 312 struct mxc_gpio_port *port = gc->private; 313 u32 gpio_idx = d->hwirq; 314 int ret; 315 316 if (enable) { 317 if (port->irq_high && (gpio_idx >= 16)) 318 ret = enable_irq_wake(port->irq_high); 319 else 320 ret = enable_irq_wake(port->irq); 321 } else { 322 if (port->irq_high && (gpio_idx >= 16)) 323 ret = disable_irq_wake(port->irq_high); 324 else 325 ret = disable_irq_wake(port->irq); 326 } 327 328 return ret; 329 } 330 331 static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) 332 { 333 struct irq_chip_generic *gc; 334 struct irq_chip_type *ct; 335 int rv; 336 337 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base, 338 port->base, handle_level_irq); 339 if (!gc) 340 return -ENOMEM; 341 gc->private = port; 342 343 ct = gc->chip_types; 344 ct->chip.irq_ack = irq_gc_ack_set_bit; 345 ct->chip.irq_mask = irq_gc_mask_clr_bit; 346 ct->chip.irq_unmask = irq_gc_mask_set_bit; 347 ct->chip.irq_set_type = gpio_set_irq_type; 348 ct->chip.irq_set_wake = gpio_set_wake_irq; 349 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND; 350 ct->regs.ack = GPIO_ISR; 351 ct->regs.mask = GPIO_IMR; 352 353 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), 354 IRQ_GC_INIT_NESTED_LOCK, 355 IRQ_NOREQUEST, 0); 356 357 return rv; 358 } 359 360 static void mxc_gpio_get_hw(struct platform_device *pdev) 361 { 362 const struct of_device_id *of_id = 363 of_match_device(mxc_gpio_dt_ids, &pdev->dev); 364 enum mxc_gpio_hwtype hwtype; 365 366 if (of_id) 367 pdev->id_entry = of_id->data; 368 hwtype = pdev->id_entry->driver_data; 369 370 if (mxc_gpio_hwtype) { 371 /* 372 * The driver works with a reasonable presupposition, 373 * that is all gpio ports must be the same type when 374 * running on one soc. 375 */ 376 BUG_ON(mxc_gpio_hwtype != hwtype); 377 return; 378 } 379 380 if (hwtype == IMX35_GPIO) 381 mxc_gpio_hwdata = &imx35_gpio_hwdata; 382 else if (hwtype == IMX31_GPIO) 383 mxc_gpio_hwdata = &imx31_gpio_hwdata; 384 else 385 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata; 386 387 mxc_gpio_hwtype = hwtype; 388 } 389 390 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 391 { 392 struct mxc_gpio_port *port = gpiochip_get_data(gc); 393 394 return irq_find_mapping(port->domain, offset); 395 } 396 397 static int mxc_gpio_probe(struct platform_device *pdev) 398 { 399 struct device_node *np = pdev->dev.of_node; 400 struct mxc_gpio_port *port; 401 struct resource *iores; 402 int irq_base; 403 int err; 404 405 mxc_gpio_get_hw(pdev); 406 407 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 408 if (!port) 409 return -ENOMEM; 410 411 port->dev = &pdev->dev; 412 413 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 414 port->base = devm_ioremap_resource(&pdev->dev, iores); 415 if (IS_ERR(port->base)) 416 return PTR_ERR(port->base); 417 418 port->irq_high = platform_get_irq(pdev, 1); 419 if (port->irq_high < 0) 420 port->irq_high = 0; 421 422 port->irq = platform_get_irq(pdev, 0); 423 if (port->irq < 0) 424 return port->irq; 425 426 /* the controller clock is optional */ 427 port->clk = devm_clk_get(&pdev->dev, NULL); 428 if (IS_ERR(port->clk)) 429 port->clk = NULL; 430 431 err = clk_prepare_enable(port->clk); 432 if (err) { 433 dev_err(&pdev->dev, "Unable to enable clock.\n"); 434 return err; 435 } 436 437 /* disable the interrupt and clear the status */ 438 writel(0, port->base + GPIO_IMR); 439 writel(~0, port->base + GPIO_ISR); 440 441 if (mxc_gpio_hwtype == IMX21_GPIO) { 442 /* 443 * Setup one handler for all GPIO interrupts. Actually setting 444 * the handler is needed only once, but doing it for every port 445 * is more robust and easier. 446 */ 447 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); 448 } else { 449 /* setup one handler for each entry */ 450 irq_set_chained_handler_and_data(port->irq, 451 mx3_gpio_irq_handler, port); 452 if (port->irq_high > 0) 453 /* setup handler for GPIO 16 to 31 */ 454 irq_set_chained_handler_and_data(port->irq_high, 455 mx3_gpio_irq_handler, 456 port); 457 } 458 459 err = bgpio_init(&port->gc, &pdev->dev, 4, 460 port->base + GPIO_PSR, 461 port->base + GPIO_DR, NULL, 462 port->base + GPIO_GDIR, NULL, 463 BGPIOF_READ_OUTPUT_REG_SET); 464 if (err) 465 goto out_bgio; 466 467 if (of_property_read_bool(np, "gpio-ranges")) { 468 port->gc.request = gpiochip_generic_request; 469 port->gc.free = gpiochip_generic_free; 470 } 471 472 port->gc.to_irq = mxc_gpio_to_irq; 473 port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : 474 pdev->id * 32; 475 476 err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port); 477 if (err) 478 goto out_bgio; 479 480 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); 481 if (irq_base < 0) { 482 err = irq_base; 483 goto out_bgio; 484 } 485 486 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, 487 &irq_domain_simple_ops, NULL); 488 if (!port->domain) { 489 err = -ENODEV; 490 goto out_bgio; 491 } 492 493 /* gpio-mxc can be a generic irq chip */ 494 err = mxc_gpio_init_gc(port, irq_base); 495 if (err < 0) 496 goto out_irqdomain_remove; 497 498 list_add_tail(&port->node, &mxc_gpio_ports); 499 500 return 0; 501 502 out_irqdomain_remove: 503 irq_domain_remove(port->domain); 504 out_bgio: 505 clk_disable_unprepare(port->clk); 506 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 507 return err; 508 } 509 510 static struct platform_driver mxc_gpio_driver = { 511 .driver = { 512 .name = "gpio-mxc", 513 .of_match_table = mxc_gpio_dt_ids, 514 .suppress_bind_attrs = true, 515 }, 516 .probe = mxc_gpio_probe, 517 .id_table = mxc_gpio_devtype, 518 }; 519 520 static int __init gpio_mxc_init(void) 521 { 522 return platform_driver_register(&mxc_gpio_driver); 523 } 524 subsys_initcall(gpio_mxc_init); 525