xref: /openbmc/linux/drivers/gpio/gpio-mxc.c (revision 5b394b2d) 
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
4 // Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5 //
6 // Based on code from Freescale Semiconductor,
7 // Authors: Daniel Mack, Juergen Beisert.
8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9 
10 #include <linux/clk.h>
11 #include <linux/err.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/gpio/driver.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/bug.h>
24 
25 enum mxc_gpio_hwtype {
26 	IMX1_GPIO,	/* runs on i.mx1 */
27 	IMX21_GPIO,	/* runs on i.mx21 and i.mx27 */
28 	IMX31_GPIO,	/* runs on i.mx31 */
29 	IMX35_GPIO,	/* runs on all other i.mx */
30 };
31 
32 /* device type dependent stuff */
33 struct mxc_gpio_hwdata {
34 	unsigned dr_reg;
35 	unsigned gdir_reg;
36 	unsigned psr_reg;
37 	unsigned icr1_reg;
38 	unsigned icr2_reg;
39 	unsigned imr_reg;
40 	unsigned isr_reg;
41 	int edge_sel_reg;
42 	unsigned low_level;
43 	unsigned high_level;
44 	unsigned rise_edge;
45 	unsigned fall_edge;
46 };
47 
48 struct mxc_gpio_reg_saved {
49 	u32 icr1;
50 	u32 icr2;
51 	u32 imr;
52 	u32 gdir;
53 	u32 edge_sel;
54 	u32 dr;
55 };
56 
57 struct mxc_gpio_port {
58 	struct list_head node;
59 	void __iomem *base;
60 	struct clk *clk;
61 	int irq;
62 	int irq_high;
63 	struct irq_domain *domain;
64 	struct gpio_chip gc;
65 	struct device *dev;
66 	u32 both_edges;
67 	struct mxc_gpio_reg_saved gpio_saved_reg;
68 	bool power_off;
69 };
70 
71 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
72 	.dr_reg		= 0x1c,
73 	.gdir_reg	= 0x00,
74 	.psr_reg	= 0x24,
75 	.icr1_reg	= 0x28,
76 	.icr2_reg	= 0x2c,
77 	.imr_reg	= 0x30,
78 	.isr_reg	= 0x34,
79 	.edge_sel_reg	= -EINVAL,
80 	.low_level	= 0x03,
81 	.high_level	= 0x02,
82 	.rise_edge	= 0x00,
83 	.fall_edge	= 0x01,
84 };
85 
86 static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
87 	.dr_reg		= 0x00,
88 	.gdir_reg	= 0x04,
89 	.psr_reg	= 0x08,
90 	.icr1_reg	= 0x0c,
91 	.icr2_reg	= 0x10,
92 	.imr_reg	= 0x14,
93 	.isr_reg	= 0x18,
94 	.edge_sel_reg	= -EINVAL,
95 	.low_level	= 0x00,
96 	.high_level	= 0x01,
97 	.rise_edge	= 0x02,
98 	.fall_edge	= 0x03,
99 };
100 
101 static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
102 	.dr_reg		= 0x00,
103 	.gdir_reg	= 0x04,
104 	.psr_reg	= 0x08,
105 	.icr1_reg	= 0x0c,
106 	.icr2_reg	= 0x10,
107 	.imr_reg	= 0x14,
108 	.isr_reg	= 0x18,
109 	.edge_sel_reg	= 0x1c,
110 	.low_level	= 0x00,
111 	.high_level	= 0x01,
112 	.rise_edge	= 0x02,
113 	.fall_edge	= 0x03,
114 };
115 
116 static enum mxc_gpio_hwtype mxc_gpio_hwtype;
117 static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
118 
119 #define GPIO_DR			(mxc_gpio_hwdata->dr_reg)
120 #define GPIO_GDIR		(mxc_gpio_hwdata->gdir_reg)
121 #define GPIO_PSR		(mxc_gpio_hwdata->psr_reg)
122 #define GPIO_ICR1		(mxc_gpio_hwdata->icr1_reg)
123 #define GPIO_ICR2		(mxc_gpio_hwdata->icr2_reg)
124 #define GPIO_IMR		(mxc_gpio_hwdata->imr_reg)
125 #define GPIO_ISR		(mxc_gpio_hwdata->isr_reg)
126 #define GPIO_EDGE_SEL		(mxc_gpio_hwdata->edge_sel_reg)
127 
128 #define GPIO_INT_LOW_LEV	(mxc_gpio_hwdata->low_level)
129 #define GPIO_INT_HIGH_LEV	(mxc_gpio_hwdata->high_level)
130 #define GPIO_INT_RISE_EDGE	(mxc_gpio_hwdata->rise_edge)
131 #define GPIO_INT_FALL_EDGE	(mxc_gpio_hwdata->fall_edge)
132 #define GPIO_INT_BOTH_EDGES	0x4
133 
134 static const struct platform_device_id mxc_gpio_devtype[] = {
135 	{
136 		.name = "imx1-gpio",
137 		.driver_data = IMX1_GPIO,
138 	}, {
139 		.name = "imx21-gpio",
140 		.driver_data = IMX21_GPIO,
141 	}, {
142 		.name = "imx31-gpio",
143 		.driver_data = IMX31_GPIO,
144 	}, {
145 		.name = "imx35-gpio",
146 		.driver_data = IMX35_GPIO,
147 	}, {
148 		/* sentinel */
149 	}
150 };
151 
152 static const struct of_device_id mxc_gpio_dt_ids[] = {
153 	{ .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
154 	{ .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
155 	{ .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
156 	{ .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
157 	{ .compatible = "fsl,imx7d-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
158 	{ /* sentinel */ }
159 };
160 
161 /*
162  * MX2 has one interrupt *for all* gpio ports. The list is used
163  * to save the references to all ports, so that mx2_gpio_irq_handler
164  * can walk through all interrupt status registers.
165  */
166 static LIST_HEAD(mxc_gpio_ports);
167 
168 /* Note: This driver assumes 32 GPIOs are handled in one register */
169 
170 static int gpio_set_irq_type(struct irq_data *d, u32 type)
171 {
172 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
173 	struct mxc_gpio_port *port = gc->private;
174 	u32 bit, val;
175 	u32 gpio_idx = d->hwirq;
176 	int edge;
177 	void __iomem *reg = port->base;
178 
179 	port->both_edges &= ~(1 << gpio_idx);
180 	switch (type) {
181 	case IRQ_TYPE_EDGE_RISING:
182 		edge = GPIO_INT_RISE_EDGE;
183 		break;
184 	case IRQ_TYPE_EDGE_FALLING:
185 		edge = GPIO_INT_FALL_EDGE;
186 		break;
187 	case IRQ_TYPE_EDGE_BOTH:
188 		if (GPIO_EDGE_SEL >= 0) {
189 			edge = GPIO_INT_BOTH_EDGES;
190 		} else {
191 			val = port->gc.get(&port->gc, gpio_idx);
192 			if (val) {
193 				edge = GPIO_INT_LOW_LEV;
194 				pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
195 			} else {
196 				edge = GPIO_INT_HIGH_LEV;
197 				pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
198 			}
199 			port->both_edges |= 1 << gpio_idx;
200 		}
201 		break;
202 	case IRQ_TYPE_LEVEL_LOW:
203 		edge = GPIO_INT_LOW_LEV;
204 		break;
205 	case IRQ_TYPE_LEVEL_HIGH:
206 		edge = GPIO_INT_HIGH_LEV;
207 		break;
208 	default:
209 		return -EINVAL;
210 	}
211 
212 	if (GPIO_EDGE_SEL >= 0) {
213 		val = readl(port->base + GPIO_EDGE_SEL);
214 		if (edge == GPIO_INT_BOTH_EDGES)
215 			writel(val | (1 << gpio_idx),
216 				port->base + GPIO_EDGE_SEL);
217 		else
218 			writel(val & ~(1 << gpio_idx),
219 				port->base + GPIO_EDGE_SEL);
220 	}
221 
222 	if (edge != GPIO_INT_BOTH_EDGES) {
223 		reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
224 		bit = gpio_idx & 0xf;
225 		val = readl(reg) & ~(0x3 << (bit << 1));
226 		writel(val | (edge << (bit << 1)), reg);
227 	}
228 
229 	writel(1 << gpio_idx, port->base + GPIO_ISR);
230 
231 	return 0;
232 }
233 
234 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
235 {
236 	void __iomem *reg = port->base;
237 	u32 bit, val;
238 	int edge;
239 
240 	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
241 	bit = gpio & 0xf;
242 	val = readl(reg);
243 	edge = (val >> (bit << 1)) & 3;
244 	val &= ~(0x3 << (bit << 1));
245 	if (edge == GPIO_INT_HIGH_LEV) {
246 		edge = GPIO_INT_LOW_LEV;
247 		pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
248 	} else if (edge == GPIO_INT_LOW_LEV) {
249 		edge = GPIO_INT_HIGH_LEV;
250 		pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
251 	} else {
252 		pr_err("mxc: invalid configuration for GPIO %d: %x\n",
253 		       gpio, edge);
254 		return;
255 	}
256 	writel(val | (edge << (bit << 1)), reg);
257 }
258 
259 /* handle 32 interrupts in one status register */
260 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
261 {
262 	while (irq_stat != 0) {
263 		int irqoffset = fls(irq_stat) - 1;
264 
265 		if (port->both_edges & (1 << irqoffset))
266 			mxc_flip_edge(port, irqoffset);
267 
268 		generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
269 
270 		irq_stat &= ~(1 << irqoffset);
271 	}
272 }
273 
274 /* MX1 and MX3 has one interrupt *per* gpio port */
275 static void mx3_gpio_irq_handler(struct irq_desc *desc)
276 {
277 	u32 irq_stat;
278 	struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
279 	struct irq_chip *chip = irq_desc_get_chip(desc);
280 
281 	chained_irq_enter(chip, desc);
282 
283 	irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
284 
285 	mxc_gpio_irq_handler(port, irq_stat);
286 
287 	chained_irq_exit(chip, desc);
288 }
289 
290 /* MX2 has one interrupt *for all* gpio ports */
291 static void mx2_gpio_irq_handler(struct irq_desc *desc)
292 {
293 	u32 irq_msk, irq_stat;
294 	struct mxc_gpio_port *port;
295 	struct irq_chip *chip = irq_desc_get_chip(desc);
296 
297 	chained_irq_enter(chip, desc);
298 
299 	/* walk through all interrupt status registers */
300 	list_for_each_entry(port, &mxc_gpio_ports, node) {
301 		irq_msk = readl(port->base + GPIO_IMR);
302 		if (!irq_msk)
303 			continue;
304 
305 		irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
306 		if (irq_stat)
307 			mxc_gpio_irq_handler(port, irq_stat);
308 	}
309 	chained_irq_exit(chip, desc);
310 }
311 
312 /*
313  * Set interrupt number "irq" in the GPIO as a wake-up source.
314  * While system is running, all registered GPIO interrupts need to have
315  * wake-up enabled. When system is suspended, only selected GPIO interrupts
316  * need to have wake-up enabled.
317  * @param  irq          interrupt source number
318  * @param  enable       enable as wake-up if equal to non-zero
319  * @return       This function returns 0 on success.
320  */
321 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
322 {
323 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
324 	struct mxc_gpio_port *port = gc->private;
325 	u32 gpio_idx = d->hwirq;
326 	int ret;
327 
328 	if (enable) {
329 		if (port->irq_high && (gpio_idx >= 16))
330 			ret = enable_irq_wake(port->irq_high);
331 		else
332 			ret = enable_irq_wake(port->irq);
333 	} else {
334 		if (port->irq_high && (gpio_idx >= 16))
335 			ret = disable_irq_wake(port->irq_high);
336 		else
337 			ret = disable_irq_wake(port->irq);
338 	}
339 
340 	return ret;
341 }
342 
343 static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
344 {
345 	struct irq_chip_generic *gc;
346 	struct irq_chip_type *ct;
347 	int rv;
348 
349 	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
350 					 port->base, handle_level_irq);
351 	if (!gc)
352 		return -ENOMEM;
353 	gc->private = port;
354 
355 	ct = gc->chip_types;
356 	ct->chip.irq_ack = irq_gc_ack_set_bit;
357 	ct->chip.irq_mask = irq_gc_mask_clr_bit;
358 	ct->chip.irq_unmask = irq_gc_mask_set_bit;
359 	ct->chip.irq_set_type = gpio_set_irq_type;
360 	ct->chip.irq_set_wake = gpio_set_wake_irq;
361 	ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
362 	ct->regs.ack = GPIO_ISR;
363 	ct->regs.mask = GPIO_IMR;
364 
365 	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
366 					 IRQ_GC_INIT_NESTED_LOCK,
367 					 IRQ_NOREQUEST, 0);
368 
369 	return rv;
370 }
371 
372 static void mxc_gpio_get_hw(struct platform_device *pdev)
373 {
374 	const struct of_device_id *of_id =
375 			of_match_device(mxc_gpio_dt_ids, &pdev->dev);
376 	enum mxc_gpio_hwtype hwtype;
377 
378 	if (of_id)
379 		pdev->id_entry = of_id->data;
380 	hwtype = pdev->id_entry->driver_data;
381 
382 	if (mxc_gpio_hwtype) {
383 		/*
384 		 * The driver works with a reasonable presupposition,
385 		 * that is all gpio ports must be the same type when
386 		 * running on one soc.
387 		 */
388 		BUG_ON(mxc_gpio_hwtype != hwtype);
389 		return;
390 	}
391 
392 	if (hwtype == IMX35_GPIO)
393 		mxc_gpio_hwdata = &imx35_gpio_hwdata;
394 	else if (hwtype == IMX31_GPIO)
395 		mxc_gpio_hwdata = &imx31_gpio_hwdata;
396 	else
397 		mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
398 
399 	mxc_gpio_hwtype = hwtype;
400 }
401 
402 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
403 {
404 	struct mxc_gpio_port *port = gpiochip_get_data(gc);
405 
406 	return irq_find_mapping(port->domain, offset);
407 }
408 
409 static int mxc_gpio_probe(struct platform_device *pdev)
410 {
411 	struct device_node *np = pdev->dev.of_node;
412 	struct mxc_gpio_port *port;
413 	struct resource *iores;
414 	int irq_base;
415 	int err;
416 
417 	mxc_gpio_get_hw(pdev);
418 
419 	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
420 	if (!port)
421 		return -ENOMEM;
422 
423 	port->dev = &pdev->dev;
424 
425 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
426 	port->base = devm_ioremap_resource(&pdev->dev, iores);
427 	if (IS_ERR(port->base))
428 		return PTR_ERR(port->base);
429 
430 	port->irq_high = platform_get_irq(pdev, 1);
431 	if (port->irq_high < 0)
432 		port->irq_high = 0;
433 
434 	port->irq = platform_get_irq(pdev, 0);
435 	if (port->irq < 0)
436 		return port->irq;
437 
438 	/* the controller clock is optional */
439 	port->clk = devm_clk_get(&pdev->dev, NULL);
440 	if (IS_ERR(port->clk))
441 		port->clk = NULL;
442 
443 	err = clk_prepare_enable(port->clk);
444 	if (err) {
445 		dev_err(&pdev->dev, "Unable to enable clock.\n");
446 		return err;
447 	}
448 
449 	if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
450 		port->power_off = true;
451 
452 	/* disable the interrupt and clear the status */
453 	writel(0, port->base + GPIO_IMR);
454 	writel(~0, port->base + GPIO_ISR);
455 
456 	if (mxc_gpio_hwtype == IMX21_GPIO) {
457 		/*
458 		 * Setup one handler for all GPIO interrupts. Actually setting
459 		 * the handler is needed only once, but doing it for every port
460 		 * is more robust and easier.
461 		 */
462 		irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
463 	} else {
464 		/* setup one handler for each entry */
465 		irq_set_chained_handler_and_data(port->irq,
466 						 mx3_gpio_irq_handler, port);
467 		if (port->irq_high > 0)
468 			/* setup handler for GPIO 16 to 31 */
469 			irq_set_chained_handler_and_data(port->irq_high,
470 							 mx3_gpio_irq_handler,
471 							 port);
472 	}
473 
474 	err = bgpio_init(&port->gc, &pdev->dev, 4,
475 			 port->base + GPIO_PSR,
476 			 port->base + GPIO_DR, NULL,
477 			 port->base + GPIO_GDIR, NULL,
478 			 BGPIOF_READ_OUTPUT_REG_SET);
479 	if (err)
480 		goto out_bgio;
481 
482 	if (of_property_read_bool(np, "gpio-ranges")) {
483 		port->gc.request = gpiochip_generic_request;
484 		port->gc.free = gpiochip_generic_free;
485 	}
486 
487 	port->gc.to_irq = mxc_gpio_to_irq;
488 	port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
489 					     pdev->id * 32;
490 
491 	err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
492 	if (err)
493 		goto out_bgio;
494 
495 	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
496 	if (irq_base < 0) {
497 		err = irq_base;
498 		goto out_bgio;
499 	}
500 
501 	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
502 					     &irq_domain_simple_ops, NULL);
503 	if (!port->domain) {
504 		err = -ENODEV;
505 		goto out_bgio;
506 	}
507 
508 	/* gpio-mxc can be a generic irq chip */
509 	err = mxc_gpio_init_gc(port, irq_base);
510 	if (err < 0)
511 		goto out_irqdomain_remove;
512 
513 	list_add_tail(&port->node, &mxc_gpio_ports);
514 
515 	platform_set_drvdata(pdev, port);
516 
517 	return 0;
518 
519 out_irqdomain_remove:
520 	irq_domain_remove(port->domain);
521 out_bgio:
522 	clk_disable_unprepare(port->clk);
523 	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
524 	return err;
525 }
526 
527 static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
528 {
529 	if (!port->power_off)
530 		return;
531 
532 	port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
533 	port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
534 	port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
535 	port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
536 	port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
537 	port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
538 }
539 
540 static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
541 {
542 	if (!port->power_off)
543 		return;
544 
545 	writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
546 	writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
547 	writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
548 	writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
549 	writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
550 	writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
551 }
552 
553 static int __maybe_unused mxc_gpio_noirq_suspend(struct device *dev)
554 {
555 	struct platform_device *pdev = to_platform_device(dev);
556 	struct mxc_gpio_port *port = platform_get_drvdata(pdev);
557 
558 	mxc_gpio_save_regs(port);
559 	clk_disable_unprepare(port->clk);
560 
561 	return 0;
562 }
563 
564 static int __maybe_unused mxc_gpio_noirq_resume(struct device *dev)
565 {
566 	struct platform_device *pdev = to_platform_device(dev);
567 	struct mxc_gpio_port *port = platform_get_drvdata(pdev);
568 	int ret;
569 
570 	ret = clk_prepare_enable(port->clk);
571 	if (ret)
572 		return ret;
573 	mxc_gpio_restore_regs(port);
574 
575 	return 0;
576 }
577 
578 static const struct dev_pm_ops mxc_gpio_dev_pm_ops = {
579 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume)
580 };
581 
582 static struct platform_driver mxc_gpio_driver = {
583 	.driver		= {
584 		.name	= "gpio-mxc",
585 		.of_match_table = mxc_gpio_dt_ids,
586 		.suppress_bind_attrs = true,
587 		.pm = &mxc_gpio_dev_pm_ops,
588 	},
589 	.probe		= mxc_gpio_probe,
590 	.id_table	= mxc_gpio_devtype,
591 };
592 
593 static int __init gpio_mxc_init(void)
594 {
595 	return platform_driver_register(&mxc_gpio_driver);
596 }
597 subsys_initcall(gpio_mxc_init);
598