xref: /openbmc/linux/drivers/gpio/gpio-mxc.c (revision 1d05334d) 
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
4 // Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5 //
6 // Based on code from Freescale Semiconductor,
7 // Authors: Daniel Mack, Juergen Beisert.
8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9 
10 #include <linux/clk.h>
11 #include <linux/err.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/syscore_ops.h>
21 #include <linux/gpio/driver.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/bug.h>
25 
26 enum mxc_gpio_hwtype {
27 	IMX1_GPIO,	/* runs on i.mx1 */
28 	IMX21_GPIO,	/* runs on i.mx21 and i.mx27 */
29 	IMX31_GPIO,	/* runs on i.mx31 */
30 	IMX35_GPIO,	/* runs on all other i.mx */
31 };
32 
33 /* device type dependent stuff */
34 struct mxc_gpio_hwdata {
35 	unsigned dr_reg;
36 	unsigned gdir_reg;
37 	unsigned psr_reg;
38 	unsigned icr1_reg;
39 	unsigned icr2_reg;
40 	unsigned imr_reg;
41 	unsigned isr_reg;
42 	int edge_sel_reg;
43 	unsigned low_level;
44 	unsigned high_level;
45 	unsigned rise_edge;
46 	unsigned fall_edge;
47 };
48 
49 struct mxc_gpio_reg_saved {
50 	u32 icr1;
51 	u32 icr2;
52 	u32 imr;
53 	u32 gdir;
54 	u32 edge_sel;
55 	u32 dr;
56 };
57 
58 struct mxc_gpio_port {
59 	struct list_head node;
60 	void __iomem *base;
61 	struct clk *clk;
62 	int irq;
63 	int irq_high;
64 	struct irq_domain *domain;
65 	struct gpio_chip gc;
66 	struct device *dev;
67 	u32 both_edges;
68 	struct mxc_gpio_reg_saved gpio_saved_reg;
69 	bool power_off;
70 };
71 
72 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
73 	.dr_reg		= 0x1c,
74 	.gdir_reg	= 0x00,
75 	.psr_reg	= 0x24,
76 	.icr1_reg	= 0x28,
77 	.icr2_reg	= 0x2c,
78 	.imr_reg	= 0x30,
79 	.isr_reg	= 0x34,
80 	.edge_sel_reg	= -EINVAL,
81 	.low_level	= 0x03,
82 	.high_level	= 0x02,
83 	.rise_edge	= 0x00,
84 	.fall_edge	= 0x01,
85 };
86 
87 static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
88 	.dr_reg		= 0x00,
89 	.gdir_reg	= 0x04,
90 	.psr_reg	= 0x08,
91 	.icr1_reg	= 0x0c,
92 	.icr2_reg	= 0x10,
93 	.imr_reg	= 0x14,
94 	.isr_reg	= 0x18,
95 	.edge_sel_reg	= -EINVAL,
96 	.low_level	= 0x00,
97 	.high_level	= 0x01,
98 	.rise_edge	= 0x02,
99 	.fall_edge	= 0x03,
100 };
101 
102 static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
103 	.dr_reg		= 0x00,
104 	.gdir_reg	= 0x04,
105 	.psr_reg	= 0x08,
106 	.icr1_reg	= 0x0c,
107 	.icr2_reg	= 0x10,
108 	.imr_reg	= 0x14,
109 	.isr_reg	= 0x18,
110 	.edge_sel_reg	= 0x1c,
111 	.low_level	= 0x00,
112 	.high_level	= 0x01,
113 	.rise_edge	= 0x02,
114 	.fall_edge	= 0x03,
115 };
116 
117 static enum mxc_gpio_hwtype mxc_gpio_hwtype;
118 static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
119 
120 #define GPIO_DR			(mxc_gpio_hwdata->dr_reg)
121 #define GPIO_GDIR		(mxc_gpio_hwdata->gdir_reg)
122 #define GPIO_PSR		(mxc_gpio_hwdata->psr_reg)
123 #define GPIO_ICR1		(mxc_gpio_hwdata->icr1_reg)
124 #define GPIO_ICR2		(mxc_gpio_hwdata->icr2_reg)
125 #define GPIO_IMR		(mxc_gpio_hwdata->imr_reg)
126 #define GPIO_ISR		(mxc_gpio_hwdata->isr_reg)
127 #define GPIO_EDGE_SEL		(mxc_gpio_hwdata->edge_sel_reg)
128 
129 #define GPIO_INT_LOW_LEV	(mxc_gpio_hwdata->low_level)
130 #define GPIO_INT_HIGH_LEV	(mxc_gpio_hwdata->high_level)
131 #define GPIO_INT_RISE_EDGE	(mxc_gpio_hwdata->rise_edge)
132 #define GPIO_INT_FALL_EDGE	(mxc_gpio_hwdata->fall_edge)
133 #define GPIO_INT_BOTH_EDGES	0x4
134 
135 static const struct platform_device_id mxc_gpio_devtype[] = {
136 	{
137 		.name = "imx1-gpio",
138 		.driver_data = IMX1_GPIO,
139 	}, {
140 		.name = "imx21-gpio",
141 		.driver_data = IMX21_GPIO,
142 	}, {
143 		.name = "imx31-gpio",
144 		.driver_data = IMX31_GPIO,
145 	}, {
146 		.name = "imx35-gpio",
147 		.driver_data = IMX35_GPIO,
148 	}, {
149 		/* sentinel */
150 	}
151 };
152 
153 static const struct of_device_id mxc_gpio_dt_ids[] = {
154 	{ .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
155 	{ .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
156 	{ .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
157 	{ .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
158 	{ .compatible = "fsl,imx7d-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
159 	{ /* sentinel */ }
160 };
161 
162 /*
163  * MX2 has one interrupt *for all* gpio ports. The list is used
164  * to save the references to all ports, so that mx2_gpio_irq_handler
165  * can walk through all interrupt status registers.
166  */
167 static LIST_HEAD(mxc_gpio_ports);
168 
169 /* Note: This driver assumes 32 GPIOs are handled in one register */
170 
171 static int gpio_set_irq_type(struct irq_data *d, u32 type)
172 {
173 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
174 	struct mxc_gpio_port *port = gc->private;
175 	u32 bit, val;
176 	u32 gpio_idx = d->hwirq;
177 	int edge;
178 	void __iomem *reg = port->base;
179 
180 	port->both_edges &= ~(1 << gpio_idx);
181 	switch (type) {
182 	case IRQ_TYPE_EDGE_RISING:
183 		edge = GPIO_INT_RISE_EDGE;
184 		break;
185 	case IRQ_TYPE_EDGE_FALLING:
186 		edge = GPIO_INT_FALL_EDGE;
187 		break;
188 	case IRQ_TYPE_EDGE_BOTH:
189 		if (GPIO_EDGE_SEL >= 0) {
190 			edge = GPIO_INT_BOTH_EDGES;
191 		} else {
192 			val = port->gc.get(&port->gc, gpio_idx);
193 			if (val) {
194 				edge = GPIO_INT_LOW_LEV;
195 				pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
196 			} else {
197 				edge = GPIO_INT_HIGH_LEV;
198 				pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
199 			}
200 			port->both_edges |= 1 << gpio_idx;
201 		}
202 		break;
203 	case IRQ_TYPE_LEVEL_LOW:
204 		edge = GPIO_INT_LOW_LEV;
205 		break;
206 	case IRQ_TYPE_LEVEL_HIGH:
207 		edge = GPIO_INT_HIGH_LEV;
208 		break;
209 	default:
210 		return -EINVAL;
211 	}
212 
213 	if (GPIO_EDGE_SEL >= 0) {
214 		val = readl(port->base + GPIO_EDGE_SEL);
215 		if (edge == GPIO_INT_BOTH_EDGES)
216 			writel(val | (1 << gpio_idx),
217 				port->base + GPIO_EDGE_SEL);
218 		else
219 			writel(val & ~(1 << gpio_idx),
220 				port->base + GPIO_EDGE_SEL);
221 	}
222 
223 	if (edge != GPIO_INT_BOTH_EDGES) {
224 		reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
225 		bit = gpio_idx & 0xf;
226 		val = readl(reg) & ~(0x3 << (bit << 1));
227 		writel(val | (edge << (bit << 1)), reg);
228 	}
229 
230 	writel(1 << gpio_idx, port->base + GPIO_ISR);
231 
232 	return 0;
233 }
234 
235 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
236 {
237 	void __iomem *reg = port->base;
238 	u32 bit, val;
239 	int edge;
240 
241 	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
242 	bit = gpio & 0xf;
243 	val = readl(reg);
244 	edge = (val >> (bit << 1)) & 3;
245 	val &= ~(0x3 << (bit << 1));
246 	if (edge == GPIO_INT_HIGH_LEV) {
247 		edge = GPIO_INT_LOW_LEV;
248 		pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
249 	} else if (edge == GPIO_INT_LOW_LEV) {
250 		edge = GPIO_INT_HIGH_LEV;
251 		pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
252 	} else {
253 		pr_err("mxc: invalid configuration for GPIO %d: %x\n",
254 		       gpio, edge);
255 		return;
256 	}
257 	writel(val | (edge << (bit << 1)), reg);
258 }
259 
260 /* handle 32 interrupts in one status register */
261 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
262 {
263 	while (irq_stat != 0) {
264 		int irqoffset = fls(irq_stat) - 1;
265 
266 		if (port->both_edges & (1 << irqoffset))
267 			mxc_flip_edge(port, irqoffset);
268 
269 		generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
270 
271 		irq_stat &= ~(1 << irqoffset);
272 	}
273 }
274 
275 /* MX1 and MX3 has one interrupt *per* gpio port */
276 static void mx3_gpio_irq_handler(struct irq_desc *desc)
277 {
278 	u32 irq_stat;
279 	struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
280 	struct irq_chip *chip = irq_desc_get_chip(desc);
281 
282 	chained_irq_enter(chip, desc);
283 
284 	irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
285 
286 	mxc_gpio_irq_handler(port, irq_stat);
287 
288 	chained_irq_exit(chip, desc);
289 }
290 
291 /* MX2 has one interrupt *for all* gpio ports */
292 static void mx2_gpio_irq_handler(struct irq_desc *desc)
293 {
294 	u32 irq_msk, irq_stat;
295 	struct mxc_gpio_port *port;
296 	struct irq_chip *chip = irq_desc_get_chip(desc);
297 
298 	chained_irq_enter(chip, desc);
299 
300 	/* walk through all interrupt status registers */
301 	list_for_each_entry(port, &mxc_gpio_ports, node) {
302 		irq_msk = readl(port->base + GPIO_IMR);
303 		if (!irq_msk)
304 			continue;
305 
306 		irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
307 		if (irq_stat)
308 			mxc_gpio_irq_handler(port, irq_stat);
309 	}
310 	chained_irq_exit(chip, desc);
311 }
312 
313 /*
314  * Set interrupt number "irq" in the GPIO as a wake-up source.
315  * While system is running, all registered GPIO interrupts need to have
316  * wake-up enabled. When system is suspended, only selected GPIO interrupts
317  * need to have wake-up enabled.
318  * @param  irq          interrupt source number
319  * @param  enable       enable as wake-up if equal to non-zero
320  * @return       This function returns 0 on success.
321  */
322 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
323 {
324 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
325 	struct mxc_gpio_port *port = gc->private;
326 	u32 gpio_idx = d->hwirq;
327 	int ret;
328 
329 	if (enable) {
330 		if (port->irq_high && (gpio_idx >= 16))
331 			ret = enable_irq_wake(port->irq_high);
332 		else
333 			ret = enable_irq_wake(port->irq);
334 	} else {
335 		if (port->irq_high && (gpio_idx >= 16))
336 			ret = disable_irq_wake(port->irq_high);
337 		else
338 			ret = disable_irq_wake(port->irq);
339 	}
340 
341 	return ret;
342 }
343 
344 static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
345 {
346 	struct irq_chip_generic *gc;
347 	struct irq_chip_type *ct;
348 	int rv;
349 
350 	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
351 					 port->base, handle_level_irq);
352 	if (!gc)
353 		return -ENOMEM;
354 	gc->private = port;
355 
356 	ct = gc->chip_types;
357 	ct->chip.irq_ack = irq_gc_ack_set_bit;
358 	ct->chip.irq_mask = irq_gc_mask_clr_bit;
359 	ct->chip.irq_unmask = irq_gc_mask_set_bit;
360 	ct->chip.irq_set_type = gpio_set_irq_type;
361 	ct->chip.irq_set_wake = gpio_set_wake_irq;
362 	ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
363 	ct->regs.ack = GPIO_ISR;
364 	ct->regs.mask = GPIO_IMR;
365 
366 	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
367 					 IRQ_GC_INIT_NESTED_LOCK,
368 					 IRQ_NOREQUEST, 0);
369 
370 	return rv;
371 }
372 
373 static void mxc_gpio_get_hw(struct platform_device *pdev)
374 {
375 	const struct of_device_id *of_id =
376 			of_match_device(mxc_gpio_dt_ids, &pdev->dev);
377 	enum mxc_gpio_hwtype hwtype;
378 
379 	if (of_id)
380 		pdev->id_entry = of_id->data;
381 	hwtype = pdev->id_entry->driver_data;
382 
383 	if (mxc_gpio_hwtype) {
384 		/*
385 		 * The driver works with a reasonable presupposition,
386 		 * that is all gpio ports must be the same type when
387 		 * running on one soc.
388 		 */
389 		BUG_ON(mxc_gpio_hwtype != hwtype);
390 		return;
391 	}
392 
393 	if (hwtype == IMX35_GPIO)
394 		mxc_gpio_hwdata = &imx35_gpio_hwdata;
395 	else if (hwtype == IMX31_GPIO)
396 		mxc_gpio_hwdata = &imx31_gpio_hwdata;
397 	else
398 		mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
399 
400 	mxc_gpio_hwtype = hwtype;
401 }
402 
403 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
404 {
405 	struct mxc_gpio_port *port = gpiochip_get_data(gc);
406 
407 	return irq_find_mapping(port->domain, offset);
408 }
409 
410 static int mxc_gpio_probe(struct platform_device *pdev)
411 {
412 	struct device_node *np = pdev->dev.of_node;
413 	struct mxc_gpio_port *port;
414 	int irq_count;
415 	int irq_base;
416 	int err;
417 
418 	mxc_gpio_get_hw(pdev);
419 
420 	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
421 	if (!port)
422 		return -ENOMEM;
423 
424 	port->dev = &pdev->dev;
425 
426 	port->base = devm_platform_ioremap_resource(pdev, 0);
427 	if (IS_ERR(port->base))
428 		return PTR_ERR(port->base);
429 
430 	irq_count = platform_irq_count(pdev);
431 	if (irq_count < 0)
432 		return irq_count;
433 
434 	if (irq_count > 1) {
435 		port->irq_high = platform_get_irq(pdev, 1);
436 		if (port->irq_high < 0)
437 			port->irq_high = 0;
438 	}
439 
440 	port->irq = platform_get_irq(pdev, 0);
441 	if (port->irq < 0)
442 		return port->irq;
443 
444 	/* the controller clock is optional */
445 	port->clk = devm_clk_get_optional(&pdev->dev, NULL);
446 	if (IS_ERR(port->clk))
447 		return PTR_ERR(port->clk);
448 
449 	err = clk_prepare_enable(port->clk);
450 	if (err) {
451 		dev_err(&pdev->dev, "Unable to enable clock.\n");
452 		return err;
453 	}
454 
455 	if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
456 		port->power_off = true;
457 
458 	/* disable the interrupt and clear the status */
459 	writel(0, port->base + GPIO_IMR);
460 	writel(~0, port->base + GPIO_ISR);
461 
462 	if (mxc_gpio_hwtype == IMX21_GPIO) {
463 		/*
464 		 * Setup one handler for all GPIO interrupts. Actually setting
465 		 * the handler is needed only once, but doing it for every port
466 		 * is more robust and easier.
467 		 */
468 		irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
469 	} else {
470 		/* setup one handler for each entry */
471 		irq_set_chained_handler_and_data(port->irq,
472 						 mx3_gpio_irq_handler, port);
473 		if (port->irq_high > 0)
474 			/* setup handler for GPIO 16 to 31 */
475 			irq_set_chained_handler_and_data(port->irq_high,
476 							 mx3_gpio_irq_handler,
477 							 port);
478 	}
479 
480 	err = bgpio_init(&port->gc, &pdev->dev, 4,
481 			 port->base + GPIO_PSR,
482 			 port->base + GPIO_DR, NULL,
483 			 port->base + GPIO_GDIR, NULL,
484 			 BGPIOF_READ_OUTPUT_REG_SET);
485 	if (err)
486 		goto out_bgio;
487 
488 	port->gc.request = gpiochip_generic_request;
489 	port->gc.free = gpiochip_generic_free;
490 	port->gc.to_irq = mxc_gpio_to_irq;
491 	port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
492 					     pdev->id * 32;
493 
494 	err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
495 	if (err)
496 		goto out_bgio;
497 
498 	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
499 	if (irq_base < 0) {
500 		err = irq_base;
501 		goto out_bgio;
502 	}
503 
504 	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
505 					     &irq_domain_simple_ops, NULL);
506 	if (!port->domain) {
507 		err = -ENODEV;
508 		goto out_bgio;
509 	}
510 
511 	/* gpio-mxc can be a generic irq chip */
512 	err = mxc_gpio_init_gc(port, irq_base);
513 	if (err < 0)
514 		goto out_irqdomain_remove;
515 
516 	list_add_tail(&port->node, &mxc_gpio_ports);
517 
518 	platform_set_drvdata(pdev, port);
519 
520 	return 0;
521 
522 out_irqdomain_remove:
523 	irq_domain_remove(port->domain);
524 out_bgio:
525 	clk_disable_unprepare(port->clk);
526 	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
527 	return err;
528 }
529 
530 static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
531 {
532 	if (!port->power_off)
533 		return;
534 
535 	port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
536 	port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
537 	port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
538 	port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
539 	port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
540 	port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
541 }
542 
543 static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
544 {
545 	if (!port->power_off)
546 		return;
547 
548 	writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
549 	writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
550 	writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
551 	writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
552 	writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
553 	writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
554 }
555 
556 static int mxc_gpio_syscore_suspend(void)
557 {
558 	struct mxc_gpio_port *port;
559 
560 	/* walk through all ports */
561 	list_for_each_entry(port, &mxc_gpio_ports, node) {
562 		mxc_gpio_save_regs(port);
563 		clk_disable_unprepare(port->clk);
564 	}
565 
566 	return 0;
567 }
568 
569 static void mxc_gpio_syscore_resume(void)
570 {
571 	struct mxc_gpio_port *port;
572 	int ret;
573 
574 	/* walk through all ports */
575 	list_for_each_entry(port, &mxc_gpio_ports, node) {
576 		ret = clk_prepare_enable(port->clk);
577 		if (ret) {
578 			pr_err("mxc: failed to enable gpio clock %d\n", ret);
579 			return;
580 		}
581 		mxc_gpio_restore_regs(port);
582 	}
583 }
584 
585 static struct syscore_ops mxc_gpio_syscore_ops = {
586 	.suspend = mxc_gpio_syscore_suspend,
587 	.resume = mxc_gpio_syscore_resume,
588 };
589 
590 static struct platform_driver mxc_gpio_driver = {
591 	.driver		= {
592 		.name	= "gpio-mxc",
593 		.of_match_table = mxc_gpio_dt_ids,
594 		.suppress_bind_attrs = true,
595 	},
596 	.probe		= mxc_gpio_probe,
597 	.id_table	= mxc_gpio_devtype,
598 };
599 
600 static int __init gpio_mxc_init(void)
601 {
602 	register_syscore_ops(&mxc_gpio_syscore_ops);
603 
604 	return platform_driver_register(&mxc_gpio_driver);
605 }
606 subsys_initcall(gpio_mxc_init);
607