1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 4 // Copyright 2008 Juergen Beisert, kernel@pengutronix.de 5 // 6 // Based on code from Freescale Semiconductor, 7 // Authors: Daniel Mack, Juergen Beisert. 8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9 10 #include <linux/clk.h> 11 #include <linux/err.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/spinlock.h> 22 #include <linux/syscore_ops.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/bug.h> 27 28 #define IMX_SCU_WAKEUP_OFF 0 29 #define IMX_SCU_WAKEUP_LOW_LVL 4 30 #define IMX_SCU_WAKEUP_FALL_EDGE 5 31 #define IMX_SCU_WAKEUP_RISE_EDGE 6 32 #define IMX_SCU_WAKEUP_HIGH_LVL 7 33 34 /* device type dependent stuff */ 35 struct mxc_gpio_hwdata { 36 unsigned dr_reg; 37 unsigned gdir_reg; 38 unsigned psr_reg; 39 unsigned icr1_reg; 40 unsigned icr2_reg; 41 unsigned imr_reg; 42 unsigned isr_reg; 43 int edge_sel_reg; 44 unsigned low_level; 45 unsigned high_level; 46 unsigned rise_edge; 47 unsigned fall_edge; 48 }; 49 50 struct mxc_gpio_reg_saved { 51 u32 icr1; 52 u32 icr2; 53 u32 imr; 54 u32 gdir; 55 u32 edge_sel; 56 u32 dr; 57 }; 58 59 struct mxc_gpio_port { 60 struct list_head node; 61 void __iomem *base; 62 struct clk *clk; 63 int irq; 64 int irq_high; 65 struct irq_domain *domain; 66 struct gpio_chip gc; 67 struct device *dev; 68 u32 both_edges; 69 struct mxc_gpio_reg_saved gpio_saved_reg; 70 bool power_off; 71 u32 wakeup_pads; 72 bool is_pad_wakeup; 73 u32 pad_type[32]; 74 const struct mxc_gpio_hwdata *hwdata; 75 }; 76 77 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 78 .dr_reg = 0x1c, 79 .gdir_reg = 0x00, 80 .psr_reg = 0x24, 81 .icr1_reg = 0x28, 82 .icr2_reg = 0x2c, 83 .imr_reg = 0x30, 84 .isr_reg = 0x34, 85 .edge_sel_reg = -EINVAL, 86 .low_level = 0x03, 87 .high_level = 0x02, 88 .rise_edge = 0x00, 89 .fall_edge = 0x01, 90 }; 91 92 static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 93 .dr_reg = 0x00, 94 .gdir_reg = 0x04, 95 .psr_reg = 0x08, 96 .icr1_reg = 0x0c, 97 .icr2_reg = 0x10, 98 .imr_reg = 0x14, 99 .isr_reg = 0x18, 100 .edge_sel_reg = -EINVAL, 101 .low_level = 0x00, 102 .high_level = 0x01, 103 .rise_edge = 0x02, 104 .fall_edge = 0x03, 105 }; 106 107 static struct mxc_gpio_hwdata imx35_gpio_hwdata = { 108 .dr_reg = 0x00, 109 .gdir_reg = 0x04, 110 .psr_reg = 0x08, 111 .icr1_reg = 0x0c, 112 .icr2_reg = 0x10, 113 .imr_reg = 0x14, 114 .isr_reg = 0x18, 115 .edge_sel_reg = 0x1c, 116 .low_level = 0x00, 117 .high_level = 0x01, 118 .rise_edge = 0x02, 119 .fall_edge = 0x03, 120 }; 121 122 #define GPIO_DR (port->hwdata->dr_reg) 123 #define GPIO_GDIR (port->hwdata->gdir_reg) 124 #define GPIO_PSR (port->hwdata->psr_reg) 125 #define GPIO_ICR1 (port->hwdata->icr1_reg) 126 #define GPIO_ICR2 (port->hwdata->icr2_reg) 127 #define GPIO_IMR (port->hwdata->imr_reg) 128 #define GPIO_ISR (port->hwdata->isr_reg) 129 #define GPIO_EDGE_SEL (port->hwdata->edge_sel_reg) 130 131 #define GPIO_INT_LOW_LEV (port->hwdata->low_level) 132 #define GPIO_INT_HIGH_LEV (port->hwdata->high_level) 133 #define GPIO_INT_RISE_EDGE (port->hwdata->rise_edge) 134 #define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge) 135 #define GPIO_INT_BOTH_EDGES 0x4 136 137 static const struct of_device_id mxc_gpio_dt_ids[] = { 138 { .compatible = "fsl,imx1-gpio", .data = &imx1_imx21_gpio_hwdata }, 139 { .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata }, 140 { .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata }, 141 { .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata }, 142 { .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata }, 143 { .compatible = "fsl,imx8dxl-gpio", .data = &imx35_gpio_hwdata }, 144 { .compatible = "fsl,imx8qm-gpio", .data = &imx35_gpio_hwdata }, 145 { .compatible = "fsl,imx8qxp-gpio", .data = &imx35_gpio_hwdata }, 146 { /* sentinel */ } 147 }; 148 MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids); 149 150 /* 151 * MX2 has one interrupt *for all* gpio ports. The list is used 152 * to save the references to all ports, so that mx2_gpio_irq_handler 153 * can walk through all interrupt status registers. 154 */ 155 static LIST_HEAD(mxc_gpio_ports); 156 157 /* Note: This driver assumes 32 GPIOs are handled in one register */ 158 159 static int gpio_set_irq_type(struct irq_data *d, u32 type) 160 { 161 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 162 struct mxc_gpio_port *port = gc->private; 163 unsigned long flags; 164 u32 bit, val; 165 u32 gpio_idx = d->hwirq; 166 int edge; 167 void __iomem *reg = port->base; 168 169 port->both_edges &= ~(1 << gpio_idx); 170 switch (type) { 171 case IRQ_TYPE_EDGE_RISING: 172 edge = GPIO_INT_RISE_EDGE; 173 break; 174 case IRQ_TYPE_EDGE_FALLING: 175 edge = GPIO_INT_FALL_EDGE; 176 break; 177 case IRQ_TYPE_EDGE_BOTH: 178 if (GPIO_EDGE_SEL >= 0) { 179 edge = GPIO_INT_BOTH_EDGES; 180 } else { 181 val = port->gc.get(&port->gc, gpio_idx); 182 if (val) { 183 edge = GPIO_INT_LOW_LEV; 184 pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx); 185 } else { 186 edge = GPIO_INT_HIGH_LEV; 187 pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx); 188 } 189 port->both_edges |= 1 << gpio_idx; 190 } 191 break; 192 case IRQ_TYPE_LEVEL_LOW: 193 edge = GPIO_INT_LOW_LEV; 194 break; 195 case IRQ_TYPE_LEVEL_HIGH: 196 edge = GPIO_INT_HIGH_LEV; 197 break; 198 default: 199 return -EINVAL; 200 } 201 202 raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags); 203 204 if (GPIO_EDGE_SEL >= 0) { 205 val = readl(port->base + GPIO_EDGE_SEL); 206 if (edge == GPIO_INT_BOTH_EDGES) 207 writel(val | (1 << gpio_idx), 208 port->base + GPIO_EDGE_SEL); 209 else 210 writel(val & ~(1 << gpio_idx), 211 port->base + GPIO_EDGE_SEL); 212 } 213 214 if (edge != GPIO_INT_BOTH_EDGES) { 215 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ 216 bit = gpio_idx & 0xf; 217 val = readl(reg) & ~(0x3 << (bit << 1)); 218 writel(val | (edge << (bit << 1)), reg); 219 } 220 221 writel(1 << gpio_idx, port->base + GPIO_ISR); 222 port->pad_type[gpio_idx] = type; 223 224 raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); 225 226 return port->gc.direction_input(&port->gc, gpio_idx); 227 } 228 229 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 230 { 231 void __iomem *reg = port->base; 232 unsigned long flags; 233 u32 bit, val; 234 int edge; 235 236 raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags); 237 238 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 239 bit = gpio & 0xf; 240 val = readl(reg); 241 edge = (val >> (bit << 1)) & 3; 242 val &= ~(0x3 << (bit << 1)); 243 if (edge == GPIO_INT_HIGH_LEV) { 244 edge = GPIO_INT_LOW_LEV; 245 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 246 } else if (edge == GPIO_INT_LOW_LEV) { 247 edge = GPIO_INT_HIGH_LEV; 248 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 249 } else { 250 pr_err("mxc: invalid configuration for GPIO %d: %x\n", 251 gpio, edge); 252 goto unlock; 253 } 254 writel(val | (edge << (bit << 1)), reg); 255 256 unlock: 257 raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); 258 } 259 260 /* handle 32 interrupts in one status register */ 261 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 262 { 263 while (irq_stat != 0) { 264 int irqoffset = fls(irq_stat) - 1; 265 266 if (port->both_edges & (1 << irqoffset)) 267 mxc_flip_edge(port, irqoffset); 268 269 generic_handle_domain_irq(port->domain, irqoffset); 270 271 irq_stat &= ~(1 << irqoffset); 272 } 273 } 274 275 /* MX1 and MX3 has one interrupt *per* gpio port */ 276 static void mx3_gpio_irq_handler(struct irq_desc *desc) 277 { 278 u32 irq_stat; 279 struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); 280 struct irq_chip *chip = irq_desc_get_chip(desc); 281 282 if (port->is_pad_wakeup) 283 return; 284 285 chained_irq_enter(chip, desc); 286 287 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 288 289 mxc_gpio_irq_handler(port, irq_stat); 290 291 chained_irq_exit(chip, desc); 292 } 293 294 /* MX2 has one interrupt *for all* gpio ports */ 295 static void mx2_gpio_irq_handler(struct irq_desc *desc) 296 { 297 u32 irq_msk, irq_stat; 298 struct mxc_gpio_port *port; 299 struct irq_chip *chip = irq_desc_get_chip(desc); 300 301 chained_irq_enter(chip, desc); 302 303 /* walk through all interrupt status registers */ 304 list_for_each_entry(port, &mxc_gpio_ports, node) { 305 irq_msk = readl(port->base + GPIO_IMR); 306 if (!irq_msk) 307 continue; 308 309 irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 310 if (irq_stat) 311 mxc_gpio_irq_handler(port, irq_stat); 312 } 313 chained_irq_exit(chip, desc); 314 } 315 316 /* 317 * Set interrupt number "irq" in the GPIO as a wake-up source. 318 * While system is running, all registered GPIO interrupts need to have 319 * wake-up enabled. When system is suspended, only selected GPIO interrupts 320 * need to have wake-up enabled. 321 * @param irq interrupt source number 322 * @param enable enable as wake-up if equal to non-zero 323 * @return This function returns 0 on success. 324 */ 325 static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 326 { 327 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 328 struct mxc_gpio_port *port = gc->private; 329 u32 gpio_idx = d->hwirq; 330 int ret; 331 332 if (enable) { 333 if (port->irq_high && (gpio_idx >= 16)) 334 ret = enable_irq_wake(port->irq_high); 335 else 336 ret = enable_irq_wake(port->irq); 337 port->wakeup_pads |= (1 << gpio_idx); 338 } else { 339 if (port->irq_high && (gpio_idx >= 16)) 340 ret = disable_irq_wake(port->irq_high); 341 else 342 ret = disable_irq_wake(port->irq); 343 port->wakeup_pads &= ~(1 << gpio_idx); 344 } 345 346 return ret; 347 } 348 349 static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) 350 { 351 struct irq_chip_generic *gc; 352 struct irq_chip_type *ct; 353 int rv; 354 355 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base, 356 port->base, handle_level_irq); 357 if (!gc) 358 return -ENOMEM; 359 gc->private = port; 360 361 ct = gc->chip_types; 362 ct->chip.irq_ack = irq_gc_ack_set_bit; 363 ct->chip.irq_mask = irq_gc_mask_clr_bit; 364 ct->chip.irq_unmask = irq_gc_mask_set_bit; 365 ct->chip.irq_set_type = gpio_set_irq_type; 366 ct->chip.irq_set_wake = gpio_set_wake_irq; 367 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND; 368 ct->regs.ack = GPIO_ISR; 369 ct->regs.mask = GPIO_IMR; 370 371 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), 372 IRQ_GC_INIT_NESTED_LOCK, 373 IRQ_NOREQUEST, 0); 374 375 return rv; 376 } 377 378 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 379 { 380 struct mxc_gpio_port *port = gpiochip_get_data(gc); 381 382 return irq_find_mapping(port->domain, offset); 383 } 384 385 static int mxc_gpio_probe(struct platform_device *pdev) 386 { 387 struct device_node *np = pdev->dev.of_node; 388 struct mxc_gpio_port *port; 389 int irq_count; 390 int irq_base; 391 int err; 392 393 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 394 if (!port) 395 return -ENOMEM; 396 397 port->dev = &pdev->dev; 398 port->hwdata = device_get_match_data(&pdev->dev); 399 400 port->base = devm_platform_ioremap_resource(pdev, 0); 401 if (IS_ERR(port->base)) 402 return PTR_ERR(port->base); 403 404 irq_count = platform_irq_count(pdev); 405 if (irq_count < 0) 406 return irq_count; 407 408 if (irq_count > 1) { 409 port->irq_high = platform_get_irq(pdev, 1); 410 if (port->irq_high < 0) 411 port->irq_high = 0; 412 } 413 414 port->irq = platform_get_irq(pdev, 0); 415 if (port->irq < 0) 416 return port->irq; 417 418 /* the controller clock is optional */ 419 port->clk = devm_clk_get_optional(&pdev->dev, NULL); 420 if (IS_ERR(port->clk)) 421 return PTR_ERR(port->clk); 422 423 err = clk_prepare_enable(port->clk); 424 if (err) { 425 dev_err(&pdev->dev, "Unable to enable clock.\n"); 426 return err; 427 } 428 429 if (of_device_is_compatible(np, "fsl,imx7d-gpio")) 430 port->power_off = true; 431 432 /* disable the interrupt and clear the status */ 433 writel(0, port->base + GPIO_IMR); 434 writel(~0, port->base + GPIO_ISR); 435 436 if (of_device_is_compatible(np, "fsl,imx21-gpio")) { 437 /* 438 * Setup one handler for all GPIO interrupts. Actually setting 439 * the handler is needed only once, but doing it for every port 440 * is more robust and easier. 441 */ 442 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); 443 } else { 444 /* setup one handler for each entry */ 445 irq_set_chained_handler_and_data(port->irq, 446 mx3_gpio_irq_handler, port); 447 if (port->irq_high > 0) 448 /* setup handler for GPIO 16 to 31 */ 449 irq_set_chained_handler_and_data(port->irq_high, 450 mx3_gpio_irq_handler, 451 port); 452 } 453 454 err = bgpio_init(&port->gc, &pdev->dev, 4, 455 port->base + GPIO_PSR, 456 port->base + GPIO_DR, NULL, 457 port->base + GPIO_GDIR, NULL, 458 BGPIOF_READ_OUTPUT_REG_SET); 459 if (err) 460 goto out_bgio; 461 462 port->gc.request = gpiochip_generic_request; 463 port->gc.free = gpiochip_generic_free; 464 port->gc.to_irq = mxc_gpio_to_irq; 465 port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : 466 pdev->id * 32; 467 468 err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port); 469 if (err) 470 goto out_bgio; 471 472 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); 473 if (irq_base < 0) { 474 err = irq_base; 475 goto out_bgio; 476 } 477 478 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, 479 &irq_domain_simple_ops, NULL); 480 if (!port->domain) { 481 err = -ENODEV; 482 goto out_bgio; 483 } 484 485 /* gpio-mxc can be a generic irq chip */ 486 err = mxc_gpio_init_gc(port, irq_base); 487 if (err < 0) 488 goto out_irqdomain_remove; 489 490 list_add_tail(&port->node, &mxc_gpio_ports); 491 492 platform_set_drvdata(pdev, port); 493 494 return 0; 495 496 out_irqdomain_remove: 497 irq_domain_remove(port->domain); 498 out_bgio: 499 clk_disable_unprepare(port->clk); 500 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 501 return err; 502 } 503 504 static void mxc_gpio_save_regs(struct mxc_gpio_port *port) 505 { 506 if (!port->power_off) 507 return; 508 509 port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1); 510 port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2); 511 port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR); 512 port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR); 513 port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL); 514 port->gpio_saved_reg.dr = readl(port->base + GPIO_DR); 515 } 516 517 static void mxc_gpio_restore_regs(struct mxc_gpio_port *port) 518 { 519 if (!port->power_off) 520 return; 521 522 writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1); 523 writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2); 524 writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR); 525 writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR); 526 writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL); 527 writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); 528 } 529 530 static bool mxc_gpio_generic_config(struct mxc_gpio_port *port, 531 unsigned int offset, unsigned long conf) 532 { 533 struct device_node *np = port->dev->of_node; 534 535 if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") || 536 of_device_is_compatible(np, "fsl,imx8qxp-gpio") || 537 of_device_is_compatible(np, "fsl,imx8qm-gpio")) 538 return (gpiochip_generic_config(&port->gc, offset, conf) == 0); 539 540 return false; 541 } 542 543 static bool mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable) 544 { 545 unsigned long config; 546 bool ret = false; 547 int i, type; 548 549 static const u32 pad_type_map[] = { 550 IMX_SCU_WAKEUP_OFF, /* 0 */ 551 IMX_SCU_WAKEUP_RISE_EDGE, /* IRQ_TYPE_EDGE_RISING */ 552 IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_FALLING */ 553 IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_BOTH */ 554 IMX_SCU_WAKEUP_HIGH_LVL, /* IRQ_TYPE_LEVEL_HIGH */ 555 IMX_SCU_WAKEUP_OFF, /* 5 */ 556 IMX_SCU_WAKEUP_OFF, /* 6 */ 557 IMX_SCU_WAKEUP_OFF, /* 7 */ 558 IMX_SCU_WAKEUP_LOW_LVL, /* IRQ_TYPE_LEVEL_LOW */ 559 }; 560 561 for (i = 0; i < 32; i++) { 562 if ((port->wakeup_pads & (1 << i))) { 563 type = port->pad_type[i]; 564 if (enable) 565 config = pad_type_map[type]; 566 else 567 config = IMX_SCU_WAKEUP_OFF; 568 ret |= mxc_gpio_generic_config(port, i, config); 569 } 570 } 571 572 return ret; 573 } 574 575 static int __maybe_unused mxc_gpio_noirq_suspend(struct device *dev) 576 { 577 struct platform_device *pdev = to_platform_device(dev); 578 struct mxc_gpio_port *port = platform_get_drvdata(pdev); 579 580 if (port->wakeup_pads > 0) 581 port->is_pad_wakeup = mxc_gpio_set_pad_wakeup(port, true); 582 583 return 0; 584 } 585 586 static int __maybe_unused mxc_gpio_noirq_resume(struct device *dev) 587 { 588 struct platform_device *pdev = to_platform_device(dev); 589 struct mxc_gpio_port *port = platform_get_drvdata(pdev); 590 591 if (port->wakeup_pads > 0) 592 mxc_gpio_set_pad_wakeup(port, false); 593 port->is_pad_wakeup = false; 594 595 return 0; 596 } 597 598 static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { 599 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume) 600 }; 601 602 static int mxc_gpio_syscore_suspend(void) 603 { 604 struct mxc_gpio_port *port; 605 606 /* walk through all ports */ 607 list_for_each_entry(port, &mxc_gpio_ports, node) { 608 mxc_gpio_save_regs(port); 609 clk_disable_unprepare(port->clk); 610 } 611 612 return 0; 613 } 614 615 static void mxc_gpio_syscore_resume(void) 616 { 617 struct mxc_gpio_port *port; 618 int ret; 619 620 /* walk through all ports */ 621 list_for_each_entry(port, &mxc_gpio_ports, node) { 622 ret = clk_prepare_enable(port->clk); 623 if (ret) { 624 pr_err("mxc: failed to enable gpio clock %d\n", ret); 625 return; 626 } 627 mxc_gpio_restore_regs(port); 628 } 629 } 630 631 static struct syscore_ops mxc_gpio_syscore_ops = { 632 .suspend = mxc_gpio_syscore_suspend, 633 .resume = mxc_gpio_syscore_resume, 634 }; 635 636 static struct platform_driver mxc_gpio_driver = { 637 .driver = { 638 .name = "gpio-mxc", 639 .of_match_table = mxc_gpio_dt_ids, 640 .suppress_bind_attrs = true, 641 .pm = &mxc_gpio_dev_pm_ops, 642 }, 643 .probe = mxc_gpio_probe, 644 }; 645 646 static int __init gpio_mxc_init(void) 647 { 648 register_syscore_ops(&mxc_gpio_syscore_ops); 649 650 return platform_driver_register(&mxc_gpio_driver); 651 } 652 subsys_initcall(gpio_mxc_init); 653 654 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 655 MODULE_DESCRIPTION("i.MX GPIO Driver"); 656 MODULE_LICENSE("GPL"); 657