1d37a65bbSShawn Guo /* 2d37a65bbSShawn Guo * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 3d37a65bbSShawn Guo * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 4d37a65bbSShawn Guo * 5d37a65bbSShawn Guo * Based on code from Freescale, 6d37a65bbSShawn Guo * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 7d37a65bbSShawn Guo * 8d37a65bbSShawn Guo * This program is free software; you can redistribute it and/or 9d37a65bbSShawn Guo * modify it under the terms of the GNU General Public License 10d37a65bbSShawn Guo * as published by the Free Software Foundation; either version 2 11d37a65bbSShawn Guo * of the License, or (at your option) any later version. 12d37a65bbSShawn Guo * This program is distributed in the hope that it will be useful, 13d37a65bbSShawn Guo * but WITHOUT ANY WARRANTY; without even the implied warranty of 14d37a65bbSShawn Guo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15d37a65bbSShawn Guo * GNU General Public License for more details. 16d37a65bbSShawn Guo * 17d37a65bbSShawn Guo * You should have received a copy of the GNU General Public License 18d37a65bbSShawn Guo * along with this program; if not, write to the Free Software 19d37a65bbSShawn Guo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 20d37a65bbSShawn Guo */ 21d37a65bbSShawn Guo 22d37a65bbSShawn Guo #include <linux/init.h> 23d37a65bbSShawn Guo #include <linux/interrupt.h> 24d37a65bbSShawn Guo #include <linux/io.h> 25d37a65bbSShawn Guo #include <linux/irq.h> 261ab7ef15SShawn Guo #include <linux/irqdomain.h> 27d37a65bbSShawn Guo #include <linux/gpio.h> 28b78d8e59SShawn Guo #include <linux/platform_device.h> 29b78d8e59SShawn Guo #include <linux/slab.h> 302ce420daSShawn Guo #include <linux/basic_mmio_gpio.h> 318937cb60SShawn Guo #include <linux/of.h> 328937cb60SShawn Guo #include <linux/of_device.h> 33bb207ef1SPaul Gortmaker #include <linux/module.h> 34d37a65bbSShawn Guo #include <asm-generic/bug.h> 350e44b6ecSShawn Guo #include <asm/mach/irq.h> 36d37a65bbSShawn Guo 37e7fc6ae7SShawn Guo enum mxc_gpio_hwtype { 38e7fc6ae7SShawn Guo IMX1_GPIO, /* runs on i.mx1 */ 39e7fc6ae7SShawn Guo IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ 40aeb27748SBenoît Thébaudeau IMX31_GPIO, /* runs on i.mx31 */ 41aeb27748SBenoît Thébaudeau IMX35_GPIO, /* runs on all other i.mx */ 42e7fc6ae7SShawn Guo }; 43e7fc6ae7SShawn Guo 44e7fc6ae7SShawn Guo /* device type dependent stuff */ 45e7fc6ae7SShawn Guo struct mxc_gpio_hwdata { 46e7fc6ae7SShawn Guo unsigned dr_reg; 47e7fc6ae7SShawn Guo unsigned gdir_reg; 48e7fc6ae7SShawn Guo unsigned psr_reg; 49e7fc6ae7SShawn Guo unsigned icr1_reg; 50e7fc6ae7SShawn Guo unsigned icr2_reg; 51e7fc6ae7SShawn Guo unsigned imr_reg; 52e7fc6ae7SShawn Guo unsigned isr_reg; 53aeb27748SBenoît Thébaudeau int edge_sel_reg; 54e7fc6ae7SShawn Guo unsigned low_level; 55e7fc6ae7SShawn Guo unsigned high_level; 56e7fc6ae7SShawn Guo unsigned rise_edge; 57e7fc6ae7SShawn Guo unsigned fall_edge; 58e7fc6ae7SShawn Guo }; 59e7fc6ae7SShawn Guo 60b78d8e59SShawn Guo struct mxc_gpio_port { 61b78d8e59SShawn Guo struct list_head node; 62b78d8e59SShawn Guo void __iomem *base; 63b78d8e59SShawn Guo int irq; 64b78d8e59SShawn Guo int irq_high; 651ab7ef15SShawn Guo struct irq_domain *domain; 662ce420daSShawn Guo struct bgpio_chip bgc; 67b78d8e59SShawn Guo u32 both_edges; 68b78d8e59SShawn Guo }; 69b78d8e59SShawn Guo 70e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 71e7fc6ae7SShawn Guo .dr_reg = 0x1c, 72e7fc6ae7SShawn Guo .gdir_reg = 0x00, 73e7fc6ae7SShawn Guo .psr_reg = 0x24, 74e7fc6ae7SShawn Guo .icr1_reg = 0x28, 75e7fc6ae7SShawn Guo .icr2_reg = 0x2c, 76e7fc6ae7SShawn Guo .imr_reg = 0x30, 77e7fc6ae7SShawn Guo .isr_reg = 0x34, 78aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 79e7fc6ae7SShawn Guo .low_level = 0x03, 80e7fc6ae7SShawn Guo .high_level = 0x02, 81e7fc6ae7SShawn Guo .rise_edge = 0x00, 82e7fc6ae7SShawn Guo .fall_edge = 0x01, 83e7fc6ae7SShawn Guo }; 84e7fc6ae7SShawn Guo 85e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 86e7fc6ae7SShawn Guo .dr_reg = 0x00, 87e7fc6ae7SShawn Guo .gdir_reg = 0x04, 88e7fc6ae7SShawn Guo .psr_reg = 0x08, 89e7fc6ae7SShawn Guo .icr1_reg = 0x0c, 90e7fc6ae7SShawn Guo .icr2_reg = 0x10, 91e7fc6ae7SShawn Guo .imr_reg = 0x14, 92e7fc6ae7SShawn Guo .isr_reg = 0x18, 93aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 94aeb27748SBenoît Thébaudeau .low_level = 0x00, 95aeb27748SBenoît Thébaudeau .high_level = 0x01, 96aeb27748SBenoît Thébaudeau .rise_edge = 0x02, 97aeb27748SBenoît Thébaudeau .fall_edge = 0x03, 98aeb27748SBenoît Thébaudeau }; 99aeb27748SBenoît Thébaudeau 100aeb27748SBenoît Thébaudeau static struct mxc_gpio_hwdata imx35_gpio_hwdata = { 101aeb27748SBenoît Thébaudeau .dr_reg = 0x00, 102aeb27748SBenoît Thébaudeau .gdir_reg = 0x04, 103aeb27748SBenoît Thébaudeau .psr_reg = 0x08, 104aeb27748SBenoît Thébaudeau .icr1_reg = 0x0c, 105aeb27748SBenoît Thébaudeau .icr2_reg = 0x10, 106aeb27748SBenoît Thébaudeau .imr_reg = 0x14, 107aeb27748SBenoît Thébaudeau .isr_reg = 0x18, 108aeb27748SBenoît Thébaudeau .edge_sel_reg = 0x1c, 109e7fc6ae7SShawn Guo .low_level = 0x00, 110e7fc6ae7SShawn Guo .high_level = 0x01, 111e7fc6ae7SShawn Guo .rise_edge = 0x02, 112e7fc6ae7SShawn Guo .fall_edge = 0x03, 113e7fc6ae7SShawn Guo }; 114e7fc6ae7SShawn Guo 115e7fc6ae7SShawn Guo static enum mxc_gpio_hwtype mxc_gpio_hwtype; 116e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata *mxc_gpio_hwdata; 117e7fc6ae7SShawn Guo 118e7fc6ae7SShawn Guo #define GPIO_DR (mxc_gpio_hwdata->dr_reg) 119e7fc6ae7SShawn Guo #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg) 120e7fc6ae7SShawn Guo #define GPIO_PSR (mxc_gpio_hwdata->psr_reg) 121e7fc6ae7SShawn Guo #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg) 122e7fc6ae7SShawn Guo #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg) 123e7fc6ae7SShawn Guo #define GPIO_IMR (mxc_gpio_hwdata->imr_reg) 124e7fc6ae7SShawn Guo #define GPIO_ISR (mxc_gpio_hwdata->isr_reg) 125aeb27748SBenoît Thébaudeau #define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg) 126e7fc6ae7SShawn Guo 127e7fc6ae7SShawn Guo #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level) 128e7fc6ae7SShawn Guo #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level) 129e7fc6ae7SShawn Guo #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge) 130e7fc6ae7SShawn Guo #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge) 131aeb27748SBenoît Thébaudeau #define GPIO_INT_BOTH_EDGES 0x4 132e7fc6ae7SShawn Guo 133e7fc6ae7SShawn Guo static struct platform_device_id mxc_gpio_devtype[] = { 134e7fc6ae7SShawn Guo { 135e7fc6ae7SShawn Guo .name = "imx1-gpio", 136e7fc6ae7SShawn Guo .driver_data = IMX1_GPIO, 137e7fc6ae7SShawn Guo }, { 138e7fc6ae7SShawn Guo .name = "imx21-gpio", 139e7fc6ae7SShawn Guo .driver_data = IMX21_GPIO, 140e7fc6ae7SShawn Guo }, { 141e7fc6ae7SShawn Guo .name = "imx31-gpio", 142e7fc6ae7SShawn Guo .driver_data = IMX31_GPIO, 143e7fc6ae7SShawn Guo }, { 144aeb27748SBenoît Thébaudeau .name = "imx35-gpio", 145aeb27748SBenoît Thébaudeau .driver_data = IMX35_GPIO, 146aeb27748SBenoît Thébaudeau }, { 147e7fc6ae7SShawn Guo /* sentinel */ 148e7fc6ae7SShawn Guo } 149e7fc6ae7SShawn Guo }; 150e7fc6ae7SShawn Guo 1518937cb60SShawn Guo static const struct of_device_id mxc_gpio_dt_ids[] = { 1528937cb60SShawn Guo { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], }, 1538937cb60SShawn Guo { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], }, 1548937cb60SShawn Guo { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], }, 155aeb27748SBenoît Thébaudeau { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], }, 1568937cb60SShawn Guo { /* sentinel */ } 1578937cb60SShawn Guo }; 1588937cb60SShawn Guo 159b78d8e59SShawn Guo /* 160b78d8e59SShawn Guo * MX2 has one interrupt *for all* gpio ports. The list is used 161b78d8e59SShawn Guo * to save the references to all ports, so that mx2_gpio_irq_handler 162b78d8e59SShawn Guo * can walk through all interrupt status registers. 163b78d8e59SShawn Guo */ 164b78d8e59SShawn Guo static LIST_HEAD(mxc_gpio_ports); 165d37a65bbSShawn Guo 166d37a65bbSShawn Guo /* Note: This driver assumes 32 GPIOs are handled in one register */ 167d37a65bbSShawn Guo 168d37a65bbSShawn Guo static int gpio_set_irq_type(struct irq_data *d, u32 type) 169d37a65bbSShawn Guo { 170e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 171e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 172d37a65bbSShawn Guo u32 bit, val; 1731ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 1741ab7ef15SShawn Guo u32 gpio = port->bgc.gc.base + gpio_idx; 175d37a65bbSShawn Guo int edge; 176d37a65bbSShawn Guo void __iomem *reg = port->base; 177d37a65bbSShawn Guo 1781ab7ef15SShawn Guo port->both_edges &= ~(1 << gpio_idx); 179d37a65bbSShawn Guo switch (type) { 180d37a65bbSShawn Guo case IRQ_TYPE_EDGE_RISING: 181d37a65bbSShawn Guo edge = GPIO_INT_RISE_EDGE; 182d37a65bbSShawn Guo break; 183d37a65bbSShawn Guo case IRQ_TYPE_EDGE_FALLING: 184d37a65bbSShawn Guo edge = GPIO_INT_FALL_EDGE; 185d37a65bbSShawn Guo break; 186d37a65bbSShawn Guo case IRQ_TYPE_EDGE_BOTH: 187aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 188aeb27748SBenoît Thébaudeau edge = GPIO_INT_BOTH_EDGES; 189aeb27748SBenoît Thébaudeau } else { 1905523f86bSShawn Guo val = gpio_get_value(gpio); 191d37a65bbSShawn Guo if (val) { 192d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 193d37a65bbSShawn Guo pr_debug("mxc: set GPIO %d to low trigger\n", gpio); 194d37a65bbSShawn Guo } else { 195d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 196d37a65bbSShawn Guo pr_debug("mxc: set GPIO %d to high trigger\n", gpio); 197d37a65bbSShawn Guo } 1981ab7ef15SShawn Guo port->both_edges |= 1 << gpio_idx; 199aeb27748SBenoît Thébaudeau } 200d37a65bbSShawn Guo break; 201d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_LOW: 202d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 203d37a65bbSShawn Guo break; 204d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_HIGH: 205d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 206d37a65bbSShawn Guo break; 207d37a65bbSShawn Guo default: 208d37a65bbSShawn Guo return -EINVAL; 209d37a65bbSShawn Guo } 210d37a65bbSShawn Guo 211aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 212aeb27748SBenoît Thébaudeau val = readl(port->base + GPIO_EDGE_SEL); 213aeb27748SBenoît Thébaudeau if (edge == GPIO_INT_BOTH_EDGES) 214f948ad07SLinus Torvalds writel(val | (1 << gpio_idx), 215aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 216aeb27748SBenoît Thébaudeau else 217f948ad07SLinus Torvalds writel(val & ~(1 << gpio_idx), 218aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 219aeb27748SBenoît Thébaudeau } 220aeb27748SBenoît Thébaudeau 221aeb27748SBenoît Thébaudeau if (edge != GPIO_INT_BOTH_EDGES) { 222f948ad07SLinus Torvalds reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ 2231ab7ef15SShawn Guo bit = gpio_idx & 0xf; 224b78d8e59SShawn Guo val = readl(reg) & ~(0x3 << (bit << 1)); 225b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 226aeb27748SBenoît Thébaudeau } 227aeb27748SBenoît Thébaudeau 2281ab7ef15SShawn Guo writel(1 << gpio_idx, port->base + GPIO_ISR); 229d37a65bbSShawn Guo 230d37a65bbSShawn Guo return 0; 231d37a65bbSShawn Guo } 232d37a65bbSShawn Guo 233d37a65bbSShawn Guo static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 234d37a65bbSShawn Guo { 235d37a65bbSShawn Guo void __iomem *reg = port->base; 236d37a65bbSShawn Guo u32 bit, val; 237d37a65bbSShawn Guo int edge; 238d37a65bbSShawn Guo 239d37a65bbSShawn Guo reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 240d37a65bbSShawn Guo bit = gpio & 0xf; 241b78d8e59SShawn Guo val = readl(reg); 242d37a65bbSShawn Guo edge = (val >> (bit << 1)) & 3; 243d37a65bbSShawn Guo val &= ~(0x3 << (bit << 1)); 244d37a65bbSShawn Guo if (edge == GPIO_INT_HIGH_LEV) { 245d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 246d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 247d37a65bbSShawn Guo } else if (edge == GPIO_INT_LOW_LEV) { 248d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 249d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 250d37a65bbSShawn Guo } else { 251d37a65bbSShawn Guo pr_err("mxc: invalid configuration for GPIO %d: %x\n", 252d37a65bbSShawn Guo gpio, edge); 253d37a65bbSShawn Guo return; 254d37a65bbSShawn Guo } 255b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 256d37a65bbSShawn Guo } 257d37a65bbSShawn Guo 258d37a65bbSShawn Guo /* handle 32 interrupts in one status register */ 259d37a65bbSShawn Guo static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 260d37a65bbSShawn Guo { 261d37a65bbSShawn Guo while (irq_stat != 0) { 262d37a65bbSShawn Guo int irqoffset = fls(irq_stat) - 1; 263d37a65bbSShawn Guo 264d37a65bbSShawn Guo if (port->both_edges & (1 << irqoffset)) 265d37a65bbSShawn Guo mxc_flip_edge(port, irqoffset); 266d37a65bbSShawn Guo 2671ab7ef15SShawn Guo generic_handle_irq(irq_find_mapping(port->domain, irqoffset)); 268d37a65bbSShawn Guo 269d37a65bbSShawn Guo irq_stat &= ~(1 << irqoffset); 270d37a65bbSShawn Guo } 271d37a65bbSShawn Guo } 272d37a65bbSShawn Guo 273d37a65bbSShawn Guo /* MX1 and MX3 has one interrupt *per* gpio port */ 274d37a65bbSShawn Guo static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) 275d37a65bbSShawn Guo { 276d37a65bbSShawn Guo u32 irq_stat; 277d37a65bbSShawn Guo struct mxc_gpio_port *port = irq_get_handler_data(irq); 2780e44b6ecSShawn Guo struct irq_chip *chip = irq_get_chip(irq); 2790e44b6ecSShawn Guo 2800e44b6ecSShawn Guo chained_irq_enter(chip, desc); 281d37a65bbSShawn Guo 282b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 283d37a65bbSShawn Guo 284d37a65bbSShawn Guo mxc_gpio_irq_handler(port, irq_stat); 2850e44b6ecSShawn Guo 2860e44b6ecSShawn Guo chained_irq_exit(chip, desc); 287d37a65bbSShawn Guo } 288d37a65bbSShawn Guo 289d37a65bbSShawn Guo /* MX2 has one interrupt *for all* gpio ports */ 290d37a65bbSShawn Guo static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) 291d37a65bbSShawn Guo { 292d37a65bbSShawn Guo u32 irq_msk, irq_stat; 293b78d8e59SShawn Guo struct mxc_gpio_port *port; 294d37a65bbSShawn Guo 295d37a65bbSShawn Guo /* walk through all interrupt status registers */ 296b78d8e59SShawn Guo list_for_each_entry(port, &mxc_gpio_ports, node) { 297b78d8e59SShawn Guo irq_msk = readl(port->base + GPIO_IMR); 298d37a65bbSShawn Guo if (!irq_msk) 299d37a65bbSShawn Guo continue; 300d37a65bbSShawn Guo 301b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 302d37a65bbSShawn Guo if (irq_stat) 303b78d8e59SShawn Guo mxc_gpio_irq_handler(port, irq_stat); 304d37a65bbSShawn Guo } 305d37a65bbSShawn Guo } 306d37a65bbSShawn Guo 307d37a65bbSShawn Guo /* 308d37a65bbSShawn Guo * Set interrupt number "irq" in the GPIO as a wake-up source. 309d37a65bbSShawn Guo * While system is running, all registered GPIO interrupts need to have 310d37a65bbSShawn Guo * wake-up enabled. When system is suspended, only selected GPIO interrupts 311d37a65bbSShawn Guo * need to have wake-up enabled. 312d37a65bbSShawn Guo * @param irq interrupt source number 313d37a65bbSShawn Guo * @param enable enable as wake-up if equal to non-zero 314d37a65bbSShawn Guo * @return This function returns 0 on success. 315d37a65bbSShawn Guo */ 316d37a65bbSShawn Guo static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 317d37a65bbSShawn Guo { 318e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 319e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 3201ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 321d37a65bbSShawn Guo 322d37a65bbSShawn Guo if (enable) { 323d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 324d37a65bbSShawn Guo enable_irq_wake(port->irq_high); 325d37a65bbSShawn Guo else 326d37a65bbSShawn Guo enable_irq_wake(port->irq); 327d37a65bbSShawn Guo } else { 328d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 329d37a65bbSShawn Guo disable_irq_wake(port->irq_high); 330d37a65bbSShawn Guo else 331d37a65bbSShawn Guo disable_irq_wake(port->irq); 332d37a65bbSShawn Guo } 333d37a65bbSShawn Guo 334d37a65bbSShawn Guo return 0; 335d37a65bbSShawn Guo } 336d37a65bbSShawn Guo 3371ab7ef15SShawn Guo static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) 338e4ea9333SShawn Guo { 339e4ea9333SShawn Guo struct irq_chip_generic *gc; 340e4ea9333SShawn Guo struct irq_chip_type *ct; 341d37a65bbSShawn Guo 3421ab7ef15SShawn Guo gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base, 343e4ea9333SShawn Guo port->base, handle_level_irq); 344e4ea9333SShawn Guo gc->private = port; 345e4ea9333SShawn Guo 346e4ea9333SShawn Guo ct = gc->chip_types; 347591567a5SShawn Guo ct->chip.irq_ack = irq_gc_ack_set_bit; 348e4ea9333SShawn Guo ct->chip.irq_mask = irq_gc_mask_clr_bit; 349e4ea9333SShawn Guo ct->chip.irq_unmask = irq_gc_mask_set_bit; 350e4ea9333SShawn Guo ct->chip.irq_set_type = gpio_set_irq_type; 351591567a5SShawn Guo ct->chip.irq_set_wake = gpio_set_wake_irq; 352e4ea9333SShawn Guo ct->regs.ack = GPIO_ISR; 353e4ea9333SShawn Guo ct->regs.mask = GPIO_IMR; 354e4ea9333SShawn Guo 355e4ea9333SShawn Guo irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK, 356e4ea9333SShawn Guo IRQ_NOREQUEST, 0); 357e4ea9333SShawn Guo } 358d37a65bbSShawn Guo 359e7fc6ae7SShawn Guo static void __devinit mxc_gpio_get_hw(struct platform_device *pdev) 360e7fc6ae7SShawn Guo { 3618937cb60SShawn Guo const struct of_device_id *of_id = 3628937cb60SShawn Guo of_match_device(mxc_gpio_dt_ids, &pdev->dev); 3638937cb60SShawn Guo enum mxc_gpio_hwtype hwtype; 3648937cb60SShawn Guo 3658937cb60SShawn Guo if (of_id) 3668937cb60SShawn Guo pdev->id_entry = of_id->data; 3678937cb60SShawn Guo hwtype = pdev->id_entry->driver_data; 368e7fc6ae7SShawn Guo 369e7fc6ae7SShawn Guo if (mxc_gpio_hwtype) { 370e7fc6ae7SShawn Guo /* 371e7fc6ae7SShawn Guo * The driver works with a reasonable presupposition, 372e7fc6ae7SShawn Guo * that is all gpio ports must be the same type when 373e7fc6ae7SShawn Guo * running on one soc. 374e7fc6ae7SShawn Guo */ 375e7fc6ae7SShawn Guo BUG_ON(mxc_gpio_hwtype != hwtype); 376e7fc6ae7SShawn Guo return; 377e7fc6ae7SShawn Guo } 378e7fc6ae7SShawn Guo 379aeb27748SBenoît Thébaudeau if (hwtype == IMX35_GPIO) 380aeb27748SBenoît Thébaudeau mxc_gpio_hwdata = &imx35_gpio_hwdata; 381aeb27748SBenoît Thébaudeau else if (hwtype == IMX31_GPIO) 382e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx31_gpio_hwdata; 383e7fc6ae7SShawn Guo else 384e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata; 385e7fc6ae7SShawn Guo 386e7fc6ae7SShawn Guo mxc_gpio_hwtype = hwtype; 387e7fc6ae7SShawn Guo } 388e7fc6ae7SShawn Guo 38909ad8039SShawn Guo static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 39009ad8039SShawn Guo { 39109ad8039SShawn Guo struct bgpio_chip *bgc = to_bgpio_chip(gc); 39209ad8039SShawn Guo struct mxc_gpio_port *port = 39309ad8039SShawn Guo container_of(bgc, struct mxc_gpio_port, bgc); 39409ad8039SShawn Guo 3951ab7ef15SShawn Guo return irq_find_mapping(port->domain, offset); 39609ad8039SShawn Guo } 39709ad8039SShawn Guo 398b78d8e59SShawn Guo static int __devinit mxc_gpio_probe(struct platform_device *pdev) 399d37a65bbSShawn Guo { 4008937cb60SShawn Guo struct device_node *np = pdev->dev.of_node; 401b78d8e59SShawn Guo struct mxc_gpio_port *port; 402b78d8e59SShawn Guo struct resource *iores; 4031ab7ef15SShawn Guo int irq_base; 404e4ea9333SShawn Guo int err; 405d37a65bbSShawn Guo 406e7fc6ae7SShawn Guo mxc_gpio_get_hw(pdev); 407e7fc6ae7SShawn Guo 408b78d8e59SShawn Guo port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL); 409b78d8e59SShawn Guo if (!port) 410b78d8e59SShawn Guo return -ENOMEM; 411d37a65bbSShawn Guo 412b78d8e59SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 413b78d8e59SShawn Guo if (!iores) { 414b78d8e59SShawn Guo err = -ENODEV; 415b78d8e59SShawn Guo goto out_kfree; 416b78d8e59SShawn Guo } 417b78d8e59SShawn Guo 418b78d8e59SShawn Guo if (!request_mem_region(iores->start, resource_size(iores), 419b78d8e59SShawn Guo pdev->name)) { 420b78d8e59SShawn Guo err = -EBUSY; 421b78d8e59SShawn Guo goto out_kfree; 422b78d8e59SShawn Guo } 423b78d8e59SShawn Guo 424b78d8e59SShawn Guo port->base = ioremap(iores->start, resource_size(iores)); 425b78d8e59SShawn Guo if (!port->base) { 426b78d8e59SShawn Guo err = -ENOMEM; 427b78d8e59SShawn Guo goto out_release_mem; 428b78d8e59SShawn Guo } 429b78d8e59SShawn Guo 430b78d8e59SShawn Guo port->irq_high = platform_get_irq(pdev, 1); 431b78d8e59SShawn Guo port->irq = platform_get_irq(pdev, 0); 432b78d8e59SShawn Guo if (port->irq < 0) { 433b78d8e59SShawn Guo err = -EINVAL; 434b78d8e59SShawn Guo goto out_iounmap; 435b78d8e59SShawn Guo } 436b78d8e59SShawn Guo 437d37a65bbSShawn Guo /* disable the interrupt and clear the status */ 438b78d8e59SShawn Guo writel(0, port->base + GPIO_IMR); 439b78d8e59SShawn Guo writel(~0, port->base + GPIO_ISR); 440d37a65bbSShawn Guo 441e7fc6ae7SShawn Guo if (mxc_gpio_hwtype == IMX21_GPIO) { 44233a4e985SUwe Kleine-König /* 44333a4e985SUwe Kleine-König * Setup one handler for all GPIO interrupts. Actually setting 44433a4e985SUwe Kleine-König * the handler is needed only once, but doing it for every port 44533a4e985SUwe Kleine-König * is more robust and easier. 44633a4e985SUwe Kleine-König */ 44733a4e985SUwe Kleine-König irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); 448b78d8e59SShawn Guo } else { 449b78d8e59SShawn Guo /* setup one handler for each entry */ 450b78d8e59SShawn Guo irq_set_chained_handler(port->irq, mx3_gpio_irq_handler); 451b78d8e59SShawn Guo irq_set_handler_data(port->irq, port); 452b78d8e59SShawn Guo if (port->irq_high > 0) { 453b78d8e59SShawn Guo /* setup handler for GPIO 16 to 31 */ 454b78d8e59SShawn Guo irq_set_chained_handler(port->irq_high, 455b78d8e59SShawn Guo mx3_gpio_irq_handler); 456b78d8e59SShawn Guo irq_set_handler_data(port->irq_high, port); 457b78d8e59SShawn Guo } 458d37a65bbSShawn Guo } 459d37a65bbSShawn Guo 4602ce420daSShawn Guo err = bgpio_init(&port->bgc, &pdev->dev, 4, 4612ce420daSShawn Guo port->base + GPIO_PSR, 4622ce420daSShawn Guo port->base + GPIO_DR, NULL, 4633e11f7b8SShawn Guo port->base + GPIO_GDIR, NULL, 0); 464b78d8e59SShawn Guo if (err) 465b78d8e59SShawn Guo goto out_iounmap; 466b78d8e59SShawn Guo 46709ad8039SShawn Guo port->bgc.gc.to_irq = mxc_gpio_to_irq; 4682ce420daSShawn Guo port->bgc.gc.base = pdev->id * 32; 469fb149218SLothar Waßmann port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir); 470fb149218SLothar Waßmann port->bgc.data = port->bgc.read_reg(port->bgc.reg_set); 4712ce420daSShawn Guo 4722ce420daSShawn Guo err = gpiochip_add(&port->bgc.gc); 4732ce420daSShawn Guo if (err) 4742ce420daSShawn Guo goto out_bgpio_remove; 4752ce420daSShawn Guo 4761ab7ef15SShawn Guo irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id()); 4771ab7ef15SShawn Guo if (irq_base < 0) { 4781ab7ef15SShawn Guo err = irq_base; 4791ab7ef15SShawn Guo goto out_gpiochip_remove; 4801ab7ef15SShawn Guo } 4811ab7ef15SShawn Guo 4821ab7ef15SShawn Guo port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, 4831ab7ef15SShawn Guo &irq_domain_simple_ops, NULL); 4841ab7ef15SShawn Guo if (!port->domain) { 4851ab7ef15SShawn Guo err = -ENODEV; 4861ab7ef15SShawn Guo goto out_irqdesc_free; 4871ab7ef15SShawn Guo } 4888937cb60SShawn Guo 4898937cb60SShawn Guo /* gpio-mxc can be a generic irq chip */ 4901ab7ef15SShawn Guo mxc_gpio_init_gc(port, irq_base); 4918937cb60SShawn Guo 492b78d8e59SShawn Guo list_add_tail(&port->node, &mxc_gpio_ports); 493b78d8e59SShawn Guo 494d37a65bbSShawn Guo return 0; 495b78d8e59SShawn Guo 4961ab7ef15SShawn Guo out_irqdesc_free: 4971ab7ef15SShawn Guo irq_free_descs(irq_base, 32); 4981ab7ef15SShawn Guo out_gpiochip_remove: 4991ab7ef15SShawn Guo WARN_ON(gpiochip_remove(&port->bgc.gc) < 0); 5002ce420daSShawn Guo out_bgpio_remove: 5012ce420daSShawn Guo bgpio_remove(&port->bgc); 502b78d8e59SShawn Guo out_iounmap: 503b78d8e59SShawn Guo iounmap(port->base); 504b78d8e59SShawn Guo out_release_mem: 505b78d8e59SShawn Guo release_mem_region(iores->start, resource_size(iores)); 506b78d8e59SShawn Guo out_kfree: 507b78d8e59SShawn Guo kfree(port); 508b78d8e59SShawn Guo dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 509b78d8e59SShawn Guo return err; 510d37a65bbSShawn Guo } 511b78d8e59SShawn Guo 512b78d8e59SShawn Guo static struct platform_driver mxc_gpio_driver = { 513b78d8e59SShawn Guo .driver = { 514b78d8e59SShawn Guo .name = "gpio-mxc", 515b78d8e59SShawn Guo .owner = THIS_MODULE, 5168937cb60SShawn Guo .of_match_table = mxc_gpio_dt_ids, 517b78d8e59SShawn Guo }, 518b78d8e59SShawn Guo .probe = mxc_gpio_probe, 519e7fc6ae7SShawn Guo .id_table = mxc_gpio_devtype, 520b78d8e59SShawn Guo }; 521b78d8e59SShawn Guo 522b78d8e59SShawn Guo static int __init gpio_mxc_init(void) 523b78d8e59SShawn Guo { 524b78d8e59SShawn Guo return platform_driver_register(&mxc_gpio_driver); 525b78d8e59SShawn Guo } 526b78d8e59SShawn Guo postcore_initcall(gpio_mxc_init); 527b78d8e59SShawn Guo 528b78d8e59SShawn Guo MODULE_AUTHOR("Freescale Semiconductor, " 529b78d8e59SShawn Guo "Daniel Mack <danielncaiaq.de>, " 530b78d8e59SShawn Guo "Juergen Beisert <kernel@pengutronix.de>"); 531b78d8e59SShawn Guo MODULE_DESCRIPTION("Freescale MXC GPIO"); 532b78d8e59SShawn Guo MODULE_LICENSE("GPL"); 533