1d37a65bbSShawn Guo /* 2d37a65bbSShawn Guo * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 3d37a65bbSShawn Guo * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 4d37a65bbSShawn Guo * 5d37a65bbSShawn Guo * Based on code from Freescale, 6d37a65bbSShawn Guo * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 7d37a65bbSShawn Guo * 8d37a65bbSShawn Guo * This program is free software; you can redistribute it and/or 9d37a65bbSShawn Guo * modify it under the terms of the GNU General Public License 10d37a65bbSShawn Guo * as published by the Free Software Foundation; either version 2 11d37a65bbSShawn Guo * of the License, or (at your option) any later version. 12d37a65bbSShawn Guo * This program is distributed in the hope that it will be useful, 13d37a65bbSShawn Guo * but WITHOUT ANY WARRANTY; without even the implied warranty of 14d37a65bbSShawn Guo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15d37a65bbSShawn Guo * GNU General Public License for more details. 16d37a65bbSShawn Guo * 17d37a65bbSShawn Guo * You should have received a copy of the GNU General Public License 18d37a65bbSShawn Guo * along with this program; if not, write to the Free Software 19d37a65bbSShawn Guo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 20d37a65bbSShawn Guo */ 21d37a65bbSShawn Guo 22d37a65bbSShawn Guo #include <linux/init.h> 23d37a65bbSShawn Guo #include <linux/interrupt.h> 24d37a65bbSShawn Guo #include <linux/io.h> 25d37a65bbSShawn Guo #include <linux/irq.h> 26d37a65bbSShawn Guo #include <linux/gpio.h> 27b78d8e59SShawn Guo #include <linux/platform_device.h> 28b78d8e59SShawn Guo #include <linux/slab.h> 292ce420daSShawn Guo #include <linux/basic_mmio_gpio.h> 30d37a65bbSShawn Guo #include <asm-generic/bug.h> 31d37a65bbSShawn Guo 32e7fc6ae7SShawn Guo enum mxc_gpio_hwtype { 33e7fc6ae7SShawn Guo IMX1_GPIO, /* runs on i.mx1 */ 34e7fc6ae7SShawn Guo IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ 35e7fc6ae7SShawn Guo IMX31_GPIO, /* runs on all other i.mx */ 36e7fc6ae7SShawn Guo }; 37e7fc6ae7SShawn Guo 38e7fc6ae7SShawn Guo /* device type dependent stuff */ 39e7fc6ae7SShawn Guo struct mxc_gpio_hwdata { 40e7fc6ae7SShawn Guo unsigned dr_reg; 41e7fc6ae7SShawn Guo unsigned gdir_reg; 42e7fc6ae7SShawn Guo unsigned psr_reg; 43e7fc6ae7SShawn Guo unsigned icr1_reg; 44e7fc6ae7SShawn Guo unsigned icr2_reg; 45e7fc6ae7SShawn Guo unsigned imr_reg; 46e7fc6ae7SShawn Guo unsigned isr_reg; 47e7fc6ae7SShawn Guo unsigned low_level; 48e7fc6ae7SShawn Guo unsigned high_level; 49e7fc6ae7SShawn Guo unsigned rise_edge; 50e7fc6ae7SShawn Guo unsigned fall_edge; 51e7fc6ae7SShawn Guo }; 52e7fc6ae7SShawn Guo 53b78d8e59SShawn Guo struct mxc_gpio_port { 54b78d8e59SShawn Guo struct list_head node; 55b78d8e59SShawn Guo void __iomem *base; 56b78d8e59SShawn Guo int irq; 57b78d8e59SShawn Guo int irq_high; 58b78d8e59SShawn Guo int virtual_irq_start; 592ce420daSShawn Guo struct bgpio_chip bgc; 60b78d8e59SShawn Guo u32 both_edges; 61b78d8e59SShawn Guo }; 62b78d8e59SShawn Guo 63e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 64e7fc6ae7SShawn Guo .dr_reg = 0x1c, 65e7fc6ae7SShawn Guo .gdir_reg = 0x00, 66e7fc6ae7SShawn Guo .psr_reg = 0x24, 67e7fc6ae7SShawn Guo .icr1_reg = 0x28, 68e7fc6ae7SShawn Guo .icr2_reg = 0x2c, 69e7fc6ae7SShawn Guo .imr_reg = 0x30, 70e7fc6ae7SShawn Guo .isr_reg = 0x34, 71e7fc6ae7SShawn Guo .low_level = 0x03, 72e7fc6ae7SShawn Guo .high_level = 0x02, 73e7fc6ae7SShawn Guo .rise_edge = 0x00, 74e7fc6ae7SShawn Guo .fall_edge = 0x01, 75e7fc6ae7SShawn Guo }; 76e7fc6ae7SShawn Guo 77e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 78e7fc6ae7SShawn Guo .dr_reg = 0x00, 79e7fc6ae7SShawn Guo .gdir_reg = 0x04, 80e7fc6ae7SShawn Guo .psr_reg = 0x08, 81e7fc6ae7SShawn Guo .icr1_reg = 0x0c, 82e7fc6ae7SShawn Guo .icr2_reg = 0x10, 83e7fc6ae7SShawn Guo .imr_reg = 0x14, 84e7fc6ae7SShawn Guo .isr_reg = 0x18, 85e7fc6ae7SShawn Guo .low_level = 0x00, 86e7fc6ae7SShawn Guo .high_level = 0x01, 87e7fc6ae7SShawn Guo .rise_edge = 0x02, 88e7fc6ae7SShawn Guo .fall_edge = 0x03, 89e7fc6ae7SShawn Guo }; 90e7fc6ae7SShawn Guo 91e7fc6ae7SShawn Guo static enum mxc_gpio_hwtype mxc_gpio_hwtype; 92e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata *mxc_gpio_hwdata; 93e7fc6ae7SShawn Guo 94e7fc6ae7SShawn Guo #define GPIO_DR (mxc_gpio_hwdata->dr_reg) 95e7fc6ae7SShawn Guo #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg) 96e7fc6ae7SShawn Guo #define GPIO_PSR (mxc_gpio_hwdata->psr_reg) 97e7fc6ae7SShawn Guo #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg) 98e7fc6ae7SShawn Guo #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg) 99e7fc6ae7SShawn Guo #define GPIO_IMR (mxc_gpio_hwdata->imr_reg) 100e7fc6ae7SShawn Guo #define GPIO_ISR (mxc_gpio_hwdata->isr_reg) 101e7fc6ae7SShawn Guo 102e7fc6ae7SShawn Guo #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level) 103e7fc6ae7SShawn Guo #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level) 104e7fc6ae7SShawn Guo #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge) 105e7fc6ae7SShawn Guo #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge) 106e7fc6ae7SShawn Guo #define GPIO_INT_NONE 0x4 107e7fc6ae7SShawn Guo 108e7fc6ae7SShawn Guo static struct platform_device_id mxc_gpio_devtype[] = { 109e7fc6ae7SShawn Guo { 110e7fc6ae7SShawn Guo .name = "imx1-gpio", 111e7fc6ae7SShawn Guo .driver_data = IMX1_GPIO, 112e7fc6ae7SShawn Guo }, { 113e7fc6ae7SShawn Guo .name = "imx21-gpio", 114e7fc6ae7SShawn Guo .driver_data = IMX21_GPIO, 115e7fc6ae7SShawn Guo }, { 116e7fc6ae7SShawn Guo .name = "imx31-gpio", 117e7fc6ae7SShawn Guo .driver_data = IMX31_GPIO, 118e7fc6ae7SShawn Guo }, { 119e7fc6ae7SShawn Guo /* sentinel */ 120e7fc6ae7SShawn Guo } 121e7fc6ae7SShawn Guo }; 122e7fc6ae7SShawn Guo 123b78d8e59SShawn Guo /* 124b78d8e59SShawn Guo * MX2 has one interrupt *for all* gpio ports. The list is used 125b78d8e59SShawn Guo * to save the references to all ports, so that mx2_gpio_irq_handler 126b78d8e59SShawn Guo * can walk through all interrupt status registers. 127b78d8e59SShawn Guo */ 128b78d8e59SShawn Guo static LIST_HEAD(mxc_gpio_ports); 129d37a65bbSShawn Guo 130d37a65bbSShawn Guo /* Note: This driver assumes 32 GPIOs are handled in one register */ 131d37a65bbSShawn Guo 132d37a65bbSShawn Guo static int gpio_set_irq_type(struct irq_data *d, u32 type) 133d37a65bbSShawn Guo { 134d37a65bbSShawn Guo u32 gpio = irq_to_gpio(d->irq); 135e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 136e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 137d37a65bbSShawn Guo u32 bit, val; 138d37a65bbSShawn Guo int edge; 139d37a65bbSShawn Guo void __iomem *reg = port->base; 140d37a65bbSShawn Guo 141d37a65bbSShawn Guo port->both_edges &= ~(1 << (gpio & 31)); 142d37a65bbSShawn Guo switch (type) { 143d37a65bbSShawn Guo case IRQ_TYPE_EDGE_RISING: 144d37a65bbSShawn Guo edge = GPIO_INT_RISE_EDGE; 145d37a65bbSShawn Guo break; 146d37a65bbSShawn Guo case IRQ_TYPE_EDGE_FALLING: 147d37a65bbSShawn Guo edge = GPIO_INT_FALL_EDGE; 148d37a65bbSShawn Guo break; 149d37a65bbSShawn Guo case IRQ_TYPE_EDGE_BOTH: 1505523f86bSShawn Guo val = gpio_get_value(gpio); 151d37a65bbSShawn Guo if (val) { 152d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 153d37a65bbSShawn Guo pr_debug("mxc: set GPIO %d to low trigger\n", gpio); 154d37a65bbSShawn Guo } else { 155d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 156d37a65bbSShawn Guo pr_debug("mxc: set GPIO %d to high trigger\n", gpio); 157d37a65bbSShawn Guo } 158d37a65bbSShawn Guo port->both_edges |= 1 << (gpio & 31); 159d37a65bbSShawn Guo break; 160d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_LOW: 161d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 162d37a65bbSShawn Guo break; 163d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_HIGH: 164d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 165d37a65bbSShawn Guo break; 166d37a65bbSShawn Guo default: 167d37a65bbSShawn Guo return -EINVAL; 168d37a65bbSShawn Guo } 169d37a65bbSShawn Guo 170d37a65bbSShawn Guo reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 171d37a65bbSShawn Guo bit = gpio & 0xf; 172b78d8e59SShawn Guo val = readl(reg) & ~(0x3 << (bit << 1)); 173b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 174e4ea9333SShawn Guo writel(1 << (gpio & 0x1f), port->base + GPIO_ISR); 175d37a65bbSShawn Guo 176d37a65bbSShawn Guo return 0; 177d37a65bbSShawn Guo } 178d37a65bbSShawn Guo 179d37a65bbSShawn Guo static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 180d37a65bbSShawn Guo { 181d37a65bbSShawn Guo void __iomem *reg = port->base; 182d37a65bbSShawn Guo u32 bit, val; 183d37a65bbSShawn Guo int edge; 184d37a65bbSShawn Guo 185d37a65bbSShawn Guo reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 186d37a65bbSShawn Guo bit = gpio & 0xf; 187b78d8e59SShawn Guo val = readl(reg); 188d37a65bbSShawn Guo edge = (val >> (bit << 1)) & 3; 189d37a65bbSShawn Guo val &= ~(0x3 << (bit << 1)); 190d37a65bbSShawn Guo if (edge == GPIO_INT_HIGH_LEV) { 191d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 192d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 193d37a65bbSShawn Guo } else if (edge == GPIO_INT_LOW_LEV) { 194d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 195d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 196d37a65bbSShawn Guo } else { 197d37a65bbSShawn Guo pr_err("mxc: invalid configuration for GPIO %d: %x\n", 198d37a65bbSShawn Guo gpio, edge); 199d37a65bbSShawn Guo return; 200d37a65bbSShawn Guo } 201b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 202d37a65bbSShawn Guo } 203d37a65bbSShawn Guo 204d37a65bbSShawn Guo /* handle 32 interrupts in one status register */ 205d37a65bbSShawn Guo static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 206d37a65bbSShawn Guo { 207d37a65bbSShawn Guo u32 gpio_irq_no_base = port->virtual_irq_start; 208d37a65bbSShawn Guo 209d37a65bbSShawn Guo while (irq_stat != 0) { 210d37a65bbSShawn Guo int irqoffset = fls(irq_stat) - 1; 211d37a65bbSShawn Guo 212d37a65bbSShawn Guo if (port->both_edges & (1 << irqoffset)) 213d37a65bbSShawn Guo mxc_flip_edge(port, irqoffset); 214d37a65bbSShawn Guo 215d37a65bbSShawn Guo generic_handle_irq(gpio_irq_no_base + irqoffset); 216d37a65bbSShawn Guo 217d37a65bbSShawn Guo irq_stat &= ~(1 << irqoffset); 218d37a65bbSShawn Guo } 219d37a65bbSShawn Guo } 220d37a65bbSShawn Guo 221d37a65bbSShawn Guo /* MX1 and MX3 has one interrupt *per* gpio port */ 222d37a65bbSShawn Guo static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) 223d37a65bbSShawn Guo { 224d37a65bbSShawn Guo u32 irq_stat; 225d37a65bbSShawn Guo struct mxc_gpio_port *port = irq_get_handler_data(irq); 226d37a65bbSShawn Guo 227b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 228d37a65bbSShawn Guo 229d37a65bbSShawn Guo mxc_gpio_irq_handler(port, irq_stat); 230d37a65bbSShawn Guo } 231d37a65bbSShawn Guo 232d37a65bbSShawn Guo /* MX2 has one interrupt *for all* gpio ports */ 233d37a65bbSShawn Guo static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) 234d37a65bbSShawn Guo { 235d37a65bbSShawn Guo u32 irq_msk, irq_stat; 236b78d8e59SShawn Guo struct mxc_gpio_port *port; 237d37a65bbSShawn Guo 238d37a65bbSShawn Guo /* walk through all interrupt status registers */ 239b78d8e59SShawn Guo list_for_each_entry(port, &mxc_gpio_ports, node) { 240b78d8e59SShawn Guo irq_msk = readl(port->base + GPIO_IMR); 241d37a65bbSShawn Guo if (!irq_msk) 242d37a65bbSShawn Guo continue; 243d37a65bbSShawn Guo 244b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 245d37a65bbSShawn Guo if (irq_stat) 246b78d8e59SShawn Guo mxc_gpio_irq_handler(port, irq_stat); 247d37a65bbSShawn Guo } 248d37a65bbSShawn Guo } 249d37a65bbSShawn Guo 250d37a65bbSShawn Guo /* 251d37a65bbSShawn Guo * Set interrupt number "irq" in the GPIO as a wake-up source. 252d37a65bbSShawn Guo * While system is running, all registered GPIO interrupts need to have 253d37a65bbSShawn Guo * wake-up enabled. When system is suspended, only selected GPIO interrupts 254d37a65bbSShawn Guo * need to have wake-up enabled. 255d37a65bbSShawn Guo * @param irq interrupt source number 256d37a65bbSShawn Guo * @param enable enable as wake-up if equal to non-zero 257d37a65bbSShawn Guo * @return This function returns 0 on success. 258d37a65bbSShawn Guo */ 259d37a65bbSShawn Guo static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 260d37a65bbSShawn Guo { 261d37a65bbSShawn Guo u32 gpio = irq_to_gpio(d->irq); 262d37a65bbSShawn Guo u32 gpio_idx = gpio & 0x1F; 263e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 264e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 265d37a65bbSShawn Guo 266d37a65bbSShawn Guo if (enable) { 267d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 268d37a65bbSShawn Guo enable_irq_wake(port->irq_high); 269d37a65bbSShawn Guo else 270d37a65bbSShawn Guo enable_irq_wake(port->irq); 271d37a65bbSShawn Guo } else { 272d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 273d37a65bbSShawn Guo disable_irq_wake(port->irq_high); 274d37a65bbSShawn Guo else 275d37a65bbSShawn Guo disable_irq_wake(port->irq); 276d37a65bbSShawn Guo } 277d37a65bbSShawn Guo 278d37a65bbSShawn Guo return 0; 279d37a65bbSShawn Guo } 280d37a65bbSShawn Guo 281e4ea9333SShawn Guo static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port) 282e4ea9333SShawn Guo { 283e4ea9333SShawn Guo struct irq_chip_generic *gc; 284e4ea9333SShawn Guo struct irq_chip_type *ct; 285d37a65bbSShawn Guo 286e4ea9333SShawn Guo gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start, 287e4ea9333SShawn Guo port->base, handle_level_irq); 288e4ea9333SShawn Guo gc->private = port; 289e4ea9333SShawn Guo 290e4ea9333SShawn Guo ct = gc->chip_types; 291e4ea9333SShawn Guo ct->chip.irq_ack = irq_gc_ack, 292e4ea9333SShawn Guo ct->chip.irq_mask = irq_gc_mask_clr_bit; 293e4ea9333SShawn Guo ct->chip.irq_unmask = irq_gc_mask_set_bit; 294e4ea9333SShawn Guo ct->chip.irq_set_type = gpio_set_irq_type; 295e4ea9333SShawn Guo ct->chip.irq_set_wake = gpio_set_wake_irq, 296e4ea9333SShawn Guo ct->regs.ack = GPIO_ISR; 297e4ea9333SShawn Guo ct->regs.mask = GPIO_IMR; 298e4ea9333SShawn Guo 299e4ea9333SShawn Guo irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK, 300e4ea9333SShawn Guo IRQ_NOREQUEST, 0); 301e4ea9333SShawn Guo } 302d37a65bbSShawn Guo 303e7fc6ae7SShawn Guo static void __devinit mxc_gpio_get_hw(struct platform_device *pdev) 304e7fc6ae7SShawn Guo { 305e7fc6ae7SShawn Guo enum mxc_gpio_hwtype hwtype = pdev->id_entry->driver_data; 306e7fc6ae7SShawn Guo 307e7fc6ae7SShawn Guo if (mxc_gpio_hwtype) { 308e7fc6ae7SShawn Guo /* 309e7fc6ae7SShawn Guo * The driver works with a reasonable presupposition, 310e7fc6ae7SShawn Guo * that is all gpio ports must be the same type when 311e7fc6ae7SShawn Guo * running on one soc. 312e7fc6ae7SShawn Guo */ 313e7fc6ae7SShawn Guo BUG_ON(mxc_gpio_hwtype != hwtype); 314e7fc6ae7SShawn Guo return; 315e7fc6ae7SShawn Guo } 316e7fc6ae7SShawn Guo 317e7fc6ae7SShawn Guo if (hwtype == IMX31_GPIO) 318e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx31_gpio_hwdata; 319e7fc6ae7SShawn Guo else 320e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata; 321e7fc6ae7SShawn Guo 322e7fc6ae7SShawn Guo mxc_gpio_hwtype = hwtype; 323e7fc6ae7SShawn Guo } 324e7fc6ae7SShawn Guo 325b78d8e59SShawn Guo static int __devinit mxc_gpio_probe(struct platform_device *pdev) 326d37a65bbSShawn Guo { 327b78d8e59SShawn Guo struct mxc_gpio_port *port; 328b78d8e59SShawn Guo struct resource *iores; 329e4ea9333SShawn Guo int err; 330d37a65bbSShawn Guo 331e7fc6ae7SShawn Guo mxc_gpio_get_hw(pdev); 332e7fc6ae7SShawn Guo 333b78d8e59SShawn Guo port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL); 334b78d8e59SShawn Guo if (!port) 335b78d8e59SShawn Guo return -ENOMEM; 336d37a65bbSShawn Guo 337b78d8e59SShawn Guo port->virtual_irq_start = MXC_GPIO_IRQ_START + pdev->id * 32; 338d37a65bbSShawn Guo 339b78d8e59SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 340b78d8e59SShawn Guo if (!iores) { 341b78d8e59SShawn Guo err = -ENODEV; 342b78d8e59SShawn Guo goto out_kfree; 343b78d8e59SShawn Guo } 344b78d8e59SShawn Guo 345b78d8e59SShawn Guo if (!request_mem_region(iores->start, resource_size(iores), 346b78d8e59SShawn Guo pdev->name)) { 347b78d8e59SShawn Guo err = -EBUSY; 348b78d8e59SShawn Guo goto out_kfree; 349b78d8e59SShawn Guo } 350b78d8e59SShawn Guo 351b78d8e59SShawn Guo port->base = ioremap(iores->start, resource_size(iores)); 352b78d8e59SShawn Guo if (!port->base) { 353b78d8e59SShawn Guo err = -ENOMEM; 354b78d8e59SShawn Guo goto out_release_mem; 355b78d8e59SShawn Guo } 356b78d8e59SShawn Guo 357b78d8e59SShawn Guo port->irq_high = platform_get_irq(pdev, 1); 358b78d8e59SShawn Guo port->irq = platform_get_irq(pdev, 0); 359b78d8e59SShawn Guo if (port->irq < 0) { 360b78d8e59SShawn Guo err = -EINVAL; 361b78d8e59SShawn Guo goto out_iounmap; 362b78d8e59SShawn Guo } 363b78d8e59SShawn Guo 364d37a65bbSShawn Guo /* disable the interrupt and clear the status */ 365b78d8e59SShawn Guo writel(0, port->base + GPIO_IMR); 366b78d8e59SShawn Guo writel(~0, port->base + GPIO_ISR); 367d37a65bbSShawn Guo 368e4ea9333SShawn Guo /* gpio-mxc can be a generic irq chip */ 369e4ea9333SShawn Guo mxc_gpio_init_gc(port); 370d37a65bbSShawn Guo 371e7fc6ae7SShawn Guo if (mxc_gpio_hwtype == IMX21_GPIO) { 372d37a65bbSShawn Guo /* setup one handler for all GPIO interrupts */ 373b78d8e59SShawn Guo if (pdev->id == 0) 374b78d8e59SShawn Guo irq_set_chained_handler(port->irq, 375b78d8e59SShawn Guo mx2_gpio_irq_handler); 376b78d8e59SShawn Guo } else { 377b78d8e59SShawn Guo /* setup one handler for each entry */ 378b78d8e59SShawn Guo irq_set_chained_handler(port->irq, mx3_gpio_irq_handler); 379b78d8e59SShawn Guo irq_set_handler_data(port->irq, port); 380b78d8e59SShawn Guo if (port->irq_high > 0) { 381b78d8e59SShawn Guo /* setup handler for GPIO 16 to 31 */ 382b78d8e59SShawn Guo irq_set_chained_handler(port->irq_high, 383b78d8e59SShawn Guo mx3_gpio_irq_handler); 384b78d8e59SShawn Guo irq_set_handler_data(port->irq_high, port); 385b78d8e59SShawn Guo } 386d37a65bbSShawn Guo } 387d37a65bbSShawn Guo 3882ce420daSShawn Guo err = bgpio_init(&port->bgc, &pdev->dev, 4, 3892ce420daSShawn Guo port->base + GPIO_PSR, 3902ce420daSShawn Guo port->base + GPIO_DR, NULL, 3912ce420daSShawn Guo port->base + GPIO_GDIR, NULL, false); 392b78d8e59SShawn Guo if (err) 393b78d8e59SShawn Guo goto out_iounmap; 394b78d8e59SShawn Guo 3952ce420daSShawn Guo port->bgc.gc.base = pdev->id * 32; 396fb149218SLothar Waßmann port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir); 397fb149218SLothar Waßmann port->bgc.data = port->bgc.read_reg(port->bgc.reg_set); 3982ce420daSShawn Guo 3992ce420daSShawn Guo err = gpiochip_add(&port->bgc.gc); 4002ce420daSShawn Guo if (err) 4012ce420daSShawn Guo goto out_bgpio_remove; 4022ce420daSShawn Guo 403b78d8e59SShawn Guo list_add_tail(&port->node, &mxc_gpio_ports); 404b78d8e59SShawn Guo 405d37a65bbSShawn Guo return 0; 406b78d8e59SShawn Guo 4072ce420daSShawn Guo out_bgpio_remove: 4082ce420daSShawn Guo bgpio_remove(&port->bgc); 409b78d8e59SShawn Guo out_iounmap: 410b78d8e59SShawn Guo iounmap(port->base); 411b78d8e59SShawn Guo out_release_mem: 412b78d8e59SShawn Guo release_mem_region(iores->start, resource_size(iores)); 413b78d8e59SShawn Guo out_kfree: 414b78d8e59SShawn Guo kfree(port); 415b78d8e59SShawn Guo dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 416b78d8e59SShawn Guo return err; 417d37a65bbSShawn Guo } 418b78d8e59SShawn Guo 419b78d8e59SShawn Guo static struct platform_driver mxc_gpio_driver = { 420b78d8e59SShawn Guo .driver = { 421b78d8e59SShawn Guo .name = "gpio-mxc", 422b78d8e59SShawn Guo .owner = THIS_MODULE, 423b78d8e59SShawn Guo }, 424b78d8e59SShawn Guo .probe = mxc_gpio_probe, 425e7fc6ae7SShawn Guo .id_table = mxc_gpio_devtype, 426b78d8e59SShawn Guo }; 427b78d8e59SShawn Guo 428b78d8e59SShawn Guo static int __init gpio_mxc_init(void) 429b78d8e59SShawn Guo { 430b78d8e59SShawn Guo return platform_driver_register(&mxc_gpio_driver); 431b78d8e59SShawn Guo } 432b78d8e59SShawn Guo postcore_initcall(gpio_mxc_init); 433b78d8e59SShawn Guo 434b78d8e59SShawn Guo MODULE_AUTHOR("Freescale Semiconductor, " 435b78d8e59SShawn Guo "Daniel Mack <danielncaiaq.de>, " 436b78d8e59SShawn Guo "Juergen Beisert <kernel@pengutronix.de>"); 437b78d8e59SShawn Guo MODULE_DESCRIPTION("Freescale MXC GPIO"); 438b78d8e59SShawn Guo MODULE_LICENSE("GPL"); 439