1014e420dSFabio Estevam // SPDX-License-Identifier: GPL-2.0+ 2014e420dSFabio Estevam // 3014e420dSFabio Estevam // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 4014e420dSFabio Estevam // Copyright 2008 Juergen Beisert, kernel@pengutronix.de 5014e420dSFabio Estevam // 6014e420dSFabio Estevam // Based on code from Freescale Semiconductor, 7014e420dSFabio Estevam // Authors: Daniel Mack, Juergen Beisert. 8014e420dSFabio Estevam // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9d37a65bbSShawn Guo 102808801aSAnson Huang #include <linux/clk.h> 1118f92b19SFabio Estevam #include <linux/err.h> 12d37a65bbSShawn Guo #include <linux/init.h> 13d37a65bbSShawn Guo #include <linux/interrupt.h> 14d37a65bbSShawn Guo #include <linux/io.h> 15d37a65bbSShawn Guo #include <linux/irq.h> 161ab7ef15SShawn Guo #include <linux/irqdomain.h> 17de88cbb7SCatalin Marinas #include <linux/irqchip/chained_irq.h> 1812d16b39SAnson Huang #include <linux/module.h> 19b78d8e59SShawn Guo #include <linux/platform_device.h> 20b78d8e59SShawn Guo #include <linux/slab.h> 21*e5464277SMarek Vasut #include <linux/spinlock.h> 221a5287a3SAnson Huang #include <linux/syscore_ops.h> 230f4630f3SLinus Walleij #include <linux/gpio/driver.h> 248937cb60SShawn Guo #include <linux/of.h> 258937cb60SShawn Guo #include <linux/of_device.h> 2616c3bd35SChristoph Hellwig #include <linux/bug.h> 27d37a65bbSShawn Guo 28f60c9eacSShenwei Wang #define IMX_SCU_WAKEUP_OFF 0 29f60c9eacSShenwei Wang #define IMX_SCU_WAKEUP_LOW_LVL 4 30f60c9eacSShenwei Wang #define IMX_SCU_WAKEUP_FALL_EDGE 5 31f60c9eacSShenwei Wang #define IMX_SCU_WAKEUP_RISE_EDGE 6 32f60c9eacSShenwei Wang #define IMX_SCU_WAKEUP_HIGH_LVL 7 33f60c9eacSShenwei Wang 34e7fc6ae7SShawn Guo /* device type dependent stuff */ 35e7fc6ae7SShawn Guo struct mxc_gpio_hwdata { 36e7fc6ae7SShawn Guo unsigned dr_reg; 37e7fc6ae7SShawn Guo unsigned gdir_reg; 38e7fc6ae7SShawn Guo unsigned psr_reg; 39e7fc6ae7SShawn Guo unsigned icr1_reg; 40e7fc6ae7SShawn Guo unsigned icr2_reg; 41e7fc6ae7SShawn Guo unsigned imr_reg; 42e7fc6ae7SShawn Guo unsigned isr_reg; 43aeb27748SBenoît Thébaudeau int edge_sel_reg; 44e7fc6ae7SShawn Guo unsigned low_level; 45e7fc6ae7SShawn Guo unsigned high_level; 46e7fc6ae7SShawn Guo unsigned rise_edge; 47e7fc6ae7SShawn Guo unsigned fall_edge; 48e7fc6ae7SShawn Guo }; 49e7fc6ae7SShawn Guo 50c19fdaeeSAnson Huang struct mxc_gpio_reg_saved { 51c19fdaeeSAnson Huang u32 icr1; 52c19fdaeeSAnson Huang u32 icr2; 53c19fdaeeSAnson Huang u32 imr; 54c19fdaeeSAnson Huang u32 gdir; 55c19fdaeeSAnson Huang u32 edge_sel; 56c19fdaeeSAnson Huang u32 dr; 57c19fdaeeSAnson Huang }; 58c19fdaeeSAnson Huang 59b78d8e59SShawn Guo struct mxc_gpio_port { 60b78d8e59SShawn Guo struct list_head node; 61b78d8e59SShawn Guo void __iomem *base; 622808801aSAnson Huang struct clk *clk; 63b78d8e59SShawn Guo int irq; 64b78d8e59SShawn Guo int irq_high; 651ab7ef15SShawn Guo struct irq_domain *domain; 660f4630f3SLinus Walleij struct gpio_chip gc; 67db5270acSBartosz Golaszewski struct device *dev; 68b78d8e59SShawn Guo u32 both_edges; 69c19fdaeeSAnson Huang struct mxc_gpio_reg_saved gpio_saved_reg; 70c19fdaeeSAnson Huang bool power_off; 71f60c9eacSShenwei Wang u32 wakeup_pads; 72f60c9eacSShenwei Wang bool is_pad_wakeup; 73f60c9eacSShenwei Wang u32 pad_type[32]; 740f2c7af4SFabio Estevam const struct mxc_gpio_hwdata *hwdata; 75b78d8e59SShawn Guo }; 76b78d8e59SShawn Guo 77e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 78e7fc6ae7SShawn Guo .dr_reg = 0x1c, 79e7fc6ae7SShawn Guo .gdir_reg = 0x00, 80e7fc6ae7SShawn Guo .psr_reg = 0x24, 81e7fc6ae7SShawn Guo .icr1_reg = 0x28, 82e7fc6ae7SShawn Guo .icr2_reg = 0x2c, 83e7fc6ae7SShawn Guo .imr_reg = 0x30, 84e7fc6ae7SShawn Guo .isr_reg = 0x34, 85aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 86e7fc6ae7SShawn Guo .low_level = 0x03, 87e7fc6ae7SShawn Guo .high_level = 0x02, 88e7fc6ae7SShawn Guo .rise_edge = 0x00, 89e7fc6ae7SShawn Guo .fall_edge = 0x01, 90e7fc6ae7SShawn Guo }; 91e7fc6ae7SShawn Guo 92e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 93e7fc6ae7SShawn Guo .dr_reg = 0x00, 94e7fc6ae7SShawn Guo .gdir_reg = 0x04, 95e7fc6ae7SShawn Guo .psr_reg = 0x08, 96e7fc6ae7SShawn Guo .icr1_reg = 0x0c, 97e7fc6ae7SShawn Guo .icr2_reg = 0x10, 98e7fc6ae7SShawn Guo .imr_reg = 0x14, 99e7fc6ae7SShawn Guo .isr_reg = 0x18, 100aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 101aeb27748SBenoît Thébaudeau .low_level = 0x00, 102aeb27748SBenoît Thébaudeau .high_level = 0x01, 103aeb27748SBenoît Thébaudeau .rise_edge = 0x02, 104aeb27748SBenoît Thébaudeau .fall_edge = 0x03, 105aeb27748SBenoît Thébaudeau }; 106aeb27748SBenoît Thébaudeau 107aeb27748SBenoît Thébaudeau static struct mxc_gpio_hwdata imx35_gpio_hwdata = { 108aeb27748SBenoît Thébaudeau .dr_reg = 0x00, 109aeb27748SBenoît Thébaudeau .gdir_reg = 0x04, 110aeb27748SBenoît Thébaudeau .psr_reg = 0x08, 111aeb27748SBenoît Thébaudeau .icr1_reg = 0x0c, 112aeb27748SBenoît Thébaudeau .icr2_reg = 0x10, 113aeb27748SBenoît Thébaudeau .imr_reg = 0x14, 114aeb27748SBenoît Thébaudeau .isr_reg = 0x18, 115aeb27748SBenoît Thébaudeau .edge_sel_reg = 0x1c, 116e7fc6ae7SShawn Guo .low_level = 0x00, 117e7fc6ae7SShawn Guo .high_level = 0x01, 118e7fc6ae7SShawn Guo .rise_edge = 0x02, 119e7fc6ae7SShawn Guo .fall_edge = 0x03, 120e7fc6ae7SShawn Guo }; 121e7fc6ae7SShawn Guo 1220f2c7af4SFabio Estevam #define GPIO_DR (port->hwdata->dr_reg) 1230f2c7af4SFabio Estevam #define GPIO_GDIR (port->hwdata->gdir_reg) 1240f2c7af4SFabio Estevam #define GPIO_PSR (port->hwdata->psr_reg) 1250f2c7af4SFabio Estevam #define GPIO_ICR1 (port->hwdata->icr1_reg) 1260f2c7af4SFabio Estevam #define GPIO_ICR2 (port->hwdata->icr2_reg) 1270f2c7af4SFabio Estevam #define GPIO_IMR (port->hwdata->imr_reg) 1280f2c7af4SFabio Estevam #define GPIO_ISR (port->hwdata->isr_reg) 1290f2c7af4SFabio Estevam #define GPIO_EDGE_SEL (port->hwdata->edge_sel_reg) 130e7fc6ae7SShawn Guo 1310f2c7af4SFabio Estevam #define GPIO_INT_LOW_LEV (port->hwdata->low_level) 1320f2c7af4SFabio Estevam #define GPIO_INT_HIGH_LEV (port->hwdata->high_level) 1330f2c7af4SFabio Estevam #define GPIO_INT_RISE_EDGE (port->hwdata->rise_edge) 1340f2c7af4SFabio Estevam #define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge) 135aeb27748SBenoît Thébaudeau #define GPIO_INT_BOTH_EDGES 0x4 136e7fc6ae7SShawn Guo 1378937cb60SShawn Guo static const struct of_device_id mxc_gpio_dt_ids[] = { 1380f2c7af4SFabio Estevam { .compatible = "fsl,imx1-gpio", .data = &imx1_imx21_gpio_hwdata }, 1390f2c7af4SFabio Estevam { .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata }, 1400f2c7af4SFabio Estevam { .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata }, 1410f2c7af4SFabio Estevam { .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata }, 1420f2c7af4SFabio Estevam { .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata }, 143f60c9eacSShenwei Wang { .compatible = "fsl,imx8dxl-gpio", .data = &imx35_gpio_hwdata }, 144f60c9eacSShenwei Wang { .compatible = "fsl,imx8qm-gpio", .data = &imx35_gpio_hwdata }, 145f60c9eacSShenwei Wang { .compatible = "fsl,imx8qxp-gpio", .data = &imx35_gpio_hwdata }, 1468937cb60SShawn Guo { /* sentinel */ } 1478937cb60SShawn Guo }; 14812d16b39SAnson Huang MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids); 1498937cb60SShawn Guo 150b78d8e59SShawn Guo /* 151b78d8e59SShawn Guo * MX2 has one interrupt *for all* gpio ports. The list is used 152b78d8e59SShawn Guo * to save the references to all ports, so that mx2_gpio_irq_handler 153b78d8e59SShawn Guo * can walk through all interrupt status registers. 154b78d8e59SShawn Guo */ 155b78d8e59SShawn Guo static LIST_HEAD(mxc_gpio_ports); 156d37a65bbSShawn Guo 157d37a65bbSShawn Guo /* Note: This driver assumes 32 GPIOs are handled in one register */ 158d37a65bbSShawn Guo 159d37a65bbSShawn Guo static int gpio_set_irq_type(struct irq_data *d, u32 type) 160d37a65bbSShawn Guo { 161e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 162e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 163*e5464277SMarek Vasut unsigned long flags; 164d37a65bbSShawn Guo u32 bit, val; 1651ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 166d37a65bbSShawn Guo int edge; 167d37a65bbSShawn Guo void __iomem *reg = port->base; 168d37a65bbSShawn Guo 1691ab7ef15SShawn Guo port->both_edges &= ~(1 << gpio_idx); 170d37a65bbSShawn Guo switch (type) { 171d37a65bbSShawn Guo case IRQ_TYPE_EDGE_RISING: 172d37a65bbSShawn Guo edge = GPIO_INT_RISE_EDGE; 173d37a65bbSShawn Guo break; 174d37a65bbSShawn Guo case IRQ_TYPE_EDGE_FALLING: 175d37a65bbSShawn Guo edge = GPIO_INT_FALL_EDGE; 176d37a65bbSShawn Guo break; 177d37a65bbSShawn Guo case IRQ_TYPE_EDGE_BOTH: 178aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 179aeb27748SBenoît Thébaudeau edge = GPIO_INT_BOTH_EDGES; 180aeb27748SBenoît Thébaudeau } else { 1818d0bd9a5SLinus Walleij val = port->gc.get(&port->gc, gpio_idx); 182d37a65bbSShawn Guo if (val) { 183d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 1848d0bd9a5SLinus Walleij pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx); 185d37a65bbSShawn Guo } else { 186d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 1878d0bd9a5SLinus Walleij pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx); 188d37a65bbSShawn Guo } 1891ab7ef15SShawn Guo port->both_edges |= 1 << gpio_idx; 190aeb27748SBenoît Thébaudeau } 191d37a65bbSShawn Guo break; 192d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_LOW: 193d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 194d37a65bbSShawn Guo break; 195d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_HIGH: 196d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 197d37a65bbSShawn Guo break; 198d37a65bbSShawn Guo default: 199d37a65bbSShawn Guo return -EINVAL; 200d37a65bbSShawn Guo } 201d37a65bbSShawn Guo 202*e5464277SMarek Vasut raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags); 203*e5464277SMarek Vasut 204aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 205aeb27748SBenoît Thébaudeau val = readl(port->base + GPIO_EDGE_SEL); 206aeb27748SBenoît Thébaudeau if (edge == GPIO_INT_BOTH_EDGES) 207f948ad07SLinus Torvalds writel(val | (1 << gpio_idx), 208aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 209aeb27748SBenoît Thébaudeau else 210f948ad07SLinus Torvalds writel(val & ~(1 << gpio_idx), 211aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 212aeb27748SBenoît Thébaudeau } 213aeb27748SBenoît Thébaudeau 214aeb27748SBenoît Thébaudeau if (edge != GPIO_INT_BOTH_EDGES) { 215f948ad07SLinus Torvalds reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ 2161ab7ef15SShawn Guo bit = gpio_idx & 0xf; 217b78d8e59SShawn Guo val = readl(reg) & ~(0x3 << (bit << 1)); 218b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 219aeb27748SBenoît Thébaudeau } 220aeb27748SBenoît Thébaudeau 2211ab7ef15SShawn Guo writel(1 << gpio_idx, port->base + GPIO_ISR); 222f60c9eacSShenwei Wang port->pad_type[gpio_idx] = type; 223d37a65bbSShawn Guo 224*e5464277SMarek Vasut raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); 225*e5464277SMarek Vasut 226d37a65bbSShawn Guo return 0; 227d37a65bbSShawn Guo } 228d37a65bbSShawn Guo 229d37a65bbSShawn Guo static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 230d37a65bbSShawn Guo { 231d37a65bbSShawn Guo void __iomem *reg = port->base; 232*e5464277SMarek Vasut unsigned long flags; 233d37a65bbSShawn Guo u32 bit, val; 234d37a65bbSShawn Guo int edge; 235d37a65bbSShawn Guo 236*e5464277SMarek Vasut raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags); 237*e5464277SMarek Vasut 238d37a65bbSShawn Guo reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 239d37a65bbSShawn Guo bit = gpio & 0xf; 240b78d8e59SShawn Guo val = readl(reg); 241d37a65bbSShawn Guo edge = (val >> (bit << 1)) & 3; 242d37a65bbSShawn Guo val &= ~(0x3 << (bit << 1)); 243d37a65bbSShawn Guo if (edge == GPIO_INT_HIGH_LEV) { 244d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 245d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 246d37a65bbSShawn Guo } else if (edge == GPIO_INT_LOW_LEV) { 247d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 248d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 249d37a65bbSShawn Guo } else { 250d37a65bbSShawn Guo pr_err("mxc: invalid configuration for GPIO %d: %x\n", 251d37a65bbSShawn Guo gpio, edge); 252d37a65bbSShawn Guo return; 253d37a65bbSShawn Guo } 254b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 255*e5464277SMarek Vasut 256*e5464277SMarek Vasut raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); 257d37a65bbSShawn Guo } 258d37a65bbSShawn Guo 259d37a65bbSShawn Guo /* handle 32 interrupts in one status register */ 260d37a65bbSShawn Guo static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 261d37a65bbSShawn Guo { 262d37a65bbSShawn Guo while (irq_stat != 0) { 263d37a65bbSShawn Guo int irqoffset = fls(irq_stat) - 1; 264d37a65bbSShawn Guo 265d37a65bbSShawn Guo if (port->both_edges & (1 << irqoffset)) 266d37a65bbSShawn Guo mxc_flip_edge(port, irqoffset); 267d37a65bbSShawn Guo 268dbd1c54fSMarc Zyngier generic_handle_domain_irq(port->domain, irqoffset); 269d37a65bbSShawn Guo 270d37a65bbSShawn Guo irq_stat &= ~(1 << irqoffset); 271d37a65bbSShawn Guo } 272d37a65bbSShawn Guo } 273d37a65bbSShawn Guo 274d37a65bbSShawn Guo /* MX1 and MX3 has one interrupt *per* gpio port */ 275bd0b9ac4SThomas Gleixner static void mx3_gpio_irq_handler(struct irq_desc *desc) 276d37a65bbSShawn Guo { 277d37a65bbSShawn Guo u32 irq_stat; 278476f8b4cSJiang Liu struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); 279476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 2800e44b6ecSShawn Guo 281f60c9eacSShenwei Wang if (port->is_pad_wakeup) 282f60c9eacSShenwei Wang return; 283f60c9eacSShenwei Wang 2840e44b6ecSShawn Guo chained_irq_enter(chip, desc); 285d37a65bbSShawn Guo 286b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 287d37a65bbSShawn Guo 288d37a65bbSShawn Guo mxc_gpio_irq_handler(port, irq_stat); 2890e44b6ecSShawn Guo 2900e44b6ecSShawn Guo chained_irq_exit(chip, desc); 291d37a65bbSShawn Guo } 292d37a65bbSShawn Guo 293d37a65bbSShawn Guo /* MX2 has one interrupt *for all* gpio ports */ 294bd0b9ac4SThomas Gleixner static void mx2_gpio_irq_handler(struct irq_desc *desc) 295d37a65bbSShawn Guo { 296d37a65bbSShawn Guo u32 irq_msk, irq_stat; 297b78d8e59SShawn Guo struct mxc_gpio_port *port; 298476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 299c0e811d9SUwe Kleine-König 300c0e811d9SUwe Kleine-König chained_irq_enter(chip, desc); 301d37a65bbSShawn Guo 302d37a65bbSShawn Guo /* walk through all interrupt status registers */ 303b78d8e59SShawn Guo list_for_each_entry(port, &mxc_gpio_ports, node) { 304b78d8e59SShawn Guo irq_msk = readl(port->base + GPIO_IMR); 305d37a65bbSShawn Guo if (!irq_msk) 306d37a65bbSShawn Guo continue; 307d37a65bbSShawn Guo 308b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 309d37a65bbSShawn Guo if (irq_stat) 310b78d8e59SShawn Guo mxc_gpio_irq_handler(port, irq_stat); 311d37a65bbSShawn Guo } 312c0e811d9SUwe Kleine-König chained_irq_exit(chip, desc); 313d37a65bbSShawn Guo } 314d37a65bbSShawn Guo 315d37a65bbSShawn Guo /* 316d37a65bbSShawn Guo * Set interrupt number "irq" in the GPIO as a wake-up source. 317d37a65bbSShawn Guo * While system is running, all registered GPIO interrupts need to have 318d37a65bbSShawn Guo * wake-up enabled. When system is suspended, only selected GPIO interrupts 319d37a65bbSShawn Guo * need to have wake-up enabled. 320d37a65bbSShawn Guo * @param irq interrupt source number 321d37a65bbSShawn Guo * @param enable enable as wake-up if equal to non-zero 322d37a65bbSShawn Guo * @return This function returns 0 on success. 323d37a65bbSShawn Guo */ 324d37a65bbSShawn Guo static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 325d37a65bbSShawn Guo { 326e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 327e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 3281ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 32977a4d757SPhilipp Rosenberger int ret; 330d37a65bbSShawn Guo 331d37a65bbSShawn Guo if (enable) { 332d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 33377a4d757SPhilipp Rosenberger ret = enable_irq_wake(port->irq_high); 334d37a65bbSShawn Guo else 33577a4d757SPhilipp Rosenberger ret = enable_irq_wake(port->irq); 336f60c9eacSShenwei Wang port->wakeup_pads |= (1 << gpio_idx); 337d37a65bbSShawn Guo } else { 338d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 33977a4d757SPhilipp Rosenberger ret = disable_irq_wake(port->irq_high); 340d37a65bbSShawn Guo else 34177a4d757SPhilipp Rosenberger ret = disable_irq_wake(port->irq); 342f60c9eacSShenwei Wang port->wakeup_pads &= ~(1 << gpio_idx); 343d37a65bbSShawn Guo } 344d37a65bbSShawn Guo 34577a4d757SPhilipp Rosenberger return ret; 346d37a65bbSShawn Guo } 347d37a65bbSShawn Guo 3489e26b0b1SPeng Fan static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) 349e4ea9333SShawn Guo { 350e4ea9333SShawn Guo struct irq_chip_generic *gc; 351e4ea9333SShawn Guo struct irq_chip_type *ct; 352db5270acSBartosz Golaszewski int rv; 353d37a65bbSShawn Guo 354db5270acSBartosz Golaszewski gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base, 355e4ea9333SShawn Guo port->base, handle_level_irq); 3569e26b0b1SPeng Fan if (!gc) 3579e26b0b1SPeng Fan return -ENOMEM; 358e4ea9333SShawn Guo gc->private = port; 359e4ea9333SShawn Guo 360e4ea9333SShawn Guo ct = gc->chip_types; 361591567a5SShawn Guo ct->chip.irq_ack = irq_gc_ack_set_bit; 362e4ea9333SShawn Guo ct->chip.irq_mask = irq_gc_mask_clr_bit; 363e4ea9333SShawn Guo ct->chip.irq_unmask = irq_gc_mask_set_bit; 364e4ea9333SShawn Guo ct->chip.irq_set_type = gpio_set_irq_type; 365591567a5SShawn Guo ct->chip.irq_set_wake = gpio_set_wake_irq; 3663093e6ccSLoic Poulain ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND; 367e4ea9333SShawn Guo ct->regs.ack = GPIO_ISR; 368e4ea9333SShawn Guo ct->regs.mask = GPIO_IMR; 369e4ea9333SShawn Guo 370db5270acSBartosz Golaszewski rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), 371db5270acSBartosz Golaszewski IRQ_GC_INIT_NESTED_LOCK, 372e4ea9333SShawn Guo IRQ_NOREQUEST, 0); 3739e26b0b1SPeng Fan 374db5270acSBartosz Golaszewski return rv; 375e4ea9333SShawn Guo } 376d37a65bbSShawn Guo 37709ad8039SShawn Guo static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 37809ad8039SShawn Guo { 3790f4630f3SLinus Walleij struct mxc_gpio_port *port = gpiochip_get_data(gc); 38009ad8039SShawn Guo 3811ab7ef15SShawn Guo return irq_find_mapping(port->domain, offset); 38209ad8039SShawn Guo } 38309ad8039SShawn Guo 3843836309dSBill Pemberton static int mxc_gpio_probe(struct platform_device *pdev) 385d37a65bbSShawn Guo { 3868937cb60SShawn Guo struct device_node *np = pdev->dev.of_node; 387b78d8e59SShawn Guo struct mxc_gpio_port *port; 388c8f3d144SAnson Huang int irq_count; 3891ab7ef15SShawn Guo int irq_base; 390e4ea9333SShawn Guo int err; 391d37a65bbSShawn Guo 3928cd73e4eSFabio Estevam port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 393b78d8e59SShawn Guo if (!port) 394b78d8e59SShawn Guo return -ENOMEM; 395d37a65bbSShawn Guo 396db5270acSBartosz Golaszewski port->dev = &pdev->dev; 3970f2c7af4SFabio Estevam port->hwdata = device_get_match_data(&pdev->dev); 3980f2c7af4SFabio Estevam 399123ac0e5SEnrico Weigelt, metux IT consult port->base = devm_platform_ioremap_resource(pdev, 0); 4008cd73e4eSFabio Estevam if (IS_ERR(port->base)) 4018cd73e4eSFabio Estevam return PTR_ERR(port->base); 402b78d8e59SShawn Guo 403c8f3d144SAnson Huang irq_count = platform_irq_count(pdev); 404c8f3d144SAnson Huang if (irq_count < 0) 405c8f3d144SAnson Huang return irq_count; 406c8f3d144SAnson Huang 407c8f3d144SAnson Huang if (irq_count > 1) { 408b78d8e59SShawn Guo port->irq_high = platform_get_irq(pdev, 1); 409cc9269f8SPhilipp Rosenberger if (port->irq_high < 0) 410cc9269f8SPhilipp Rosenberger port->irq_high = 0; 411c8f3d144SAnson Huang } 412cc9269f8SPhilipp Rosenberger 413b78d8e59SShawn Guo port->irq = platform_get_irq(pdev, 0); 4148cd73e4eSFabio Estevam if (port->irq < 0) 4155ea80e49SSachin Kamat return port->irq; 416b78d8e59SShawn Guo 4172808801aSAnson Huang /* the controller clock is optional */ 4187beb620fSAnson Huang port->clk = devm_clk_get_optional(&pdev->dev, NULL); 4197beb620fSAnson Huang if (IS_ERR(port->clk)) 4207beb620fSAnson Huang return PTR_ERR(port->clk); 4212808801aSAnson Huang 4222808801aSAnson Huang err = clk_prepare_enable(port->clk); 4232808801aSAnson Huang if (err) { 4242808801aSAnson Huang dev_err(&pdev->dev, "Unable to enable clock.\n"); 4252808801aSAnson Huang return err; 4262808801aSAnson Huang } 4272808801aSAnson Huang 428c19fdaeeSAnson Huang if (of_device_is_compatible(np, "fsl,imx7d-gpio")) 429c19fdaeeSAnson Huang port->power_off = true; 430c19fdaeeSAnson Huang 431d37a65bbSShawn Guo /* disable the interrupt and clear the status */ 432b78d8e59SShawn Guo writel(0, port->base + GPIO_IMR); 433b78d8e59SShawn Guo writel(~0, port->base + GPIO_ISR); 434d37a65bbSShawn Guo 4350f2c7af4SFabio Estevam if (of_device_is_compatible(np, "fsl,imx21-gpio")) { 43633a4e985SUwe Kleine-König /* 43733a4e985SUwe Kleine-König * Setup one handler for all GPIO interrupts. Actually setting 43833a4e985SUwe Kleine-König * the handler is needed only once, but doing it for every port 43933a4e985SUwe Kleine-König * is more robust and easier. 44033a4e985SUwe Kleine-König */ 44133a4e985SUwe Kleine-König irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); 442b78d8e59SShawn Guo } else { 443b78d8e59SShawn Guo /* setup one handler for each entry */ 444e65eea54SRussell King irq_set_chained_handler_and_data(port->irq, 445e65eea54SRussell King mx3_gpio_irq_handler, port); 446e65eea54SRussell King if (port->irq_high > 0) 447b78d8e59SShawn Guo /* setup handler for GPIO 16 to 31 */ 448e65eea54SRussell King irq_set_chained_handler_and_data(port->irq_high, 449e65eea54SRussell King mx3_gpio_irq_handler, 450e65eea54SRussell King port); 451d37a65bbSShawn Guo } 452d37a65bbSShawn Guo 4530f4630f3SLinus Walleij err = bgpio_init(&port->gc, &pdev->dev, 4, 4542ce420daSShawn Guo port->base + GPIO_PSR, 4552ce420daSShawn Guo port->base + GPIO_DR, NULL, 456442b2494SVladimir Zapolskiy port->base + GPIO_GDIR, NULL, 457442b2494SVladimir Zapolskiy BGPIOF_READ_OUTPUT_REG_SET); 458b78d8e59SShawn Guo if (err) 4598cd73e4eSFabio Estevam goto out_bgio; 460b78d8e59SShawn Guo 4614c806c98SVladimir Zapolskiy port->gc.request = gpiochip_generic_request; 4624c806c98SVladimir Zapolskiy port->gc.free = gpiochip_generic_free; 4630f4630f3SLinus Walleij port->gc.to_irq = mxc_gpio_to_irq; 4640f4630f3SLinus Walleij port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : 4657e6086d9SShawn Guo pdev->id * 32; 4662ce420daSShawn Guo 467ffc56630SLaxman Dewangan err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port); 4682ce420daSShawn Guo if (err) 4690f4630f3SLinus Walleij goto out_bgio; 4702ce420daSShawn Guo 471c553c3c4SBartosz Golaszewski irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); 4721ab7ef15SShawn Guo if (irq_base < 0) { 4731ab7ef15SShawn Guo err = irq_base; 474ffc56630SLaxman Dewangan goto out_bgio; 4751ab7ef15SShawn Guo } 4761ab7ef15SShawn Guo 4771ab7ef15SShawn Guo port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, 4781ab7ef15SShawn Guo &irq_domain_simple_ops, NULL); 4791ab7ef15SShawn Guo if (!port->domain) { 4801ab7ef15SShawn Guo err = -ENODEV; 481c553c3c4SBartosz Golaszewski goto out_bgio; 4821ab7ef15SShawn Guo } 4838937cb60SShawn Guo 4848937cb60SShawn Guo /* gpio-mxc can be a generic irq chip */ 4859e26b0b1SPeng Fan err = mxc_gpio_init_gc(port, irq_base); 4869e26b0b1SPeng Fan if (err < 0) 4879e26b0b1SPeng Fan goto out_irqdomain_remove; 4888937cb60SShawn Guo 489b78d8e59SShawn Guo list_add_tail(&port->node, &mxc_gpio_ports); 490b78d8e59SShawn Guo 491c19fdaeeSAnson Huang platform_set_drvdata(pdev, port); 492c19fdaeeSAnson Huang 493d37a65bbSShawn Guo return 0; 494b78d8e59SShawn Guo 4959e26b0b1SPeng Fan out_irqdomain_remove: 4969e26b0b1SPeng Fan irq_domain_remove(port->domain); 4978cd73e4eSFabio Estevam out_bgio: 4982808801aSAnson Huang clk_disable_unprepare(port->clk); 499b78d8e59SShawn Guo dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 500b78d8e59SShawn Guo return err; 501d37a65bbSShawn Guo } 502b78d8e59SShawn Guo 503c19fdaeeSAnson Huang static void mxc_gpio_save_regs(struct mxc_gpio_port *port) 504c19fdaeeSAnson Huang { 505c19fdaeeSAnson Huang if (!port->power_off) 506c19fdaeeSAnson Huang return; 507c19fdaeeSAnson Huang 508c19fdaeeSAnson Huang port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1); 509c19fdaeeSAnson Huang port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2); 510c19fdaeeSAnson Huang port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR); 511c19fdaeeSAnson Huang port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR); 512c19fdaeeSAnson Huang port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL); 513c19fdaeeSAnson Huang port->gpio_saved_reg.dr = readl(port->base + GPIO_DR); 514c19fdaeeSAnson Huang } 515c19fdaeeSAnson Huang 516c19fdaeeSAnson Huang static void mxc_gpio_restore_regs(struct mxc_gpio_port *port) 517c19fdaeeSAnson Huang { 518c19fdaeeSAnson Huang if (!port->power_off) 519c19fdaeeSAnson Huang return; 520c19fdaeeSAnson Huang 521c19fdaeeSAnson Huang writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1); 522c19fdaeeSAnson Huang writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2); 523c19fdaeeSAnson Huang writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR); 524c19fdaeeSAnson Huang writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR); 525c19fdaeeSAnson Huang writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL); 526c19fdaeeSAnson Huang writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); 527c19fdaeeSAnson Huang } 528c19fdaeeSAnson Huang 529f60c9eacSShenwei Wang static bool mxc_gpio_generic_config(struct mxc_gpio_port *port, 530f60c9eacSShenwei Wang unsigned int offset, unsigned long conf) 531f60c9eacSShenwei Wang { 532f60c9eacSShenwei Wang struct device_node *np = port->dev->of_node; 533f60c9eacSShenwei Wang 534f60c9eacSShenwei Wang if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") || 535f60c9eacSShenwei Wang of_device_is_compatible(np, "fsl,imx8qxp-gpio") || 536f60c9eacSShenwei Wang of_device_is_compatible(np, "fsl,imx8qm-gpio")) 537f60c9eacSShenwei Wang return (gpiochip_generic_config(&port->gc, offset, conf) == 0); 538f60c9eacSShenwei Wang 539f60c9eacSShenwei Wang return false; 540f60c9eacSShenwei Wang } 541f60c9eacSShenwei Wang 542f60c9eacSShenwei Wang static bool mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable) 543f60c9eacSShenwei Wang { 544f60c9eacSShenwei Wang unsigned long config; 545f60c9eacSShenwei Wang bool ret = false; 546f60c9eacSShenwei Wang int i, type; 547f60c9eacSShenwei Wang 548f60c9eacSShenwei Wang static const u32 pad_type_map[] = { 549f60c9eacSShenwei Wang IMX_SCU_WAKEUP_OFF, /* 0 */ 550f60c9eacSShenwei Wang IMX_SCU_WAKEUP_RISE_EDGE, /* IRQ_TYPE_EDGE_RISING */ 551f60c9eacSShenwei Wang IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_FALLING */ 552f60c9eacSShenwei Wang IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_BOTH */ 553f60c9eacSShenwei Wang IMX_SCU_WAKEUP_HIGH_LVL, /* IRQ_TYPE_LEVEL_HIGH */ 554f60c9eacSShenwei Wang IMX_SCU_WAKEUP_OFF, /* 5 */ 555f60c9eacSShenwei Wang IMX_SCU_WAKEUP_OFF, /* 6 */ 556f60c9eacSShenwei Wang IMX_SCU_WAKEUP_OFF, /* 7 */ 557f60c9eacSShenwei Wang IMX_SCU_WAKEUP_LOW_LVL, /* IRQ_TYPE_LEVEL_LOW */ 558f60c9eacSShenwei Wang }; 559f60c9eacSShenwei Wang 560f60c9eacSShenwei Wang for (i = 0; i < 32; i++) { 561f60c9eacSShenwei Wang if ((port->wakeup_pads & (1 << i))) { 562f60c9eacSShenwei Wang type = port->pad_type[i]; 563f60c9eacSShenwei Wang if (enable) 564f60c9eacSShenwei Wang config = pad_type_map[type]; 565f60c9eacSShenwei Wang else 566f60c9eacSShenwei Wang config = IMX_SCU_WAKEUP_OFF; 567f60c9eacSShenwei Wang ret |= mxc_gpio_generic_config(port, i, config); 568f60c9eacSShenwei Wang } 569f60c9eacSShenwei Wang } 570f60c9eacSShenwei Wang 571f60c9eacSShenwei Wang return ret; 572f60c9eacSShenwei Wang } 573f60c9eacSShenwei Wang 574f60c9eacSShenwei Wang static int __maybe_unused mxc_gpio_noirq_suspend(struct device *dev) 575f60c9eacSShenwei Wang { 576f60c9eacSShenwei Wang struct platform_device *pdev = to_platform_device(dev); 577f60c9eacSShenwei Wang struct mxc_gpio_port *port = platform_get_drvdata(pdev); 578f60c9eacSShenwei Wang 579f60c9eacSShenwei Wang if (port->wakeup_pads > 0) 580f60c9eacSShenwei Wang port->is_pad_wakeup = mxc_gpio_set_pad_wakeup(port, true); 581f60c9eacSShenwei Wang 582f60c9eacSShenwei Wang return 0; 583f60c9eacSShenwei Wang } 584f60c9eacSShenwei Wang 585f60c9eacSShenwei Wang static int __maybe_unused mxc_gpio_noirq_resume(struct device *dev) 586f60c9eacSShenwei Wang { 587f60c9eacSShenwei Wang struct platform_device *pdev = to_platform_device(dev); 588f60c9eacSShenwei Wang struct mxc_gpio_port *port = platform_get_drvdata(pdev); 589f60c9eacSShenwei Wang 590f60c9eacSShenwei Wang if (port->wakeup_pads > 0) 591f60c9eacSShenwei Wang mxc_gpio_set_pad_wakeup(port, false); 592f60c9eacSShenwei Wang port->is_pad_wakeup = false; 593f60c9eacSShenwei Wang 594f60c9eacSShenwei Wang return 0; 595f60c9eacSShenwei Wang } 596f60c9eacSShenwei Wang 597f60c9eacSShenwei Wang static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { 598f60c9eacSShenwei Wang SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume) 599f60c9eacSShenwei Wang }; 600f60c9eacSShenwei Wang 6011a5287a3SAnson Huang static int mxc_gpio_syscore_suspend(void) 602c19fdaeeSAnson Huang { 6031a5287a3SAnson Huang struct mxc_gpio_port *port; 604c19fdaeeSAnson Huang 6051a5287a3SAnson Huang /* walk through all ports */ 6061a5287a3SAnson Huang list_for_each_entry(port, &mxc_gpio_ports, node) { 607c19fdaeeSAnson Huang mxc_gpio_save_regs(port); 608c19fdaeeSAnson Huang clk_disable_unprepare(port->clk); 6091a5287a3SAnson Huang } 610c19fdaeeSAnson Huang 611c19fdaeeSAnson Huang return 0; 612c19fdaeeSAnson Huang } 613c19fdaeeSAnson Huang 6141a5287a3SAnson Huang static void mxc_gpio_syscore_resume(void) 615c19fdaeeSAnson Huang { 6161a5287a3SAnson Huang struct mxc_gpio_port *port; 617c19fdaeeSAnson Huang int ret; 618c19fdaeeSAnson Huang 6191a5287a3SAnson Huang /* walk through all ports */ 6201a5287a3SAnson Huang list_for_each_entry(port, &mxc_gpio_ports, node) { 621c19fdaeeSAnson Huang ret = clk_prepare_enable(port->clk); 6221a5287a3SAnson Huang if (ret) { 6231a5287a3SAnson Huang pr_err("mxc: failed to enable gpio clock %d\n", ret); 6241a5287a3SAnson Huang return; 6251a5287a3SAnson Huang } 626c19fdaeeSAnson Huang mxc_gpio_restore_regs(port); 6271a5287a3SAnson Huang } 628c19fdaeeSAnson Huang } 629c19fdaeeSAnson Huang 6301a5287a3SAnson Huang static struct syscore_ops mxc_gpio_syscore_ops = { 6311a5287a3SAnson Huang .suspend = mxc_gpio_syscore_suspend, 6321a5287a3SAnson Huang .resume = mxc_gpio_syscore_resume, 633c19fdaeeSAnson Huang }; 634c19fdaeeSAnson Huang 635b78d8e59SShawn Guo static struct platform_driver mxc_gpio_driver = { 636b78d8e59SShawn Guo .driver = { 637b78d8e59SShawn Guo .name = "gpio-mxc", 6388937cb60SShawn Guo .of_match_table = mxc_gpio_dt_ids, 63990e1fc4cSBartosz Golaszewski .suppress_bind_attrs = true, 640f60c9eacSShenwei Wang .pm = &mxc_gpio_dev_pm_ops, 641b78d8e59SShawn Guo }, 642b78d8e59SShawn Guo .probe = mxc_gpio_probe, 643b78d8e59SShawn Guo }; 644b78d8e59SShawn Guo 645b78d8e59SShawn Guo static int __init gpio_mxc_init(void) 646b78d8e59SShawn Guo { 6471a5287a3SAnson Huang register_syscore_ops(&mxc_gpio_syscore_ops); 6481a5287a3SAnson Huang 649b78d8e59SShawn Guo return platform_driver_register(&mxc_gpio_driver); 650b78d8e59SShawn Guo } 651e188cbf7SVladimir Zapolskiy subsys_initcall(gpio_mxc_init); 65212d16b39SAnson Huang 65312d16b39SAnson Huang MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 65412d16b39SAnson Huang MODULE_DESCRIPTION("i.MX GPIO Driver"); 65512d16b39SAnson Huang MODULE_LICENSE("GPL"); 656