1014e420dSFabio Estevam // SPDX-License-Identifier: GPL-2.0+ 2014e420dSFabio Estevam // 3014e420dSFabio Estevam // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 4014e420dSFabio Estevam // Copyright 2008 Juergen Beisert, kernel@pengutronix.de 5014e420dSFabio Estevam // 6014e420dSFabio Estevam // Based on code from Freescale Semiconductor, 7014e420dSFabio Estevam // Authors: Daniel Mack, Juergen Beisert. 8014e420dSFabio Estevam // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9d37a65bbSShawn Guo 102808801aSAnson Huang #include <linux/clk.h> 1118f92b19SFabio Estevam #include <linux/err.h> 12d37a65bbSShawn Guo #include <linux/init.h> 13d37a65bbSShawn Guo #include <linux/interrupt.h> 14d37a65bbSShawn Guo #include <linux/io.h> 15d37a65bbSShawn Guo #include <linux/irq.h> 161ab7ef15SShawn Guo #include <linux/irqdomain.h> 17de88cbb7SCatalin Marinas #include <linux/irqchip/chained_irq.h> 1812d16b39SAnson Huang #include <linux/module.h> 19b78d8e59SShawn Guo #include <linux/platform_device.h> 20b78d8e59SShawn Guo #include <linux/slab.h> 211a5287a3SAnson Huang #include <linux/syscore_ops.h> 220f4630f3SLinus Walleij #include <linux/gpio/driver.h> 238937cb60SShawn Guo #include <linux/of.h> 248937cb60SShawn Guo #include <linux/of_device.h> 2516c3bd35SChristoph Hellwig #include <linux/bug.h> 26d37a65bbSShawn Guo 27e7fc6ae7SShawn Guo /* device type dependent stuff */ 28e7fc6ae7SShawn Guo struct mxc_gpio_hwdata { 29e7fc6ae7SShawn Guo unsigned dr_reg; 30e7fc6ae7SShawn Guo unsigned gdir_reg; 31e7fc6ae7SShawn Guo unsigned psr_reg; 32e7fc6ae7SShawn Guo unsigned icr1_reg; 33e7fc6ae7SShawn Guo unsigned icr2_reg; 34e7fc6ae7SShawn Guo unsigned imr_reg; 35e7fc6ae7SShawn Guo unsigned isr_reg; 36aeb27748SBenoît Thébaudeau int edge_sel_reg; 37e7fc6ae7SShawn Guo unsigned low_level; 38e7fc6ae7SShawn Guo unsigned high_level; 39e7fc6ae7SShawn Guo unsigned rise_edge; 40e7fc6ae7SShawn Guo unsigned fall_edge; 41e7fc6ae7SShawn Guo }; 42e7fc6ae7SShawn Guo 43c19fdaeeSAnson Huang struct mxc_gpio_reg_saved { 44c19fdaeeSAnson Huang u32 icr1; 45c19fdaeeSAnson Huang u32 icr2; 46c19fdaeeSAnson Huang u32 imr; 47c19fdaeeSAnson Huang u32 gdir; 48c19fdaeeSAnson Huang u32 edge_sel; 49c19fdaeeSAnson Huang u32 dr; 50c19fdaeeSAnson Huang }; 51c19fdaeeSAnson Huang 52b78d8e59SShawn Guo struct mxc_gpio_port { 53b78d8e59SShawn Guo struct list_head node; 54b78d8e59SShawn Guo void __iomem *base; 552808801aSAnson Huang struct clk *clk; 56b78d8e59SShawn Guo int irq; 57b78d8e59SShawn Guo int irq_high; 581ab7ef15SShawn Guo struct irq_domain *domain; 590f4630f3SLinus Walleij struct gpio_chip gc; 60db5270acSBartosz Golaszewski struct device *dev; 61b78d8e59SShawn Guo u32 both_edges; 62c19fdaeeSAnson Huang struct mxc_gpio_reg_saved gpio_saved_reg; 63c19fdaeeSAnson Huang bool power_off; 640f2c7af4SFabio Estevam const struct mxc_gpio_hwdata *hwdata; 65b78d8e59SShawn Guo }; 66b78d8e59SShawn Guo 67e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 68e7fc6ae7SShawn Guo .dr_reg = 0x1c, 69e7fc6ae7SShawn Guo .gdir_reg = 0x00, 70e7fc6ae7SShawn Guo .psr_reg = 0x24, 71e7fc6ae7SShawn Guo .icr1_reg = 0x28, 72e7fc6ae7SShawn Guo .icr2_reg = 0x2c, 73e7fc6ae7SShawn Guo .imr_reg = 0x30, 74e7fc6ae7SShawn Guo .isr_reg = 0x34, 75aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 76e7fc6ae7SShawn Guo .low_level = 0x03, 77e7fc6ae7SShawn Guo .high_level = 0x02, 78e7fc6ae7SShawn Guo .rise_edge = 0x00, 79e7fc6ae7SShawn Guo .fall_edge = 0x01, 80e7fc6ae7SShawn Guo }; 81e7fc6ae7SShawn Guo 82e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 83e7fc6ae7SShawn Guo .dr_reg = 0x00, 84e7fc6ae7SShawn Guo .gdir_reg = 0x04, 85e7fc6ae7SShawn Guo .psr_reg = 0x08, 86e7fc6ae7SShawn Guo .icr1_reg = 0x0c, 87e7fc6ae7SShawn Guo .icr2_reg = 0x10, 88e7fc6ae7SShawn Guo .imr_reg = 0x14, 89e7fc6ae7SShawn Guo .isr_reg = 0x18, 90aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 91aeb27748SBenoît Thébaudeau .low_level = 0x00, 92aeb27748SBenoît Thébaudeau .high_level = 0x01, 93aeb27748SBenoît Thébaudeau .rise_edge = 0x02, 94aeb27748SBenoît Thébaudeau .fall_edge = 0x03, 95aeb27748SBenoît Thébaudeau }; 96aeb27748SBenoît Thébaudeau 97aeb27748SBenoît Thébaudeau static struct mxc_gpio_hwdata imx35_gpio_hwdata = { 98aeb27748SBenoît Thébaudeau .dr_reg = 0x00, 99aeb27748SBenoît Thébaudeau .gdir_reg = 0x04, 100aeb27748SBenoît Thébaudeau .psr_reg = 0x08, 101aeb27748SBenoît Thébaudeau .icr1_reg = 0x0c, 102aeb27748SBenoît Thébaudeau .icr2_reg = 0x10, 103aeb27748SBenoît Thébaudeau .imr_reg = 0x14, 104aeb27748SBenoît Thébaudeau .isr_reg = 0x18, 105aeb27748SBenoît Thébaudeau .edge_sel_reg = 0x1c, 106e7fc6ae7SShawn Guo .low_level = 0x00, 107e7fc6ae7SShawn Guo .high_level = 0x01, 108e7fc6ae7SShawn Guo .rise_edge = 0x02, 109e7fc6ae7SShawn Guo .fall_edge = 0x03, 110e7fc6ae7SShawn Guo }; 111e7fc6ae7SShawn Guo 1120f2c7af4SFabio Estevam #define GPIO_DR (port->hwdata->dr_reg) 1130f2c7af4SFabio Estevam #define GPIO_GDIR (port->hwdata->gdir_reg) 1140f2c7af4SFabio Estevam #define GPIO_PSR (port->hwdata->psr_reg) 1150f2c7af4SFabio Estevam #define GPIO_ICR1 (port->hwdata->icr1_reg) 1160f2c7af4SFabio Estevam #define GPIO_ICR2 (port->hwdata->icr2_reg) 1170f2c7af4SFabio Estevam #define GPIO_IMR (port->hwdata->imr_reg) 1180f2c7af4SFabio Estevam #define GPIO_ISR (port->hwdata->isr_reg) 1190f2c7af4SFabio Estevam #define GPIO_EDGE_SEL (port->hwdata->edge_sel_reg) 120e7fc6ae7SShawn Guo 1210f2c7af4SFabio Estevam #define GPIO_INT_LOW_LEV (port->hwdata->low_level) 1220f2c7af4SFabio Estevam #define GPIO_INT_HIGH_LEV (port->hwdata->high_level) 1230f2c7af4SFabio Estevam #define GPIO_INT_RISE_EDGE (port->hwdata->rise_edge) 1240f2c7af4SFabio Estevam #define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge) 125aeb27748SBenoît Thébaudeau #define GPIO_INT_BOTH_EDGES 0x4 126e7fc6ae7SShawn Guo 1278937cb60SShawn Guo static const struct of_device_id mxc_gpio_dt_ids[] = { 1280f2c7af4SFabio Estevam { .compatible = "fsl,imx1-gpio", .data = &imx1_imx21_gpio_hwdata }, 1290f2c7af4SFabio Estevam { .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata }, 1300f2c7af4SFabio Estevam { .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata }, 1310f2c7af4SFabio Estevam { .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata }, 1320f2c7af4SFabio Estevam { .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata }, 1338937cb60SShawn Guo { /* sentinel */ } 1348937cb60SShawn Guo }; 13512d16b39SAnson Huang MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids); 1368937cb60SShawn Guo 137b78d8e59SShawn Guo /* 138b78d8e59SShawn Guo * MX2 has one interrupt *for all* gpio ports. The list is used 139b78d8e59SShawn Guo * to save the references to all ports, so that mx2_gpio_irq_handler 140b78d8e59SShawn Guo * can walk through all interrupt status registers. 141b78d8e59SShawn Guo */ 142b78d8e59SShawn Guo static LIST_HEAD(mxc_gpio_ports); 143d37a65bbSShawn Guo 144d37a65bbSShawn Guo /* Note: This driver assumes 32 GPIOs are handled in one register */ 145d37a65bbSShawn Guo 146d37a65bbSShawn Guo static int gpio_set_irq_type(struct irq_data *d, u32 type) 147d37a65bbSShawn Guo { 148e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 149e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 150d37a65bbSShawn Guo u32 bit, val; 1511ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 152d37a65bbSShawn Guo int edge; 153d37a65bbSShawn Guo void __iomem *reg = port->base; 154d37a65bbSShawn Guo 1551ab7ef15SShawn Guo port->both_edges &= ~(1 << gpio_idx); 156d37a65bbSShawn Guo switch (type) { 157d37a65bbSShawn Guo case IRQ_TYPE_EDGE_RISING: 158d37a65bbSShawn Guo edge = GPIO_INT_RISE_EDGE; 159d37a65bbSShawn Guo break; 160d37a65bbSShawn Guo case IRQ_TYPE_EDGE_FALLING: 161d37a65bbSShawn Guo edge = GPIO_INT_FALL_EDGE; 162d37a65bbSShawn Guo break; 163d37a65bbSShawn Guo case IRQ_TYPE_EDGE_BOTH: 164aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 165aeb27748SBenoît Thébaudeau edge = GPIO_INT_BOTH_EDGES; 166aeb27748SBenoît Thébaudeau } else { 1678d0bd9a5SLinus Walleij val = port->gc.get(&port->gc, gpio_idx); 168d37a65bbSShawn Guo if (val) { 169d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 1708d0bd9a5SLinus Walleij pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx); 171d37a65bbSShawn Guo } else { 172d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 1738d0bd9a5SLinus Walleij pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx); 174d37a65bbSShawn Guo } 1751ab7ef15SShawn Guo port->both_edges |= 1 << gpio_idx; 176aeb27748SBenoît Thébaudeau } 177d37a65bbSShawn Guo break; 178d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_LOW: 179d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 180d37a65bbSShawn Guo break; 181d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_HIGH: 182d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 183d37a65bbSShawn Guo break; 184d37a65bbSShawn Guo default: 185d37a65bbSShawn Guo return -EINVAL; 186d37a65bbSShawn Guo } 187d37a65bbSShawn Guo 188aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 189aeb27748SBenoît Thébaudeau val = readl(port->base + GPIO_EDGE_SEL); 190aeb27748SBenoît Thébaudeau if (edge == GPIO_INT_BOTH_EDGES) 191f948ad07SLinus Torvalds writel(val | (1 << gpio_idx), 192aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 193aeb27748SBenoît Thébaudeau else 194f948ad07SLinus Torvalds writel(val & ~(1 << gpio_idx), 195aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 196aeb27748SBenoît Thébaudeau } 197aeb27748SBenoît Thébaudeau 198aeb27748SBenoît Thébaudeau if (edge != GPIO_INT_BOTH_EDGES) { 199f948ad07SLinus Torvalds reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ 2001ab7ef15SShawn Guo bit = gpio_idx & 0xf; 201b78d8e59SShawn Guo val = readl(reg) & ~(0x3 << (bit << 1)); 202b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 203aeb27748SBenoît Thébaudeau } 204aeb27748SBenoît Thébaudeau 2051ab7ef15SShawn Guo writel(1 << gpio_idx, port->base + GPIO_ISR); 206d37a65bbSShawn Guo 207d37a65bbSShawn Guo return 0; 208d37a65bbSShawn Guo } 209d37a65bbSShawn Guo 210d37a65bbSShawn Guo static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 211d37a65bbSShawn Guo { 212d37a65bbSShawn Guo void __iomem *reg = port->base; 213d37a65bbSShawn Guo u32 bit, val; 214d37a65bbSShawn Guo int edge; 215d37a65bbSShawn Guo 216d37a65bbSShawn Guo reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 217d37a65bbSShawn Guo bit = gpio & 0xf; 218b78d8e59SShawn Guo val = readl(reg); 219d37a65bbSShawn Guo edge = (val >> (bit << 1)) & 3; 220d37a65bbSShawn Guo val &= ~(0x3 << (bit << 1)); 221d37a65bbSShawn Guo if (edge == GPIO_INT_HIGH_LEV) { 222d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 223d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 224d37a65bbSShawn Guo } else if (edge == GPIO_INT_LOW_LEV) { 225d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 226d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 227d37a65bbSShawn Guo } else { 228d37a65bbSShawn Guo pr_err("mxc: invalid configuration for GPIO %d: %x\n", 229d37a65bbSShawn Guo gpio, edge); 230d37a65bbSShawn Guo return; 231d37a65bbSShawn Guo } 232b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 233d37a65bbSShawn Guo } 234d37a65bbSShawn Guo 235d37a65bbSShawn Guo /* handle 32 interrupts in one status register */ 236d37a65bbSShawn Guo static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 237d37a65bbSShawn Guo { 238d37a65bbSShawn Guo while (irq_stat != 0) { 239d37a65bbSShawn Guo int irqoffset = fls(irq_stat) - 1; 240d37a65bbSShawn Guo 241d37a65bbSShawn Guo if (port->both_edges & (1 << irqoffset)) 242d37a65bbSShawn Guo mxc_flip_edge(port, irqoffset); 243d37a65bbSShawn Guo 244*dbd1c54fSMarc Zyngier generic_handle_domain_irq(port->domain, irqoffset); 245d37a65bbSShawn Guo 246d37a65bbSShawn Guo irq_stat &= ~(1 << irqoffset); 247d37a65bbSShawn Guo } 248d37a65bbSShawn Guo } 249d37a65bbSShawn Guo 250d37a65bbSShawn Guo /* MX1 and MX3 has one interrupt *per* gpio port */ 251bd0b9ac4SThomas Gleixner static void mx3_gpio_irq_handler(struct irq_desc *desc) 252d37a65bbSShawn Guo { 253d37a65bbSShawn Guo u32 irq_stat; 254476f8b4cSJiang Liu struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); 255476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 2560e44b6ecSShawn Guo 2570e44b6ecSShawn Guo chained_irq_enter(chip, desc); 258d37a65bbSShawn Guo 259b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 260d37a65bbSShawn Guo 261d37a65bbSShawn Guo mxc_gpio_irq_handler(port, irq_stat); 2620e44b6ecSShawn Guo 2630e44b6ecSShawn Guo chained_irq_exit(chip, desc); 264d37a65bbSShawn Guo } 265d37a65bbSShawn Guo 266d37a65bbSShawn Guo /* MX2 has one interrupt *for all* gpio ports */ 267bd0b9ac4SThomas Gleixner static void mx2_gpio_irq_handler(struct irq_desc *desc) 268d37a65bbSShawn Guo { 269d37a65bbSShawn Guo u32 irq_msk, irq_stat; 270b78d8e59SShawn Guo struct mxc_gpio_port *port; 271476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 272c0e811d9SUwe Kleine-König 273c0e811d9SUwe Kleine-König chained_irq_enter(chip, desc); 274d37a65bbSShawn Guo 275d37a65bbSShawn Guo /* walk through all interrupt status registers */ 276b78d8e59SShawn Guo list_for_each_entry(port, &mxc_gpio_ports, node) { 277b78d8e59SShawn Guo irq_msk = readl(port->base + GPIO_IMR); 278d37a65bbSShawn Guo if (!irq_msk) 279d37a65bbSShawn Guo continue; 280d37a65bbSShawn Guo 281b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 282d37a65bbSShawn Guo if (irq_stat) 283b78d8e59SShawn Guo mxc_gpio_irq_handler(port, irq_stat); 284d37a65bbSShawn Guo } 285c0e811d9SUwe Kleine-König chained_irq_exit(chip, desc); 286d37a65bbSShawn Guo } 287d37a65bbSShawn Guo 288d37a65bbSShawn Guo /* 289d37a65bbSShawn Guo * Set interrupt number "irq" in the GPIO as a wake-up source. 290d37a65bbSShawn Guo * While system is running, all registered GPIO interrupts need to have 291d37a65bbSShawn Guo * wake-up enabled. When system is suspended, only selected GPIO interrupts 292d37a65bbSShawn Guo * need to have wake-up enabled. 293d37a65bbSShawn Guo * @param irq interrupt source number 294d37a65bbSShawn Guo * @param enable enable as wake-up if equal to non-zero 295d37a65bbSShawn Guo * @return This function returns 0 on success. 296d37a65bbSShawn Guo */ 297d37a65bbSShawn Guo static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 298d37a65bbSShawn Guo { 299e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 300e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 3011ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 30277a4d757SPhilipp Rosenberger int ret; 303d37a65bbSShawn Guo 304d37a65bbSShawn Guo if (enable) { 305d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 30677a4d757SPhilipp Rosenberger ret = enable_irq_wake(port->irq_high); 307d37a65bbSShawn Guo else 30877a4d757SPhilipp Rosenberger ret = enable_irq_wake(port->irq); 309d37a65bbSShawn Guo } else { 310d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 31177a4d757SPhilipp Rosenberger ret = disable_irq_wake(port->irq_high); 312d37a65bbSShawn Guo else 31377a4d757SPhilipp Rosenberger ret = disable_irq_wake(port->irq); 314d37a65bbSShawn Guo } 315d37a65bbSShawn Guo 31677a4d757SPhilipp Rosenberger return ret; 317d37a65bbSShawn Guo } 318d37a65bbSShawn Guo 3199e26b0b1SPeng Fan static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) 320e4ea9333SShawn Guo { 321e4ea9333SShawn Guo struct irq_chip_generic *gc; 322e4ea9333SShawn Guo struct irq_chip_type *ct; 323db5270acSBartosz Golaszewski int rv; 324d37a65bbSShawn Guo 325db5270acSBartosz Golaszewski gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base, 326e4ea9333SShawn Guo port->base, handle_level_irq); 3279e26b0b1SPeng Fan if (!gc) 3289e26b0b1SPeng Fan return -ENOMEM; 329e4ea9333SShawn Guo gc->private = port; 330e4ea9333SShawn Guo 331e4ea9333SShawn Guo ct = gc->chip_types; 332591567a5SShawn Guo ct->chip.irq_ack = irq_gc_ack_set_bit; 333e4ea9333SShawn Guo ct->chip.irq_mask = irq_gc_mask_clr_bit; 334e4ea9333SShawn Guo ct->chip.irq_unmask = irq_gc_mask_set_bit; 335e4ea9333SShawn Guo ct->chip.irq_set_type = gpio_set_irq_type; 336591567a5SShawn Guo ct->chip.irq_set_wake = gpio_set_wake_irq; 3373093e6ccSLoic Poulain ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND; 338e4ea9333SShawn Guo ct->regs.ack = GPIO_ISR; 339e4ea9333SShawn Guo ct->regs.mask = GPIO_IMR; 340e4ea9333SShawn Guo 341db5270acSBartosz Golaszewski rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), 342db5270acSBartosz Golaszewski IRQ_GC_INIT_NESTED_LOCK, 343e4ea9333SShawn Guo IRQ_NOREQUEST, 0); 3449e26b0b1SPeng Fan 345db5270acSBartosz Golaszewski return rv; 346e4ea9333SShawn Guo } 347d37a65bbSShawn Guo 34809ad8039SShawn Guo static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 34909ad8039SShawn Guo { 3500f4630f3SLinus Walleij struct mxc_gpio_port *port = gpiochip_get_data(gc); 35109ad8039SShawn Guo 3521ab7ef15SShawn Guo return irq_find_mapping(port->domain, offset); 35309ad8039SShawn Guo } 35409ad8039SShawn Guo 3553836309dSBill Pemberton static int mxc_gpio_probe(struct platform_device *pdev) 356d37a65bbSShawn Guo { 3578937cb60SShawn Guo struct device_node *np = pdev->dev.of_node; 358b78d8e59SShawn Guo struct mxc_gpio_port *port; 359c8f3d144SAnson Huang int irq_count; 3601ab7ef15SShawn Guo int irq_base; 361e4ea9333SShawn Guo int err; 362d37a65bbSShawn Guo 3638cd73e4eSFabio Estevam port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 364b78d8e59SShawn Guo if (!port) 365b78d8e59SShawn Guo return -ENOMEM; 366d37a65bbSShawn Guo 367db5270acSBartosz Golaszewski port->dev = &pdev->dev; 368db5270acSBartosz Golaszewski 3690f2c7af4SFabio Estevam port->hwdata = device_get_match_data(&pdev->dev); 3700f2c7af4SFabio Estevam 371123ac0e5SEnrico Weigelt, metux IT consult port->base = devm_platform_ioremap_resource(pdev, 0); 3728cd73e4eSFabio Estevam if (IS_ERR(port->base)) 3738cd73e4eSFabio Estevam return PTR_ERR(port->base); 374b78d8e59SShawn Guo 375c8f3d144SAnson Huang irq_count = platform_irq_count(pdev); 376c8f3d144SAnson Huang if (irq_count < 0) 377c8f3d144SAnson Huang return irq_count; 378c8f3d144SAnson Huang 379c8f3d144SAnson Huang if (irq_count > 1) { 380b78d8e59SShawn Guo port->irq_high = platform_get_irq(pdev, 1); 381cc9269f8SPhilipp Rosenberger if (port->irq_high < 0) 382cc9269f8SPhilipp Rosenberger port->irq_high = 0; 383c8f3d144SAnson Huang } 384cc9269f8SPhilipp Rosenberger 385b78d8e59SShawn Guo port->irq = platform_get_irq(pdev, 0); 3868cd73e4eSFabio Estevam if (port->irq < 0) 3875ea80e49SSachin Kamat return port->irq; 388b78d8e59SShawn Guo 3892808801aSAnson Huang /* the controller clock is optional */ 3907beb620fSAnson Huang port->clk = devm_clk_get_optional(&pdev->dev, NULL); 3917beb620fSAnson Huang if (IS_ERR(port->clk)) 3927beb620fSAnson Huang return PTR_ERR(port->clk); 3932808801aSAnson Huang 3942808801aSAnson Huang err = clk_prepare_enable(port->clk); 3952808801aSAnson Huang if (err) { 3962808801aSAnson Huang dev_err(&pdev->dev, "Unable to enable clock.\n"); 3972808801aSAnson Huang return err; 3982808801aSAnson Huang } 3992808801aSAnson Huang 400c19fdaeeSAnson Huang if (of_device_is_compatible(np, "fsl,imx7d-gpio")) 401c19fdaeeSAnson Huang port->power_off = true; 402c19fdaeeSAnson Huang 403d37a65bbSShawn Guo /* disable the interrupt and clear the status */ 404b78d8e59SShawn Guo writel(0, port->base + GPIO_IMR); 405b78d8e59SShawn Guo writel(~0, port->base + GPIO_ISR); 406d37a65bbSShawn Guo 4070f2c7af4SFabio Estevam if (of_device_is_compatible(np, "fsl,imx21-gpio")) { 40833a4e985SUwe Kleine-König /* 40933a4e985SUwe Kleine-König * Setup one handler for all GPIO interrupts. Actually setting 41033a4e985SUwe Kleine-König * the handler is needed only once, but doing it for every port 41133a4e985SUwe Kleine-König * is more robust and easier. 41233a4e985SUwe Kleine-König */ 41333a4e985SUwe Kleine-König irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); 414b78d8e59SShawn Guo } else { 415b78d8e59SShawn Guo /* setup one handler for each entry */ 416e65eea54SRussell King irq_set_chained_handler_and_data(port->irq, 417e65eea54SRussell King mx3_gpio_irq_handler, port); 418e65eea54SRussell King if (port->irq_high > 0) 419b78d8e59SShawn Guo /* setup handler for GPIO 16 to 31 */ 420e65eea54SRussell King irq_set_chained_handler_and_data(port->irq_high, 421e65eea54SRussell King mx3_gpio_irq_handler, 422e65eea54SRussell King port); 423d37a65bbSShawn Guo } 424d37a65bbSShawn Guo 4250f4630f3SLinus Walleij err = bgpio_init(&port->gc, &pdev->dev, 4, 4262ce420daSShawn Guo port->base + GPIO_PSR, 4272ce420daSShawn Guo port->base + GPIO_DR, NULL, 428442b2494SVladimir Zapolskiy port->base + GPIO_GDIR, NULL, 429442b2494SVladimir Zapolskiy BGPIOF_READ_OUTPUT_REG_SET); 430b78d8e59SShawn Guo if (err) 4318cd73e4eSFabio Estevam goto out_bgio; 432b78d8e59SShawn Guo 4334c806c98SVladimir Zapolskiy port->gc.request = gpiochip_generic_request; 4344c806c98SVladimir Zapolskiy port->gc.free = gpiochip_generic_free; 4350f4630f3SLinus Walleij port->gc.to_irq = mxc_gpio_to_irq; 4360f4630f3SLinus Walleij port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : 4377e6086d9SShawn Guo pdev->id * 32; 4382ce420daSShawn Guo 439ffc56630SLaxman Dewangan err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port); 4402ce420daSShawn Guo if (err) 4410f4630f3SLinus Walleij goto out_bgio; 4422ce420daSShawn Guo 443c553c3c4SBartosz Golaszewski irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); 4441ab7ef15SShawn Guo if (irq_base < 0) { 4451ab7ef15SShawn Guo err = irq_base; 446ffc56630SLaxman Dewangan goto out_bgio; 4471ab7ef15SShawn Guo } 4481ab7ef15SShawn Guo 4491ab7ef15SShawn Guo port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, 4501ab7ef15SShawn Guo &irq_domain_simple_ops, NULL); 4511ab7ef15SShawn Guo if (!port->domain) { 4521ab7ef15SShawn Guo err = -ENODEV; 453c553c3c4SBartosz Golaszewski goto out_bgio; 4541ab7ef15SShawn Guo } 4558937cb60SShawn Guo 4568937cb60SShawn Guo /* gpio-mxc can be a generic irq chip */ 4579e26b0b1SPeng Fan err = mxc_gpio_init_gc(port, irq_base); 4589e26b0b1SPeng Fan if (err < 0) 4599e26b0b1SPeng Fan goto out_irqdomain_remove; 4608937cb60SShawn Guo 461b78d8e59SShawn Guo list_add_tail(&port->node, &mxc_gpio_ports); 462b78d8e59SShawn Guo 463c19fdaeeSAnson Huang platform_set_drvdata(pdev, port); 464c19fdaeeSAnson Huang 465d37a65bbSShawn Guo return 0; 466b78d8e59SShawn Guo 4679e26b0b1SPeng Fan out_irqdomain_remove: 4689e26b0b1SPeng Fan irq_domain_remove(port->domain); 4698cd73e4eSFabio Estevam out_bgio: 4702808801aSAnson Huang clk_disable_unprepare(port->clk); 471b78d8e59SShawn Guo dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 472b78d8e59SShawn Guo return err; 473d37a65bbSShawn Guo } 474b78d8e59SShawn Guo 475c19fdaeeSAnson Huang static void mxc_gpio_save_regs(struct mxc_gpio_port *port) 476c19fdaeeSAnson Huang { 477c19fdaeeSAnson Huang if (!port->power_off) 478c19fdaeeSAnson Huang return; 479c19fdaeeSAnson Huang 480c19fdaeeSAnson Huang port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1); 481c19fdaeeSAnson Huang port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2); 482c19fdaeeSAnson Huang port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR); 483c19fdaeeSAnson Huang port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR); 484c19fdaeeSAnson Huang port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL); 485c19fdaeeSAnson Huang port->gpio_saved_reg.dr = readl(port->base + GPIO_DR); 486c19fdaeeSAnson Huang } 487c19fdaeeSAnson Huang 488c19fdaeeSAnson Huang static void mxc_gpio_restore_regs(struct mxc_gpio_port *port) 489c19fdaeeSAnson Huang { 490c19fdaeeSAnson Huang if (!port->power_off) 491c19fdaeeSAnson Huang return; 492c19fdaeeSAnson Huang 493c19fdaeeSAnson Huang writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1); 494c19fdaeeSAnson Huang writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2); 495c19fdaeeSAnson Huang writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR); 496c19fdaeeSAnson Huang writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR); 497c19fdaeeSAnson Huang writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL); 498c19fdaeeSAnson Huang writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); 499c19fdaeeSAnson Huang } 500c19fdaeeSAnson Huang 5011a5287a3SAnson Huang static int mxc_gpio_syscore_suspend(void) 502c19fdaeeSAnson Huang { 5031a5287a3SAnson Huang struct mxc_gpio_port *port; 504c19fdaeeSAnson Huang 5051a5287a3SAnson Huang /* walk through all ports */ 5061a5287a3SAnson Huang list_for_each_entry(port, &mxc_gpio_ports, node) { 507c19fdaeeSAnson Huang mxc_gpio_save_regs(port); 508c19fdaeeSAnson Huang clk_disable_unprepare(port->clk); 5091a5287a3SAnson Huang } 510c19fdaeeSAnson Huang 511c19fdaeeSAnson Huang return 0; 512c19fdaeeSAnson Huang } 513c19fdaeeSAnson Huang 5141a5287a3SAnson Huang static void mxc_gpio_syscore_resume(void) 515c19fdaeeSAnson Huang { 5161a5287a3SAnson Huang struct mxc_gpio_port *port; 517c19fdaeeSAnson Huang int ret; 518c19fdaeeSAnson Huang 5191a5287a3SAnson Huang /* walk through all ports */ 5201a5287a3SAnson Huang list_for_each_entry(port, &mxc_gpio_ports, node) { 521c19fdaeeSAnson Huang ret = clk_prepare_enable(port->clk); 5221a5287a3SAnson Huang if (ret) { 5231a5287a3SAnson Huang pr_err("mxc: failed to enable gpio clock %d\n", ret); 5241a5287a3SAnson Huang return; 5251a5287a3SAnson Huang } 526c19fdaeeSAnson Huang mxc_gpio_restore_regs(port); 5271a5287a3SAnson Huang } 528c19fdaeeSAnson Huang } 529c19fdaeeSAnson Huang 5301a5287a3SAnson Huang static struct syscore_ops mxc_gpio_syscore_ops = { 5311a5287a3SAnson Huang .suspend = mxc_gpio_syscore_suspend, 5321a5287a3SAnson Huang .resume = mxc_gpio_syscore_resume, 533c19fdaeeSAnson Huang }; 534c19fdaeeSAnson Huang 535b78d8e59SShawn Guo static struct platform_driver mxc_gpio_driver = { 536b78d8e59SShawn Guo .driver = { 537b78d8e59SShawn Guo .name = "gpio-mxc", 5388937cb60SShawn Guo .of_match_table = mxc_gpio_dt_ids, 53990e1fc4cSBartosz Golaszewski .suppress_bind_attrs = true, 540b78d8e59SShawn Guo }, 541b78d8e59SShawn Guo .probe = mxc_gpio_probe, 542b78d8e59SShawn Guo }; 543b78d8e59SShawn Guo 544b78d8e59SShawn Guo static int __init gpio_mxc_init(void) 545b78d8e59SShawn Guo { 5461a5287a3SAnson Huang register_syscore_ops(&mxc_gpio_syscore_ops); 5471a5287a3SAnson Huang 548b78d8e59SShawn Guo return platform_driver_register(&mxc_gpio_driver); 549b78d8e59SShawn Guo } 550e188cbf7SVladimir Zapolskiy subsys_initcall(gpio_mxc_init); 55112d16b39SAnson Huang 55212d16b39SAnson Huang MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 55312d16b39SAnson Huang MODULE_DESCRIPTION("i.MX GPIO Driver"); 55412d16b39SAnson Huang MODULE_LICENSE("GPL"); 555