1d37a65bbSShawn Guo /* 2d37a65bbSShawn Guo * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 3d37a65bbSShawn Guo * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 4d37a65bbSShawn Guo * 52c8d6c86SPaul Gortmaker * Based on code from Freescale Semiconductor, 62c8d6c86SPaul Gortmaker * Authors: Daniel Mack, Juergen Beisert. 7d37a65bbSShawn Guo * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 8d37a65bbSShawn Guo * 9d37a65bbSShawn Guo * This program is free software; you can redistribute it and/or 10d37a65bbSShawn Guo * modify it under the terms of the GNU General Public License 11d37a65bbSShawn Guo * as published by the Free Software Foundation; either version 2 12d37a65bbSShawn Guo * of the License, or (at your option) any later version. 13d37a65bbSShawn Guo * This program is distributed in the hope that it will be useful, 14d37a65bbSShawn Guo * but WITHOUT ANY WARRANTY; without even the implied warranty of 15d37a65bbSShawn Guo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16d37a65bbSShawn Guo * GNU General Public License for more details. 17d37a65bbSShawn Guo * 18d37a65bbSShawn Guo * You should have received a copy of the GNU General Public License 19d37a65bbSShawn Guo * along with this program; if not, write to the Free Software 20d37a65bbSShawn Guo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 21d37a65bbSShawn Guo */ 22d37a65bbSShawn Guo 2318f92b19SFabio Estevam #include <linux/err.h> 24d37a65bbSShawn Guo #include <linux/init.h> 25d37a65bbSShawn Guo #include <linux/interrupt.h> 26d37a65bbSShawn Guo #include <linux/io.h> 27d37a65bbSShawn Guo #include <linux/irq.h> 281ab7ef15SShawn Guo #include <linux/irqdomain.h> 29de88cbb7SCatalin Marinas #include <linux/irqchip/chained_irq.h> 30b78d8e59SShawn Guo #include <linux/platform_device.h> 31b78d8e59SShawn Guo #include <linux/slab.h> 320f4630f3SLinus Walleij #include <linux/gpio/driver.h> 330f4630f3SLinus Walleij /* FIXME: for gpio_get_value() replace this with direct register read */ 340f4630f3SLinus Walleij #include <linux/gpio.h> 358937cb60SShawn Guo #include <linux/of.h> 368937cb60SShawn Guo #include <linux/of_device.h> 3716c3bd35SChristoph Hellwig #include <linux/bug.h> 38d37a65bbSShawn Guo 39e7fc6ae7SShawn Guo enum mxc_gpio_hwtype { 40e7fc6ae7SShawn Guo IMX1_GPIO, /* runs on i.mx1 */ 41e7fc6ae7SShawn Guo IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ 42aeb27748SBenoît Thébaudeau IMX31_GPIO, /* runs on i.mx31 */ 43aeb27748SBenoît Thébaudeau IMX35_GPIO, /* runs on all other i.mx */ 44e7fc6ae7SShawn Guo }; 45e7fc6ae7SShawn Guo 46e7fc6ae7SShawn Guo /* device type dependent stuff */ 47e7fc6ae7SShawn Guo struct mxc_gpio_hwdata { 48e7fc6ae7SShawn Guo unsigned dr_reg; 49e7fc6ae7SShawn Guo unsigned gdir_reg; 50e7fc6ae7SShawn Guo unsigned psr_reg; 51e7fc6ae7SShawn Guo unsigned icr1_reg; 52e7fc6ae7SShawn Guo unsigned icr2_reg; 53e7fc6ae7SShawn Guo unsigned imr_reg; 54e7fc6ae7SShawn Guo unsigned isr_reg; 55aeb27748SBenoît Thébaudeau int edge_sel_reg; 56e7fc6ae7SShawn Guo unsigned low_level; 57e7fc6ae7SShawn Guo unsigned high_level; 58e7fc6ae7SShawn Guo unsigned rise_edge; 59e7fc6ae7SShawn Guo unsigned fall_edge; 60e7fc6ae7SShawn Guo }; 61e7fc6ae7SShawn Guo 62b78d8e59SShawn Guo struct mxc_gpio_port { 63b78d8e59SShawn Guo struct list_head node; 64b78d8e59SShawn Guo void __iomem *base; 65b78d8e59SShawn Guo int irq; 66b78d8e59SShawn Guo int irq_high; 671ab7ef15SShawn Guo struct irq_domain *domain; 680f4630f3SLinus Walleij struct gpio_chip gc; 69db5270acSBartosz Golaszewski struct device *dev; 70b78d8e59SShawn Guo u32 both_edges; 71b78d8e59SShawn Guo }; 72b78d8e59SShawn Guo 73e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 74e7fc6ae7SShawn Guo .dr_reg = 0x1c, 75e7fc6ae7SShawn Guo .gdir_reg = 0x00, 76e7fc6ae7SShawn Guo .psr_reg = 0x24, 77e7fc6ae7SShawn Guo .icr1_reg = 0x28, 78e7fc6ae7SShawn Guo .icr2_reg = 0x2c, 79e7fc6ae7SShawn Guo .imr_reg = 0x30, 80e7fc6ae7SShawn Guo .isr_reg = 0x34, 81aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 82e7fc6ae7SShawn Guo .low_level = 0x03, 83e7fc6ae7SShawn Guo .high_level = 0x02, 84e7fc6ae7SShawn Guo .rise_edge = 0x00, 85e7fc6ae7SShawn Guo .fall_edge = 0x01, 86e7fc6ae7SShawn Guo }; 87e7fc6ae7SShawn Guo 88e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 89e7fc6ae7SShawn Guo .dr_reg = 0x00, 90e7fc6ae7SShawn Guo .gdir_reg = 0x04, 91e7fc6ae7SShawn Guo .psr_reg = 0x08, 92e7fc6ae7SShawn Guo .icr1_reg = 0x0c, 93e7fc6ae7SShawn Guo .icr2_reg = 0x10, 94e7fc6ae7SShawn Guo .imr_reg = 0x14, 95e7fc6ae7SShawn Guo .isr_reg = 0x18, 96aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 97aeb27748SBenoît Thébaudeau .low_level = 0x00, 98aeb27748SBenoît Thébaudeau .high_level = 0x01, 99aeb27748SBenoît Thébaudeau .rise_edge = 0x02, 100aeb27748SBenoît Thébaudeau .fall_edge = 0x03, 101aeb27748SBenoît Thébaudeau }; 102aeb27748SBenoît Thébaudeau 103aeb27748SBenoît Thébaudeau static struct mxc_gpio_hwdata imx35_gpio_hwdata = { 104aeb27748SBenoît Thébaudeau .dr_reg = 0x00, 105aeb27748SBenoît Thébaudeau .gdir_reg = 0x04, 106aeb27748SBenoît Thébaudeau .psr_reg = 0x08, 107aeb27748SBenoît Thébaudeau .icr1_reg = 0x0c, 108aeb27748SBenoît Thébaudeau .icr2_reg = 0x10, 109aeb27748SBenoît Thébaudeau .imr_reg = 0x14, 110aeb27748SBenoît Thébaudeau .isr_reg = 0x18, 111aeb27748SBenoît Thébaudeau .edge_sel_reg = 0x1c, 112e7fc6ae7SShawn Guo .low_level = 0x00, 113e7fc6ae7SShawn Guo .high_level = 0x01, 114e7fc6ae7SShawn Guo .rise_edge = 0x02, 115e7fc6ae7SShawn Guo .fall_edge = 0x03, 116e7fc6ae7SShawn Guo }; 117e7fc6ae7SShawn Guo 118e7fc6ae7SShawn Guo static enum mxc_gpio_hwtype mxc_gpio_hwtype; 119e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata *mxc_gpio_hwdata; 120e7fc6ae7SShawn Guo 121e7fc6ae7SShawn Guo #define GPIO_DR (mxc_gpio_hwdata->dr_reg) 122e7fc6ae7SShawn Guo #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg) 123e7fc6ae7SShawn Guo #define GPIO_PSR (mxc_gpio_hwdata->psr_reg) 124e7fc6ae7SShawn Guo #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg) 125e7fc6ae7SShawn Guo #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg) 126e7fc6ae7SShawn Guo #define GPIO_IMR (mxc_gpio_hwdata->imr_reg) 127e7fc6ae7SShawn Guo #define GPIO_ISR (mxc_gpio_hwdata->isr_reg) 128aeb27748SBenoît Thébaudeau #define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg) 129e7fc6ae7SShawn Guo 130e7fc6ae7SShawn Guo #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level) 131e7fc6ae7SShawn Guo #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level) 132e7fc6ae7SShawn Guo #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge) 133e7fc6ae7SShawn Guo #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge) 134aeb27748SBenoît Thébaudeau #define GPIO_INT_BOTH_EDGES 0x4 135e7fc6ae7SShawn Guo 136f4f79d40SKrzysztof Kozlowski static const struct platform_device_id mxc_gpio_devtype[] = { 137e7fc6ae7SShawn Guo { 138e7fc6ae7SShawn Guo .name = "imx1-gpio", 139e7fc6ae7SShawn Guo .driver_data = IMX1_GPIO, 140e7fc6ae7SShawn Guo }, { 141e7fc6ae7SShawn Guo .name = "imx21-gpio", 142e7fc6ae7SShawn Guo .driver_data = IMX21_GPIO, 143e7fc6ae7SShawn Guo }, { 144e7fc6ae7SShawn Guo .name = "imx31-gpio", 145e7fc6ae7SShawn Guo .driver_data = IMX31_GPIO, 146e7fc6ae7SShawn Guo }, { 147aeb27748SBenoît Thébaudeau .name = "imx35-gpio", 148aeb27748SBenoît Thébaudeau .driver_data = IMX35_GPIO, 149aeb27748SBenoît Thébaudeau }, { 150e7fc6ae7SShawn Guo /* sentinel */ 151e7fc6ae7SShawn Guo } 152e7fc6ae7SShawn Guo }; 153e7fc6ae7SShawn Guo 1548937cb60SShawn Guo static const struct of_device_id mxc_gpio_dt_ids[] = { 1558937cb60SShawn Guo { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], }, 1568937cb60SShawn Guo { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], }, 1578937cb60SShawn Guo { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], }, 158aeb27748SBenoît Thébaudeau { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], }, 1598937cb60SShawn Guo { /* sentinel */ } 1608937cb60SShawn Guo }; 1618937cb60SShawn Guo 162b78d8e59SShawn Guo /* 163b78d8e59SShawn Guo * MX2 has one interrupt *for all* gpio ports. The list is used 164b78d8e59SShawn Guo * to save the references to all ports, so that mx2_gpio_irq_handler 165b78d8e59SShawn Guo * can walk through all interrupt status registers. 166b78d8e59SShawn Guo */ 167b78d8e59SShawn Guo static LIST_HEAD(mxc_gpio_ports); 168d37a65bbSShawn Guo 169d37a65bbSShawn Guo /* Note: This driver assumes 32 GPIOs are handled in one register */ 170d37a65bbSShawn Guo 171d37a65bbSShawn Guo static int gpio_set_irq_type(struct irq_data *d, u32 type) 172d37a65bbSShawn Guo { 173e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 174e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 175d37a65bbSShawn Guo u32 bit, val; 1761ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 1770f4630f3SLinus Walleij u32 gpio = port->gc.base + gpio_idx; 178d37a65bbSShawn Guo int edge; 179d37a65bbSShawn Guo void __iomem *reg = port->base; 180d37a65bbSShawn Guo 1811ab7ef15SShawn Guo port->both_edges &= ~(1 << gpio_idx); 182d37a65bbSShawn Guo switch (type) { 183d37a65bbSShawn Guo case IRQ_TYPE_EDGE_RISING: 184d37a65bbSShawn Guo edge = GPIO_INT_RISE_EDGE; 185d37a65bbSShawn Guo break; 186d37a65bbSShawn Guo case IRQ_TYPE_EDGE_FALLING: 187d37a65bbSShawn Guo edge = GPIO_INT_FALL_EDGE; 188d37a65bbSShawn Guo break; 189d37a65bbSShawn Guo case IRQ_TYPE_EDGE_BOTH: 190aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 191aeb27748SBenoît Thébaudeau edge = GPIO_INT_BOTH_EDGES; 192aeb27748SBenoît Thébaudeau } else { 1935523f86bSShawn Guo val = gpio_get_value(gpio); 194d37a65bbSShawn Guo if (val) { 195d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 196d37a65bbSShawn Guo pr_debug("mxc: set GPIO %d to low trigger\n", gpio); 197d37a65bbSShawn Guo } else { 198d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 199d37a65bbSShawn Guo pr_debug("mxc: set GPIO %d to high trigger\n", gpio); 200d37a65bbSShawn Guo } 2011ab7ef15SShawn Guo port->both_edges |= 1 << gpio_idx; 202aeb27748SBenoît Thébaudeau } 203d37a65bbSShawn Guo break; 204d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_LOW: 205d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 206d37a65bbSShawn Guo break; 207d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_HIGH: 208d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 209d37a65bbSShawn Guo break; 210d37a65bbSShawn Guo default: 211d37a65bbSShawn Guo return -EINVAL; 212d37a65bbSShawn Guo } 213d37a65bbSShawn Guo 214aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 215aeb27748SBenoît Thébaudeau val = readl(port->base + GPIO_EDGE_SEL); 216aeb27748SBenoît Thébaudeau if (edge == GPIO_INT_BOTH_EDGES) 217f948ad07SLinus Torvalds writel(val | (1 << gpio_idx), 218aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 219aeb27748SBenoît Thébaudeau else 220f948ad07SLinus Torvalds writel(val & ~(1 << gpio_idx), 221aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 222aeb27748SBenoît Thébaudeau } 223aeb27748SBenoît Thébaudeau 224aeb27748SBenoît Thébaudeau if (edge != GPIO_INT_BOTH_EDGES) { 225f948ad07SLinus Torvalds reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ 2261ab7ef15SShawn Guo bit = gpio_idx & 0xf; 227b78d8e59SShawn Guo val = readl(reg) & ~(0x3 << (bit << 1)); 228b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 229aeb27748SBenoît Thébaudeau } 230aeb27748SBenoît Thébaudeau 2311ab7ef15SShawn Guo writel(1 << gpio_idx, port->base + GPIO_ISR); 232d37a65bbSShawn Guo 233d37a65bbSShawn Guo return 0; 234d37a65bbSShawn Guo } 235d37a65bbSShawn Guo 236d37a65bbSShawn Guo static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 237d37a65bbSShawn Guo { 238d37a65bbSShawn Guo void __iomem *reg = port->base; 239d37a65bbSShawn Guo u32 bit, val; 240d37a65bbSShawn Guo int edge; 241d37a65bbSShawn Guo 242d37a65bbSShawn Guo reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 243d37a65bbSShawn Guo bit = gpio & 0xf; 244b78d8e59SShawn Guo val = readl(reg); 245d37a65bbSShawn Guo edge = (val >> (bit << 1)) & 3; 246d37a65bbSShawn Guo val &= ~(0x3 << (bit << 1)); 247d37a65bbSShawn Guo if (edge == GPIO_INT_HIGH_LEV) { 248d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 249d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 250d37a65bbSShawn Guo } else if (edge == GPIO_INT_LOW_LEV) { 251d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 252d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 253d37a65bbSShawn Guo } else { 254d37a65bbSShawn Guo pr_err("mxc: invalid configuration for GPIO %d: %x\n", 255d37a65bbSShawn Guo gpio, edge); 256d37a65bbSShawn Guo return; 257d37a65bbSShawn Guo } 258b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 259d37a65bbSShawn Guo } 260d37a65bbSShawn Guo 261d37a65bbSShawn Guo /* handle 32 interrupts in one status register */ 262d37a65bbSShawn Guo static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 263d37a65bbSShawn Guo { 264d37a65bbSShawn Guo while (irq_stat != 0) { 265d37a65bbSShawn Guo int irqoffset = fls(irq_stat) - 1; 266d37a65bbSShawn Guo 267d37a65bbSShawn Guo if (port->both_edges & (1 << irqoffset)) 268d37a65bbSShawn Guo mxc_flip_edge(port, irqoffset); 269d37a65bbSShawn Guo 2701ab7ef15SShawn Guo generic_handle_irq(irq_find_mapping(port->domain, irqoffset)); 271d37a65bbSShawn Guo 272d37a65bbSShawn Guo irq_stat &= ~(1 << irqoffset); 273d37a65bbSShawn Guo } 274d37a65bbSShawn Guo } 275d37a65bbSShawn Guo 276d37a65bbSShawn Guo /* MX1 and MX3 has one interrupt *per* gpio port */ 277bd0b9ac4SThomas Gleixner static void mx3_gpio_irq_handler(struct irq_desc *desc) 278d37a65bbSShawn Guo { 279d37a65bbSShawn Guo u32 irq_stat; 280476f8b4cSJiang Liu struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); 281476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 2820e44b6ecSShawn Guo 2830e44b6ecSShawn Guo chained_irq_enter(chip, desc); 284d37a65bbSShawn Guo 285b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 286d37a65bbSShawn Guo 287d37a65bbSShawn Guo mxc_gpio_irq_handler(port, irq_stat); 2880e44b6ecSShawn Guo 2890e44b6ecSShawn Guo chained_irq_exit(chip, desc); 290d37a65bbSShawn Guo } 291d37a65bbSShawn Guo 292d37a65bbSShawn Guo /* MX2 has one interrupt *for all* gpio ports */ 293bd0b9ac4SThomas Gleixner static void mx2_gpio_irq_handler(struct irq_desc *desc) 294d37a65bbSShawn Guo { 295d37a65bbSShawn Guo u32 irq_msk, irq_stat; 296b78d8e59SShawn Guo struct mxc_gpio_port *port; 297476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 298c0e811d9SUwe Kleine-König 299c0e811d9SUwe Kleine-König chained_irq_enter(chip, desc); 300d37a65bbSShawn Guo 301d37a65bbSShawn Guo /* walk through all interrupt status registers */ 302b78d8e59SShawn Guo list_for_each_entry(port, &mxc_gpio_ports, node) { 303b78d8e59SShawn Guo irq_msk = readl(port->base + GPIO_IMR); 304d37a65bbSShawn Guo if (!irq_msk) 305d37a65bbSShawn Guo continue; 306d37a65bbSShawn Guo 307b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 308d37a65bbSShawn Guo if (irq_stat) 309b78d8e59SShawn Guo mxc_gpio_irq_handler(port, irq_stat); 310d37a65bbSShawn Guo } 311c0e811d9SUwe Kleine-König chained_irq_exit(chip, desc); 312d37a65bbSShawn Guo } 313d37a65bbSShawn Guo 314d37a65bbSShawn Guo /* 315d37a65bbSShawn Guo * Set interrupt number "irq" in the GPIO as a wake-up source. 316d37a65bbSShawn Guo * While system is running, all registered GPIO interrupts need to have 317d37a65bbSShawn Guo * wake-up enabled. When system is suspended, only selected GPIO interrupts 318d37a65bbSShawn Guo * need to have wake-up enabled. 319d37a65bbSShawn Guo * @param irq interrupt source number 320d37a65bbSShawn Guo * @param enable enable as wake-up if equal to non-zero 321d37a65bbSShawn Guo * @return This function returns 0 on success. 322d37a65bbSShawn Guo */ 323d37a65bbSShawn Guo static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 324d37a65bbSShawn Guo { 325e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 326e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 3271ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 32877a4d757SPhilipp Rosenberger int ret; 329d37a65bbSShawn Guo 330d37a65bbSShawn Guo if (enable) { 331d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 33277a4d757SPhilipp Rosenberger ret = enable_irq_wake(port->irq_high); 333d37a65bbSShawn Guo else 33477a4d757SPhilipp Rosenberger ret = enable_irq_wake(port->irq); 335d37a65bbSShawn Guo } else { 336d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 33777a4d757SPhilipp Rosenberger ret = disable_irq_wake(port->irq_high); 338d37a65bbSShawn Guo else 33977a4d757SPhilipp Rosenberger ret = disable_irq_wake(port->irq); 340d37a65bbSShawn Guo } 341d37a65bbSShawn Guo 34277a4d757SPhilipp Rosenberger return ret; 343d37a65bbSShawn Guo } 344d37a65bbSShawn Guo 3459e26b0b1SPeng Fan static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) 346e4ea9333SShawn Guo { 347e4ea9333SShawn Guo struct irq_chip_generic *gc; 348e4ea9333SShawn Guo struct irq_chip_type *ct; 349db5270acSBartosz Golaszewski int rv; 350d37a65bbSShawn Guo 351db5270acSBartosz Golaszewski gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base, 352e4ea9333SShawn Guo port->base, handle_level_irq); 3539e26b0b1SPeng Fan if (!gc) 3549e26b0b1SPeng Fan return -ENOMEM; 355e4ea9333SShawn Guo gc->private = port; 356e4ea9333SShawn Guo 357e4ea9333SShawn Guo ct = gc->chip_types; 358591567a5SShawn Guo ct->chip.irq_ack = irq_gc_ack_set_bit; 359e4ea9333SShawn Guo ct->chip.irq_mask = irq_gc_mask_clr_bit; 360e4ea9333SShawn Guo ct->chip.irq_unmask = irq_gc_mask_set_bit; 361e4ea9333SShawn Guo ct->chip.irq_set_type = gpio_set_irq_type; 362591567a5SShawn Guo ct->chip.irq_set_wake = gpio_set_wake_irq; 363952cfbd3SUlises Brindis ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND; 364e4ea9333SShawn Guo ct->regs.ack = GPIO_ISR; 365e4ea9333SShawn Guo ct->regs.mask = GPIO_IMR; 366e4ea9333SShawn Guo 367db5270acSBartosz Golaszewski rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), 368db5270acSBartosz Golaszewski IRQ_GC_INIT_NESTED_LOCK, 369e4ea9333SShawn Guo IRQ_NOREQUEST, 0); 3709e26b0b1SPeng Fan 371db5270acSBartosz Golaszewski return rv; 372e4ea9333SShawn Guo } 373d37a65bbSShawn Guo 3743836309dSBill Pemberton static void mxc_gpio_get_hw(struct platform_device *pdev) 375e7fc6ae7SShawn Guo { 3768937cb60SShawn Guo const struct of_device_id *of_id = 3778937cb60SShawn Guo of_match_device(mxc_gpio_dt_ids, &pdev->dev); 3788937cb60SShawn Guo enum mxc_gpio_hwtype hwtype; 3798937cb60SShawn Guo 3808937cb60SShawn Guo if (of_id) 3818937cb60SShawn Guo pdev->id_entry = of_id->data; 3828937cb60SShawn Guo hwtype = pdev->id_entry->driver_data; 383e7fc6ae7SShawn Guo 384e7fc6ae7SShawn Guo if (mxc_gpio_hwtype) { 385e7fc6ae7SShawn Guo /* 386e7fc6ae7SShawn Guo * The driver works with a reasonable presupposition, 387e7fc6ae7SShawn Guo * that is all gpio ports must be the same type when 388e7fc6ae7SShawn Guo * running on one soc. 389e7fc6ae7SShawn Guo */ 390e7fc6ae7SShawn Guo BUG_ON(mxc_gpio_hwtype != hwtype); 391e7fc6ae7SShawn Guo return; 392e7fc6ae7SShawn Guo } 393e7fc6ae7SShawn Guo 394aeb27748SBenoît Thébaudeau if (hwtype == IMX35_GPIO) 395aeb27748SBenoît Thébaudeau mxc_gpio_hwdata = &imx35_gpio_hwdata; 396aeb27748SBenoît Thébaudeau else if (hwtype == IMX31_GPIO) 397e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx31_gpio_hwdata; 398e7fc6ae7SShawn Guo else 399e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata; 400e7fc6ae7SShawn Guo 401e7fc6ae7SShawn Guo mxc_gpio_hwtype = hwtype; 402e7fc6ae7SShawn Guo } 403e7fc6ae7SShawn Guo 40409ad8039SShawn Guo static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 40509ad8039SShawn Guo { 4060f4630f3SLinus Walleij struct mxc_gpio_port *port = gpiochip_get_data(gc); 40709ad8039SShawn Guo 4081ab7ef15SShawn Guo return irq_find_mapping(port->domain, offset); 40909ad8039SShawn Guo } 41009ad8039SShawn Guo 4113836309dSBill Pemberton static int mxc_gpio_probe(struct platform_device *pdev) 412d37a65bbSShawn Guo { 4138937cb60SShawn Guo struct device_node *np = pdev->dev.of_node; 414b78d8e59SShawn Guo struct mxc_gpio_port *port; 415b78d8e59SShawn Guo struct resource *iores; 4161ab7ef15SShawn Guo int irq_base; 417e4ea9333SShawn Guo int err; 418d37a65bbSShawn Guo 419e7fc6ae7SShawn Guo mxc_gpio_get_hw(pdev); 420e7fc6ae7SShawn Guo 4218cd73e4eSFabio Estevam port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 422b78d8e59SShawn Guo if (!port) 423b78d8e59SShawn Guo return -ENOMEM; 424d37a65bbSShawn Guo 425db5270acSBartosz Golaszewski port->dev = &pdev->dev; 426db5270acSBartosz Golaszewski 427b78d8e59SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4288cd73e4eSFabio Estevam port->base = devm_ioremap_resource(&pdev->dev, iores); 4298cd73e4eSFabio Estevam if (IS_ERR(port->base)) 4308cd73e4eSFabio Estevam return PTR_ERR(port->base); 431b78d8e59SShawn Guo 432b78d8e59SShawn Guo port->irq_high = platform_get_irq(pdev, 1); 433cc9269f8SPhilipp Rosenberger if (port->irq_high < 0) 434cc9269f8SPhilipp Rosenberger port->irq_high = 0; 435cc9269f8SPhilipp Rosenberger 436b78d8e59SShawn Guo port->irq = platform_get_irq(pdev, 0); 4378cd73e4eSFabio Estevam if (port->irq < 0) 4385ea80e49SSachin Kamat return port->irq; 439b78d8e59SShawn Guo 440d37a65bbSShawn Guo /* disable the interrupt and clear the status */ 441b78d8e59SShawn Guo writel(0, port->base + GPIO_IMR); 442b78d8e59SShawn Guo writel(~0, port->base + GPIO_ISR); 443d37a65bbSShawn Guo 444e7fc6ae7SShawn Guo if (mxc_gpio_hwtype == IMX21_GPIO) { 44533a4e985SUwe Kleine-König /* 44633a4e985SUwe Kleine-König * Setup one handler for all GPIO interrupts. Actually setting 44733a4e985SUwe Kleine-König * the handler is needed only once, but doing it for every port 44833a4e985SUwe Kleine-König * is more robust and easier. 44933a4e985SUwe Kleine-König */ 45033a4e985SUwe Kleine-König irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); 451b78d8e59SShawn Guo } else { 452b78d8e59SShawn Guo /* setup one handler for each entry */ 453e65eea54SRussell King irq_set_chained_handler_and_data(port->irq, 454e65eea54SRussell King mx3_gpio_irq_handler, port); 455e65eea54SRussell King if (port->irq_high > 0) 456b78d8e59SShawn Guo /* setup handler for GPIO 16 to 31 */ 457e65eea54SRussell King irq_set_chained_handler_and_data(port->irq_high, 458e65eea54SRussell King mx3_gpio_irq_handler, 459e65eea54SRussell King port); 460d37a65bbSShawn Guo } 461d37a65bbSShawn Guo 4620f4630f3SLinus Walleij err = bgpio_init(&port->gc, &pdev->dev, 4, 4632ce420daSShawn Guo port->base + GPIO_PSR, 4642ce420daSShawn Guo port->base + GPIO_DR, NULL, 465442b2494SVladimir Zapolskiy port->base + GPIO_GDIR, NULL, 466442b2494SVladimir Zapolskiy BGPIOF_READ_OUTPUT_REG_SET); 467b78d8e59SShawn Guo if (err) 4688cd73e4eSFabio Estevam goto out_bgio; 469b78d8e59SShawn Guo 4704c806c98SVladimir Zapolskiy if (of_property_read_bool(np, "gpio-ranges")) { 4714c806c98SVladimir Zapolskiy port->gc.request = gpiochip_generic_request; 4724c806c98SVladimir Zapolskiy port->gc.free = gpiochip_generic_free; 4734c806c98SVladimir Zapolskiy } 4744c806c98SVladimir Zapolskiy 4750f4630f3SLinus Walleij port->gc.to_irq = mxc_gpio_to_irq; 4760f4630f3SLinus Walleij port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : 4777e6086d9SShawn Guo pdev->id * 32; 4782ce420daSShawn Guo 479ffc56630SLaxman Dewangan err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port); 4802ce420daSShawn Guo if (err) 4810f4630f3SLinus Walleij goto out_bgio; 4822ce420daSShawn Guo 483c553c3c4SBartosz Golaszewski irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); 4841ab7ef15SShawn Guo if (irq_base < 0) { 4851ab7ef15SShawn Guo err = irq_base; 486ffc56630SLaxman Dewangan goto out_bgio; 4871ab7ef15SShawn Guo } 4881ab7ef15SShawn Guo 4891ab7ef15SShawn Guo port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, 4901ab7ef15SShawn Guo &irq_domain_simple_ops, NULL); 4911ab7ef15SShawn Guo if (!port->domain) { 4921ab7ef15SShawn Guo err = -ENODEV; 493c553c3c4SBartosz Golaszewski goto out_bgio; 4941ab7ef15SShawn Guo } 4958937cb60SShawn Guo 4968937cb60SShawn Guo /* gpio-mxc can be a generic irq chip */ 4979e26b0b1SPeng Fan err = mxc_gpio_init_gc(port, irq_base); 4989e26b0b1SPeng Fan if (err < 0) 4999e26b0b1SPeng Fan goto out_irqdomain_remove; 5008937cb60SShawn Guo 501b78d8e59SShawn Guo list_add_tail(&port->node, &mxc_gpio_ports); 502b78d8e59SShawn Guo 503d37a65bbSShawn Guo return 0; 504b78d8e59SShawn Guo 5059e26b0b1SPeng Fan out_irqdomain_remove: 5069e26b0b1SPeng Fan irq_domain_remove(port->domain); 5078cd73e4eSFabio Estevam out_bgio: 508b78d8e59SShawn Guo dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 509b78d8e59SShawn Guo return err; 510d37a65bbSShawn Guo } 511b78d8e59SShawn Guo 512b78d8e59SShawn Guo static struct platform_driver mxc_gpio_driver = { 513b78d8e59SShawn Guo .driver = { 514b78d8e59SShawn Guo .name = "gpio-mxc", 5158937cb60SShawn Guo .of_match_table = mxc_gpio_dt_ids, 51690e1fc4cSBartosz Golaszewski .suppress_bind_attrs = true, 517b78d8e59SShawn Guo }, 518b78d8e59SShawn Guo .probe = mxc_gpio_probe, 519e7fc6ae7SShawn Guo .id_table = mxc_gpio_devtype, 520b78d8e59SShawn Guo }; 521b78d8e59SShawn Guo 522b78d8e59SShawn Guo static int __init gpio_mxc_init(void) 523b78d8e59SShawn Guo { 524b78d8e59SShawn Guo return platform_driver_register(&mxc_gpio_driver); 525b78d8e59SShawn Guo } 526e188cbf7SVladimir Zapolskiy subsys_initcall(gpio_mxc_init); 527