1014e420dSFabio Estevam // SPDX-License-Identifier: GPL-2.0+ 2014e420dSFabio Estevam // 3014e420dSFabio Estevam // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 4014e420dSFabio Estevam // Copyright 2008 Juergen Beisert, kernel@pengutronix.de 5014e420dSFabio Estevam // 6014e420dSFabio Estevam // Based on code from Freescale Semiconductor, 7014e420dSFabio Estevam // Authors: Daniel Mack, Juergen Beisert. 8014e420dSFabio Estevam // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9d37a65bbSShawn Guo 102808801aSAnson Huang #include <linux/clk.h> 1118f92b19SFabio Estevam #include <linux/err.h> 12d37a65bbSShawn Guo #include <linux/init.h> 13d37a65bbSShawn Guo #include <linux/interrupt.h> 14d37a65bbSShawn Guo #include <linux/io.h> 15d37a65bbSShawn Guo #include <linux/irq.h> 161ab7ef15SShawn Guo #include <linux/irqdomain.h> 17de88cbb7SCatalin Marinas #include <linux/irqchip/chained_irq.h> 18b78d8e59SShawn Guo #include <linux/platform_device.h> 19b78d8e59SShawn Guo #include <linux/slab.h> 200f4630f3SLinus Walleij #include <linux/gpio/driver.h> 218937cb60SShawn Guo #include <linux/of.h> 228937cb60SShawn Guo #include <linux/of_device.h> 2316c3bd35SChristoph Hellwig #include <linux/bug.h> 24d37a65bbSShawn Guo 25e7fc6ae7SShawn Guo enum mxc_gpio_hwtype { 26e7fc6ae7SShawn Guo IMX1_GPIO, /* runs on i.mx1 */ 27e7fc6ae7SShawn Guo IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ 28aeb27748SBenoît Thébaudeau IMX31_GPIO, /* runs on i.mx31 */ 29aeb27748SBenoît Thébaudeau IMX35_GPIO, /* runs on all other i.mx */ 30e7fc6ae7SShawn Guo }; 31e7fc6ae7SShawn Guo 32e7fc6ae7SShawn Guo /* device type dependent stuff */ 33e7fc6ae7SShawn Guo struct mxc_gpio_hwdata { 34e7fc6ae7SShawn Guo unsigned dr_reg; 35e7fc6ae7SShawn Guo unsigned gdir_reg; 36e7fc6ae7SShawn Guo unsigned psr_reg; 37e7fc6ae7SShawn Guo unsigned icr1_reg; 38e7fc6ae7SShawn Guo unsigned icr2_reg; 39e7fc6ae7SShawn Guo unsigned imr_reg; 40e7fc6ae7SShawn Guo unsigned isr_reg; 41aeb27748SBenoît Thébaudeau int edge_sel_reg; 42e7fc6ae7SShawn Guo unsigned low_level; 43e7fc6ae7SShawn Guo unsigned high_level; 44e7fc6ae7SShawn Guo unsigned rise_edge; 45e7fc6ae7SShawn Guo unsigned fall_edge; 46e7fc6ae7SShawn Guo }; 47e7fc6ae7SShawn Guo 48c19fdaeeSAnson Huang struct mxc_gpio_reg_saved { 49c19fdaeeSAnson Huang u32 icr1; 50c19fdaeeSAnson Huang u32 icr2; 51c19fdaeeSAnson Huang u32 imr; 52c19fdaeeSAnson Huang u32 gdir; 53c19fdaeeSAnson Huang u32 edge_sel; 54c19fdaeeSAnson Huang u32 dr; 55c19fdaeeSAnson Huang }; 56c19fdaeeSAnson Huang 57b78d8e59SShawn Guo struct mxc_gpio_port { 58b78d8e59SShawn Guo struct list_head node; 59b78d8e59SShawn Guo void __iomem *base; 602808801aSAnson Huang struct clk *clk; 61b78d8e59SShawn Guo int irq; 62b78d8e59SShawn Guo int irq_high; 631ab7ef15SShawn Guo struct irq_domain *domain; 640f4630f3SLinus Walleij struct gpio_chip gc; 65db5270acSBartosz Golaszewski struct device *dev; 66b78d8e59SShawn Guo u32 both_edges; 67c19fdaeeSAnson Huang struct mxc_gpio_reg_saved gpio_saved_reg; 68c19fdaeeSAnson Huang bool power_off; 69b78d8e59SShawn Guo }; 70b78d8e59SShawn Guo 71e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 72e7fc6ae7SShawn Guo .dr_reg = 0x1c, 73e7fc6ae7SShawn Guo .gdir_reg = 0x00, 74e7fc6ae7SShawn Guo .psr_reg = 0x24, 75e7fc6ae7SShawn Guo .icr1_reg = 0x28, 76e7fc6ae7SShawn Guo .icr2_reg = 0x2c, 77e7fc6ae7SShawn Guo .imr_reg = 0x30, 78e7fc6ae7SShawn Guo .isr_reg = 0x34, 79aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 80e7fc6ae7SShawn Guo .low_level = 0x03, 81e7fc6ae7SShawn Guo .high_level = 0x02, 82e7fc6ae7SShawn Guo .rise_edge = 0x00, 83e7fc6ae7SShawn Guo .fall_edge = 0x01, 84e7fc6ae7SShawn Guo }; 85e7fc6ae7SShawn Guo 86e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 87e7fc6ae7SShawn Guo .dr_reg = 0x00, 88e7fc6ae7SShawn Guo .gdir_reg = 0x04, 89e7fc6ae7SShawn Guo .psr_reg = 0x08, 90e7fc6ae7SShawn Guo .icr1_reg = 0x0c, 91e7fc6ae7SShawn Guo .icr2_reg = 0x10, 92e7fc6ae7SShawn Guo .imr_reg = 0x14, 93e7fc6ae7SShawn Guo .isr_reg = 0x18, 94aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 95aeb27748SBenoît Thébaudeau .low_level = 0x00, 96aeb27748SBenoît Thébaudeau .high_level = 0x01, 97aeb27748SBenoît Thébaudeau .rise_edge = 0x02, 98aeb27748SBenoît Thébaudeau .fall_edge = 0x03, 99aeb27748SBenoît Thébaudeau }; 100aeb27748SBenoît Thébaudeau 101aeb27748SBenoît Thébaudeau static struct mxc_gpio_hwdata imx35_gpio_hwdata = { 102aeb27748SBenoît Thébaudeau .dr_reg = 0x00, 103aeb27748SBenoît Thébaudeau .gdir_reg = 0x04, 104aeb27748SBenoît Thébaudeau .psr_reg = 0x08, 105aeb27748SBenoît Thébaudeau .icr1_reg = 0x0c, 106aeb27748SBenoît Thébaudeau .icr2_reg = 0x10, 107aeb27748SBenoît Thébaudeau .imr_reg = 0x14, 108aeb27748SBenoît Thébaudeau .isr_reg = 0x18, 109aeb27748SBenoît Thébaudeau .edge_sel_reg = 0x1c, 110e7fc6ae7SShawn Guo .low_level = 0x00, 111e7fc6ae7SShawn Guo .high_level = 0x01, 112e7fc6ae7SShawn Guo .rise_edge = 0x02, 113e7fc6ae7SShawn Guo .fall_edge = 0x03, 114e7fc6ae7SShawn Guo }; 115e7fc6ae7SShawn Guo 116e7fc6ae7SShawn Guo static enum mxc_gpio_hwtype mxc_gpio_hwtype; 117e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata *mxc_gpio_hwdata; 118e7fc6ae7SShawn Guo 119e7fc6ae7SShawn Guo #define GPIO_DR (mxc_gpio_hwdata->dr_reg) 120e7fc6ae7SShawn Guo #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg) 121e7fc6ae7SShawn Guo #define GPIO_PSR (mxc_gpio_hwdata->psr_reg) 122e7fc6ae7SShawn Guo #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg) 123e7fc6ae7SShawn Guo #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg) 124e7fc6ae7SShawn Guo #define GPIO_IMR (mxc_gpio_hwdata->imr_reg) 125e7fc6ae7SShawn Guo #define GPIO_ISR (mxc_gpio_hwdata->isr_reg) 126aeb27748SBenoît Thébaudeau #define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg) 127e7fc6ae7SShawn Guo 128e7fc6ae7SShawn Guo #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level) 129e7fc6ae7SShawn Guo #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level) 130e7fc6ae7SShawn Guo #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge) 131e7fc6ae7SShawn Guo #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge) 132aeb27748SBenoît Thébaudeau #define GPIO_INT_BOTH_EDGES 0x4 133e7fc6ae7SShawn Guo 134f4f79d40SKrzysztof Kozlowski static const struct platform_device_id mxc_gpio_devtype[] = { 135e7fc6ae7SShawn Guo { 136e7fc6ae7SShawn Guo .name = "imx1-gpio", 137e7fc6ae7SShawn Guo .driver_data = IMX1_GPIO, 138e7fc6ae7SShawn Guo }, { 139e7fc6ae7SShawn Guo .name = "imx21-gpio", 140e7fc6ae7SShawn Guo .driver_data = IMX21_GPIO, 141e7fc6ae7SShawn Guo }, { 142e7fc6ae7SShawn Guo .name = "imx31-gpio", 143e7fc6ae7SShawn Guo .driver_data = IMX31_GPIO, 144e7fc6ae7SShawn Guo }, { 145aeb27748SBenoît Thébaudeau .name = "imx35-gpio", 146aeb27748SBenoît Thébaudeau .driver_data = IMX35_GPIO, 147aeb27748SBenoît Thébaudeau }, { 148e7fc6ae7SShawn Guo /* sentinel */ 149e7fc6ae7SShawn Guo } 150e7fc6ae7SShawn Guo }; 151e7fc6ae7SShawn Guo 1528937cb60SShawn Guo static const struct of_device_id mxc_gpio_dt_ids[] = { 1538937cb60SShawn Guo { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], }, 1548937cb60SShawn Guo { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], }, 1558937cb60SShawn Guo { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], }, 156aeb27748SBenoît Thébaudeau { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], }, 157c19fdaeeSAnson Huang { .compatible = "fsl,imx7d-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], }, 1588937cb60SShawn Guo { /* sentinel */ } 1598937cb60SShawn Guo }; 1608937cb60SShawn Guo 161b78d8e59SShawn Guo /* 162b78d8e59SShawn Guo * MX2 has one interrupt *for all* gpio ports. The list is used 163b78d8e59SShawn Guo * to save the references to all ports, so that mx2_gpio_irq_handler 164b78d8e59SShawn Guo * can walk through all interrupt status registers. 165b78d8e59SShawn Guo */ 166b78d8e59SShawn Guo static LIST_HEAD(mxc_gpio_ports); 167d37a65bbSShawn Guo 168d37a65bbSShawn Guo /* Note: This driver assumes 32 GPIOs are handled in one register */ 169d37a65bbSShawn Guo 170d37a65bbSShawn Guo static int gpio_set_irq_type(struct irq_data *d, u32 type) 171d37a65bbSShawn Guo { 172e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 173e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 174d37a65bbSShawn Guo u32 bit, val; 1751ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 176d37a65bbSShawn Guo int edge; 177d37a65bbSShawn Guo void __iomem *reg = port->base; 178d37a65bbSShawn Guo 1791ab7ef15SShawn Guo port->both_edges &= ~(1 << gpio_idx); 180d37a65bbSShawn Guo switch (type) { 181d37a65bbSShawn Guo case IRQ_TYPE_EDGE_RISING: 182d37a65bbSShawn Guo edge = GPIO_INT_RISE_EDGE; 183d37a65bbSShawn Guo break; 184d37a65bbSShawn Guo case IRQ_TYPE_EDGE_FALLING: 185d37a65bbSShawn Guo edge = GPIO_INT_FALL_EDGE; 186d37a65bbSShawn Guo break; 187d37a65bbSShawn Guo case IRQ_TYPE_EDGE_BOTH: 188aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 189aeb27748SBenoît Thébaudeau edge = GPIO_INT_BOTH_EDGES; 190aeb27748SBenoît Thébaudeau } else { 1918d0bd9a5SLinus Walleij val = port->gc.get(&port->gc, gpio_idx); 192d37a65bbSShawn Guo if (val) { 193d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 1948d0bd9a5SLinus Walleij pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx); 195d37a65bbSShawn Guo } else { 196d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 1978d0bd9a5SLinus Walleij pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx); 198d37a65bbSShawn Guo } 1991ab7ef15SShawn Guo port->both_edges |= 1 << gpio_idx; 200aeb27748SBenoît Thébaudeau } 201d37a65bbSShawn Guo break; 202d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_LOW: 203d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 204d37a65bbSShawn Guo break; 205d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_HIGH: 206d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 207d37a65bbSShawn Guo break; 208d37a65bbSShawn Guo default: 209d37a65bbSShawn Guo return -EINVAL; 210d37a65bbSShawn Guo } 211d37a65bbSShawn Guo 212aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 213aeb27748SBenoît Thébaudeau val = readl(port->base + GPIO_EDGE_SEL); 214aeb27748SBenoît Thébaudeau if (edge == GPIO_INT_BOTH_EDGES) 215f948ad07SLinus Torvalds writel(val | (1 << gpio_idx), 216aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 217aeb27748SBenoît Thébaudeau else 218f948ad07SLinus Torvalds writel(val & ~(1 << gpio_idx), 219aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 220aeb27748SBenoît Thébaudeau } 221aeb27748SBenoît Thébaudeau 222aeb27748SBenoît Thébaudeau if (edge != GPIO_INT_BOTH_EDGES) { 223f948ad07SLinus Torvalds reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ 2241ab7ef15SShawn Guo bit = gpio_idx & 0xf; 225b78d8e59SShawn Guo val = readl(reg) & ~(0x3 << (bit << 1)); 226b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 227aeb27748SBenoît Thébaudeau } 228aeb27748SBenoît Thébaudeau 2291ab7ef15SShawn Guo writel(1 << gpio_idx, port->base + GPIO_ISR); 230d37a65bbSShawn Guo 231d37a65bbSShawn Guo return 0; 232d37a65bbSShawn Guo } 233d37a65bbSShawn Guo 234d37a65bbSShawn Guo static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 235d37a65bbSShawn Guo { 236d37a65bbSShawn Guo void __iomem *reg = port->base; 237d37a65bbSShawn Guo u32 bit, val; 238d37a65bbSShawn Guo int edge; 239d37a65bbSShawn Guo 240d37a65bbSShawn Guo reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 241d37a65bbSShawn Guo bit = gpio & 0xf; 242b78d8e59SShawn Guo val = readl(reg); 243d37a65bbSShawn Guo edge = (val >> (bit << 1)) & 3; 244d37a65bbSShawn Guo val &= ~(0x3 << (bit << 1)); 245d37a65bbSShawn Guo if (edge == GPIO_INT_HIGH_LEV) { 246d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 247d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 248d37a65bbSShawn Guo } else if (edge == GPIO_INT_LOW_LEV) { 249d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 250d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 251d37a65bbSShawn Guo } else { 252d37a65bbSShawn Guo pr_err("mxc: invalid configuration for GPIO %d: %x\n", 253d37a65bbSShawn Guo gpio, edge); 254d37a65bbSShawn Guo return; 255d37a65bbSShawn Guo } 256b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 257d37a65bbSShawn Guo } 258d37a65bbSShawn Guo 259d37a65bbSShawn Guo /* handle 32 interrupts in one status register */ 260d37a65bbSShawn Guo static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 261d37a65bbSShawn Guo { 262d37a65bbSShawn Guo while (irq_stat != 0) { 263d37a65bbSShawn Guo int irqoffset = fls(irq_stat) - 1; 264d37a65bbSShawn Guo 265d37a65bbSShawn Guo if (port->both_edges & (1 << irqoffset)) 266d37a65bbSShawn Guo mxc_flip_edge(port, irqoffset); 267d37a65bbSShawn Guo 2681ab7ef15SShawn Guo generic_handle_irq(irq_find_mapping(port->domain, irqoffset)); 269d37a65bbSShawn Guo 270d37a65bbSShawn Guo irq_stat &= ~(1 << irqoffset); 271d37a65bbSShawn Guo } 272d37a65bbSShawn Guo } 273d37a65bbSShawn Guo 274d37a65bbSShawn Guo /* MX1 and MX3 has one interrupt *per* gpio port */ 275bd0b9ac4SThomas Gleixner static void mx3_gpio_irq_handler(struct irq_desc *desc) 276d37a65bbSShawn Guo { 277d37a65bbSShawn Guo u32 irq_stat; 278476f8b4cSJiang Liu struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); 279476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 2800e44b6ecSShawn Guo 2810e44b6ecSShawn Guo chained_irq_enter(chip, desc); 282d37a65bbSShawn Guo 283b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 284d37a65bbSShawn Guo 285d37a65bbSShawn Guo mxc_gpio_irq_handler(port, irq_stat); 2860e44b6ecSShawn Guo 2870e44b6ecSShawn Guo chained_irq_exit(chip, desc); 288d37a65bbSShawn Guo } 289d37a65bbSShawn Guo 290d37a65bbSShawn Guo /* MX2 has one interrupt *for all* gpio ports */ 291bd0b9ac4SThomas Gleixner static void mx2_gpio_irq_handler(struct irq_desc *desc) 292d37a65bbSShawn Guo { 293d37a65bbSShawn Guo u32 irq_msk, irq_stat; 294b78d8e59SShawn Guo struct mxc_gpio_port *port; 295476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 296c0e811d9SUwe Kleine-König 297c0e811d9SUwe Kleine-König chained_irq_enter(chip, desc); 298d37a65bbSShawn Guo 299d37a65bbSShawn Guo /* walk through all interrupt status registers */ 300b78d8e59SShawn Guo list_for_each_entry(port, &mxc_gpio_ports, node) { 301b78d8e59SShawn Guo irq_msk = readl(port->base + GPIO_IMR); 302d37a65bbSShawn Guo if (!irq_msk) 303d37a65bbSShawn Guo continue; 304d37a65bbSShawn Guo 305b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 306d37a65bbSShawn Guo if (irq_stat) 307b78d8e59SShawn Guo mxc_gpio_irq_handler(port, irq_stat); 308d37a65bbSShawn Guo } 309c0e811d9SUwe Kleine-König chained_irq_exit(chip, desc); 310d37a65bbSShawn Guo } 311d37a65bbSShawn Guo 312d37a65bbSShawn Guo /* 313d37a65bbSShawn Guo * Set interrupt number "irq" in the GPIO as a wake-up source. 314d37a65bbSShawn Guo * While system is running, all registered GPIO interrupts need to have 315d37a65bbSShawn Guo * wake-up enabled. When system is suspended, only selected GPIO interrupts 316d37a65bbSShawn Guo * need to have wake-up enabled. 317d37a65bbSShawn Guo * @param irq interrupt source number 318d37a65bbSShawn Guo * @param enable enable as wake-up if equal to non-zero 319d37a65bbSShawn Guo * @return This function returns 0 on success. 320d37a65bbSShawn Guo */ 321d37a65bbSShawn Guo static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 322d37a65bbSShawn Guo { 323e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 324e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 3251ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 32677a4d757SPhilipp Rosenberger int ret; 327d37a65bbSShawn Guo 328d37a65bbSShawn Guo if (enable) { 329d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 33077a4d757SPhilipp Rosenberger ret = enable_irq_wake(port->irq_high); 331d37a65bbSShawn Guo else 33277a4d757SPhilipp Rosenberger ret = enable_irq_wake(port->irq); 333d37a65bbSShawn Guo } else { 334d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 33577a4d757SPhilipp Rosenberger ret = disable_irq_wake(port->irq_high); 336d37a65bbSShawn Guo else 33777a4d757SPhilipp Rosenberger ret = disable_irq_wake(port->irq); 338d37a65bbSShawn Guo } 339d37a65bbSShawn Guo 34077a4d757SPhilipp Rosenberger return ret; 341d37a65bbSShawn Guo } 342d37a65bbSShawn Guo 3439e26b0b1SPeng Fan static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) 344e4ea9333SShawn Guo { 345e4ea9333SShawn Guo struct irq_chip_generic *gc; 346e4ea9333SShawn Guo struct irq_chip_type *ct; 347db5270acSBartosz Golaszewski int rv; 348d37a65bbSShawn Guo 349db5270acSBartosz Golaszewski gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base, 350e4ea9333SShawn Guo port->base, handle_level_irq); 3519e26b0b1SPeng Fan if (!gc) 3529e26b0b1SPeng Fan return -ENOMEM; 353e4ea9333SShawn Guo gc->private = port; 354e4ea9333SShawn Guo 355e4ea9333SShawn Guo ct = gc->chip_types; 356591567a5SShawn Guo ct->chip.irq_ack = irq_gc_ack_set_bit; 357e4ea9333SShawn Guo ct->chip.irq_mask = irq_gc_mask_clr_bit; 358e4ea9333SShawn Guo ct->chip.irq_unmask = irq_gc_mask_set_bit; 359e4ea9333SShawn Guo ct->chip.irq_set_type = gpio_set_irq_type; 360591567a5SShawn Guo ct->chip.irq_set_wake = gpio_set_wake_irq; 361952cfbd3SUlises Brindis ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND; 362e4ea9333SShawn Guo ct->regs.ack = GPIO_ISR; 363e4ea9333SShawn Guo ct->regs.mask = GPIO_IMR; 364e4ea9333SShawn Guo 365db5270acSBartosz Golaszewski rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), 366db5270acSBartosz Golaszewski IRQ_GC_INIT_NESTED_LOCK, 367e4ea9333SShawn Guo IRQ_NOREQUEST, 0); 3689e26b0b1SPeng Fan 369db5270acSBartosz Golaszewski return rv; 370e4ea9333SShawn Guo } 371d37a65bbSShawn Guo 3723836309dSBill Pemberton static void mxc_gpio_get_hw(struct platform_device *pdev) 373e7fc6ae7SShawn Guo { 3748937cb60SShawn Guo const struct of_device_id *of_id = 3758937cb60SShawn Guo of_match_device(mxc_gpio_dt_ids, &pdev->dev); 3768937cb60SShawn Guo enum mxc_gpio_hwtype hwtype; 3778937cb60SShawn Guo 3788937cb60SShawn Guo if (of_id) 3798937cb60SShawn Guo pdev->id_entry = of_id->data; 3808937cb60SShawn Guo hwtype = pdev->id_entry->driver_data; 381e7fc6ae7SShawn Guo 382e7fc6ae7SShawn Guo if (mxc_gpio_hwtype) { 383e7fc6ae7SShawn Guo /* 384e7fc6ae7SShawn Guo * The driver works with a reasonable presupposition, 385e7fc6ae7SShawn Guo * that is all gpio ports must be the same type when 386e7fc6ae7SShawn Guo * running on one soc. 387e7fc6ae7SShawn Guo */ 388e7fc6ae7SShawn Guo BUG_ON(mxc_gpio_hwtype != hwtype); 389e7fc6ae7SShawn Guo return; 390e7fc6ae7SShawn Guo } 391e7fc6ae7SShawn Guo 392aeb27748SBenoît Thébaudeau if (hwtype == IMX35_GPIO) 393aeb27748SBenoît Thébaudeau mxc_gpio_hwdata = &imx35_gpio_hwdata; 394aeb27748SBenoît Thébaudeau else if (hwtype == IMX31_GPIO) 395e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx31_gpio_hwdata; 396e7fc6ae7SShawn Guo else 397e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata; 398e7fc6ae7SShawn Guo 399e7fc6ae7SShawn Guo mxc_gpio_hwtype = hwtype; 400e7fc6ae7SShawn Guo } 401e7fc6ae7SShawn Guo 40209ad8039SShawn Guo static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 40309ad8039SShawn Guo { 4040f4630f3SLinus Walleij struct mxc_gpio_port *port = gpiochip_get_data(gc); 40509ad8039SShawn Guo 4061ab7ef15SShawn Guo return irq_find_mapping(port->domain, offset); 40709ad8039SShawn Guo } 40809ad8039SShawn Guo 4093836309dSBill Pemberton static int mxc_gpio_probe(struct platform_device *pdev) 410d37a65bbSShawn Guo { 4118937cb60SShawn Guo struct device_node *np = pdev->dev.of_node; 412b78d8e59SShawn Guo struct mxc_gpio_port *port; 413b78d8e59SShawn Guo struct resource *iores; 4141ab7ef15SShawn Guo int irq_base; 415e4ea9333SShawn Guo int err; 416d37a65bbSShawn Guo 417e7fc6ae7SShawn Guo mxc_gpio_get_hw(pdev); 418e7fc6ae7SShawn Guo 4198cd73e4eSFabio Estevam port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 420b78d8e59SShawn Guo if (!port) 421b78d8e59SShawn Guo return -ENOMEM; 422d37a65bbSShawn Guo 423db5270acSBartosz Golaszewski port->dev = &pdev->dev; 424db5270acSBartosz Golaszewski 425b78d8e59SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4268cd73e4eSFabio Estevam port->base = devm_ioremap_resource(&pdev->dev, iores); 4278cd73e4eSFabio Estevam if (IS_ERR(port->base)) 4288cd73e4eSFabio Estevam return PTR_ERR(port->base); 429b78d8e59SShawn Guo 430b78d8e59SShawn Guo port->irq_high = platform_get_irq(pdev, 1); 431cc9269f8SPhilipp Rosenberger if (port->irq_high < 0) 432cc9269f8SPhilipp Rosenberger port->irq_high = 0; 433cc9269f8SPhilipp Rosenberger 434b78d8e59SShawn Guo port->irq = platform_get_irq(pdev, 0); 4358cd73e4eSFabio Estevam if (port->irq < 0) 4365ea80e49SSachin Kamat return port->irq; 437b78d8e59SShawn Guo 4382808801aSAnson Huang /* the controller clock is optional */ 4392808801aSAnson Huang port->clk = devm_clk_get(&pdev->dev, NULL); 4402808801aSAnson Huang if (IS_ERR(port->clk)) 4412808801aSAnson Huang port->clk = NULL; 4422808801aSAnson Huang 4432808801aSAnson Huang err = clk_prepare_enable(port->clk); 4442808801aSAnson Huang if (err) { 4452808801aSAnson Huang dev_err(&pdev->dev, "Unable to enable clock.\n"); 4462808801aSAnson Huang return err; 4472808801aSAnson Huang } 4482808801aSAnson Huang 449c19fdaeeSAnson Huang if (of_device_is_compatible(np, "fsl,imx7d-gpio")) 450c19fdaeeSAnson Huang port->power_off = true; 451c19fdaeeSAnson Huang 452d37a65bbSShawn Guo /* disable the interrupt and clear the status */ 453b78d8e59SShawn Guo writel(0, port->base + GPIO_IMR); 454b78d8e59SShawn Guo writel(~0, port->base + GPIO_ISR); 455d37a65bbSShawn Guo 456e7fc6ae7SShawn Guo if (mxc_gpio_hwtype == IMX21_GPIO) { 45733a4e985SUwe Kleine-König /* 45833a4e985SUwe Kleine-König * Setup one handler for all GPIO interrupts. Actually setting 45933a4e985SUwe Kleine-König * the handler is needed only once, but doing it for every port 46033a4e985SUwe Kleine-König * is more robust and easier. 46133a4e985SUwe Kleine-König */ 46233a4e985SUwe Kleine-König irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); 463b78d8e59SShawn Guo } else { 464b78d8e59SShawn Guo /* setup one handler for each entry */ 465e65eea54SRussell King irq_set_chained_handler_and_data(port->irq, 466e65eea54SRussell King mx3_gpio_irq_handler, port); 467e65eea54SRussell King if (port->irq_high > 0) 468b78d8e59SShawn Guo /* setup handler for GPIO 16 to 31 */ 469e65eea54SRussell King irq_set_chained_handler_and_data(port->irq_high, 470e65eea54SRussell King mx3_gpio_irq_handler, 471e65eea54SRussell King port); 472d37a65bbSShawn Guo } 473d37a65bbSShawn Guo 4740f4630f3SLinus Walleij err = bgpio_init(&port->gc, &pdev->dev, 4, 4752ce420daSShawn Guo port->base + GPIO_PSR, 4762ce420daSShawn Guo port->base + GPIO_DR, NULL, 477442b2494SVladimir Zapolskiy port->base + GPIO_GDIR, NULL, 478442b2494SVladimir Zapolskiy BGPIOF_READ_OUTPUT_REG_SET); 479b78d8e59SShawn Guo if (err) 4808cd73e4eSFabio Estevam goto out_bgio; 481b78d8e59SShawn Guo 4824c806c98SVladimir Zapolskiy if (of_property_read_bool(np, "gpio-ranges")) { 4834c806c98SVladimir Zapolskiy port->gc.request = gpiochip_generic_request; 4844c806c98SVladimir Zapolskiy port->gc.free = gpiochip_generic_free; 4854c806c98SVladimir Zapolskiy } 4864c806c98SVladimir Zapolskiy 4870f4630f3SLinus Walleij port->gc.to_irq = mxc_gpio_to_irq; 4880f4630f3SLinus Walleij port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : 4897e6086d9SShawn Guo pdev->id * 32; 4902ce420daSShawn Guo 491ffc56630SLaxman Dewangan err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port); 4922ce420daSShawn Guo if (err) 4930f4630f3SLinus Walleij goto out_bgio; 4942ce420daSShawn Guo 495c553c3c4SBartosz Golaszewski irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); 4961ab7ef15SShawn Guo if (irq_base < 0) { 4971ab7ef15SShawn Guo err = irq_base; 498ffc56630SLaxman Dewangan goto out_bgio; 4991ab7ef15SShawn Guo } 5001ab7ef15SShawn Guo 5011ab7ef15SShawn Guo port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, 5021ab7ef15SShawn Guo &irq_domain_simple_ops, NULL); 5031ab7ef15SShawn Guo if (!port->domain) { 5041ab7ef15SShawn Guo err = -ENODEV; 505c553c3c4SBartosz Golaszewski goto out_bgio; 5061ab7ef15SShawn Guo } 5078937cb60SShawn Guo 5088937cb60SShawn Guo /* gpio-mxc can be a generic irq chip */ 5099e26b0b1SPeng Fan err = mxc_gpio_init_gc(port, irq_base); 5109e26b0b1SPeng Fan if (err < 0) 5119e26b0b1SPeng Fan goto out_irqdomain_remove; 5128937cb60SShawn Guo 513b78d8e59SShawn Guo list_add_tail(&port->node, &mxc_gpio_ports); 514b78d8e59SShawn Guo 515c19fdaeeSAnson Huang platform_set_drvdata(pdev, port); 516c19fdaeeSAnson Huang 517d37a65bbSShawn Guo return 0; 518b78d8e59SShawn Guo 5199e26b0b1SPeng Fan out_irqdomain_remove: 5209e26b0b1SPeng Fan irq_domain_remove(port->domain); 5218cd73e4eSFabio Estevam out_bgio: 5222808801aSAnson Huang clk_disable_unprepare(port->clk); 523b78d8e59SShawn Guo dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 524b78d8e59SShawn Guo return err; 525d37a65bbSShawn Guo } 526b78d8e59SShawn Guo 527c19fdaeeSAnson Huang static void mxc_gpio_save_regs(struct mxc_gpio_port *port) 528c19fdaeeSAnson Huang { 529c19fdaeeSAnson Huang if (!port->power_off) 530c19fdaeeSAnson Huang return; 531c19fdaeeSAnson Huang 532c19fdaeeSAnson Huang port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1); 533c19fdaeeSAnson Huang port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2); 534c19fdaeeSAnson Huang port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR); 535c19fdaeeSAnson Huang port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR); 536c19fdaeeSAnson Huang port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL); 537c19fdaeeSAnson Huang port->gpio_saved_reg.dr = readl(port->base + GPIO_DR); 538c19fdaeeSAnson Huang } 539c19fdaeeSAnson Huang 540c19fdaeeSAnson Huang static void mxc_gpio_restore_regs(struct mxc_gpio_port *port) 541c19fdaeeSAnson Huang { 542c19fdaeeSAnson Huang if (!port->power_off) 543c19fdaeeSAnson Huang return; 544c19fdaeeSAnson Huang 545c19fdaeeSAnson Huang writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1); 546c19fdaeeSAnson Huang writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2); 547c19fdaeeSAnson Huang writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR); 548c19fdaeeSAnson Huang writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR); 549c19fdaeeSAnson Huang writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL); 550c19fdaeeSAnson Huang writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); 551c19fdaeeSAnson Huang } 552c19fdaeeSAnson Huang 553c19fdaeeSAnson Huang static int __maybe_unused mxc_gpio_noirq_suspend(struct device *dev) 554c19fdaeeSAnson Huang { 555c19fdaeeSAnson Huang struct platform_device *pdev = to_platform_device(dev); 556c19fdaeeSAnson Huang struct mxc_gpio_port *port = platform_get_drvdata(pdev); 557c19fdaeeSAnson Huang 558c19fdaeeSAnson Huang mxc_gpio_save_regs(port); 559c19fdaeeSAnson Huang clk_disable_unprepare(port->clk); 560c19fdaeeSAnson Huang 561c19fdaeeSAnson Huang return 0; 562c19fdaeeSAnson Huang } 563c19fdaeeSAnson Huang 564c19fdaeeSAnson Huang static int __maybe_unused mxc_gpio_noirq_resume(struct device *dev) 565c19fdaeeSAnson Huang { 566c19fdaeeSAnson Huang struct platform_device *pdev = to_platform_device(dev); 567c19fdaeeSAnson Huang struct mxc_gpio_port *port = platform_get_drvdata(pdev); 568c19fdaeeSAnson Huang int ret; 569c19fdaeeSAnson Huang 570c19fdaeeSAnson Huang ret = clk_prepare_enable(port->clk); 571c19fdaeeSAnson Huang if (ret) 572c19fdaeeSAnson Huang return ret; 573c19fdaeeSAnson Huang mxc_gpio_restore_regs(port); 574c19fdaeeSAnson Huang 575c19fdaeeSAnson Huang return 0; 576c19fdaeeSAnson Huang } 577c19fdaeeSAnson Huang 578c19fdaeeSAnson Huang static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { 579c19fdaeeSAnson Huang SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume) 580c19fdaeeSAnson Huang }; 581c19fdaeeSAnson Huang 582b78d8e59SShawn Guo static struct platform_driver mxc_gpio_driver = { 583b78d8e59SShawn Guo .driver = { 584b78d8e59SShawn Guo .name = "gpio-mxc", 5858937cb60SShawn Guo .of_match_table = mxc_gpio_dt_ids, 58690e1fc4cSBartosz Golaszewski .suppress_bind_attrs = true, 587c19fdaeeSAnson Huang .pm = &mxc_gpio_dev_pm_ops, 588b78d8e59SShawn Guo }, 589b78d8e59SShawn Guo .probe = mxc_gpio_probe, 590e7fc6ae7SShawn Guo .id_table = mxc_gpio_devtype, 591b78d8e59SShawn Guo }; 592b78d8e59SShawn Guo 593b78d8e59SShawn Guo static int __init gpio_mxc_init(void) 594b78d8e59SShawn Guo { 595b78d8e59SShawn Guo return platform_driver_register(&mxc_gpio_driver); 596b78d8e59SShawn Guo } 597e188cbf7SVladimir Zapolskiy subsys_initcall(gpio_mxc_init); 598