1d37a65bbSShawn Guo /* 2d37a65bbSShawn Guo * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 3d37a65bbSShawn Guo * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 4d37a65bbSShawn Guo * 52c8d6c86SPaul Gortmaker * Based on code from Freescale Semiconductor, 62c8d6c86SPaul Gortmaker * Authors: Daniel Mack, Juergen Beisert. 7d37a65bbSShawn Guo * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 8d37a65bbSShawn Guo * 9d37a65bbSShawn Guo * This program is free software; you can redistribute it and/or 10d37a65bbSShawn Guo * modify it under the terms of the GNU General Public License 11d37a65bbSShawn Guo * as published by the Free Software Foundation; either version 2 12d37a65bbSShawn Guo * of the License, or (at your option) any later version. 13d37a65bbSShawn Guo * This program is distributed in the hope that it will be useful, 14d37a65bbSShawn Guo * but WITHOUT ANY WARRANTY; without even the implied warranty of 15d37a65bbSShawn Guo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16d37a65bbSShawn Guo * GNU General Public License for more details. 17d37a65bbSShawn Guo * 18d37a65bbSShawn Guo * You should have received a copy of the GNU General Public License 19d37a65bbSShawn Guo * along with this program; if not, write to the Free Software 20d37a65bbSShawn Guo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 21d37a65bbSShawn Guo */ 22d37a65bbSShawn Guo 2318f92b19SFabio Estevam #include <linux/err.h> 24d37a65bbSShawn Guo #include <linux/init.h> 25d37a65bbSShawn Guo #include <linux/interrupt.h> 26d37a65bbSShawn Guo #include <linux/io.h> 27d37a65bbSShawn Guo #include <linux/irq.h> 281ab7ef15SShawn Guo #include <linux/irqdomain.h> 29de88cbb7SCatalin Marinas #include <linux/irqchip/chained_irq.h> 30b78d8e59SShawn Guo #include <linux/platform_device.h> 31b78d8e59SShawn Guo #include <linux/slab.h> 320f4630f3SLinus Walleij #include <linux/gpio/driver.h> 338937cb60SShawn Guo #include <linux/of.h> 348937cb60SShawn Guo #include <linux/of_device.h> 3516c3bd35SChristoph Hellwig #include <linux/bug.h> 36d37a65bbSShawn Guo 37e7fc6ae7SShawn Guo enum mxc_gpio_hwtype { 38e7fc6ae7SShawn Guo IMX1_GPIO, /* runs on i.mx1 */ 39e7fc6ae7SShawn Guo IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ 40aeb27748SBenoît Thébaudeau IMX31_GPIO, /* runs on i.mx31 */ 41aeb27748SBenoît Thébaudeau IMX35_GPIO, /* runs on all other i.mx */ 42e7fc6ae7SShawn Guo }; 43e7fc6ae7SShawn Guo 44e7fc6ae7SShawn Guo /* device type dependent stuff */ 45e7fc6ae7SShawn Guo struct mxc_gpio_hwdata { 46e7fc6ae7SShawn Guo unsigned dr_reg; 47e7fc6ae7SShawn Guo unsigned gdir_reg; 48e7fc6ae7SShawn Guo unsigned psr_reg; 49e7fc6ae7SShawn Guo unsigned icr1_reg; 50e7fc6ae7SShawn Guo unsigned icr2_reg; 51e7fc6ae7SShawn Guo unsigned imr_reg; 52e7fc6ae7SShawn Guo unsigned isr_reg; 53aeb27748SBenoît Thébaudeau int edge_sel_reg; 54e7fc6ae7SShawn Guo unsigned low_level; 55e7fc6ae7SShawn Guo unsigned high_level; 56e7fc6ae7SShawn Guo unsigned rise_edge; 57e7fc6ae7SShawn Guo unsigned fall_edge; 58e7fc6ae7SShawn Guo }; 59e7fc6ae7SShawn Guo 60b78d8e59SShawn Guo struct mxc_gpio_port { 61b78d8e59SShawn Guo struct list_head node; 62b78d8e59SShawn Guo void __iomem *base; 63b78d8e59SShawn Guo int irq; 64b78d8e59SShawn Guo int irq_high; 651ab7ef15SShawn Guo struct irq_domain *domain; 660f4630f3SLinus Walleij struct gpio_chip gc; 67db5270acSBartosz Golaszewski struct device *dev; 68b78d8e59SShawn Guo u32 both_edges; 69b78d8e59SShawn Guo }; 70b78d8e59SShawn Guo 71e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 72e7fc6ae7SShawn Guo .dr_reg = 0x1c, 73e7fc6ae7SShawn Guo .gdir_reg = 0x00, 74e7fc6ae7SShawn Guo .psr_reg = 0x24, 75e7fc6ae7SShawn Guo .icr1_reg = 0x28, 76e7fc6ae7SShawn Guo .icr2_reg = 0x2c, 77e7fc6ae7SShawn Guo .imr_reg = 0x30, 78e7fc6ae7SShawn Guo .isr_reg = 0x34, 79aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 80e7fc6ae7SShawn Guo .low_level = 0x03, 81e7fc6ae7SShawn Guo .high_level = 0x02, 82e7fc6ae7SShawn Guo .rise_edge = 0x00, 83e7fc6ae7SShawn Guo .fall_edge = 0x01, 84e7fc6ae7SShawn Guo }; 85e7fc6ae7SShawn Guo 86e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 87e7fc6ae7SShawn Guo .dr_reg = 0x00, 88e7fc6ae7SShawn Guo .gdir_reg = 0x04, 89e7fc6ae7SShawn Guo .psr_reg = 0x08, 90e7fc6ae7SShawn Guo .icr1_reg = 0x0c, 91e7fc6ae7SShawn Guo .icr2_reg = 0x10, 92e7fc6ae7SShawn Guo .imr_reg = 0x14, 93e7fc6ae7SShawn Guo .isr_reg = 0x18, 94aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 95aeb27748SBenoît Thébaudeau .low_level = 0x00, 96aeb27748SBenoît Thébaudeau .high_level = 0x01, 97aeb27748SBenoît Thébaudeau .rise_edge = 0x02, 98aeb27748SBenoît Thébaudeau .fall_edge = 0x03, 99aeb27748SBenoît Thébaudeau }; 100aeb27748SBenoît Thébaudeau 101aeb27748SBenoît Thébaudeau static struct mxc_gpio_hwdata imx35_gpio_hwdata = { 102aeb27748SBenoît Thébaudeau .dr_reg = 0x00, 103aeb27748SBenoît Thébaudeau .gdir_reg = 0x04, 104aeb27748SBenoît Thébaudeau .psr_reg = 0x08, 105aeb27748SBenoît Thébaudeau .icr1_reg = 0x0c, 106aeb27748SBenoît Thébaudeau .icr2_reg = 0x10, 107aeb27748SBenoît Thébaudeau .imr_reg = 0x14, 108aeb27748SBenoît Thébaudeau .isr_reg = 0x18, 109aeb27748SBenoît Thébaudeau .edge_sel_reg = 0x1c, 110e7fc6ae7SShawn Guo .low_level = 0x00, 111e7fc6ae7SShawn Guo .high_level = 0x01, 112e7fc6ae7SShawn Guo .rise_edge = 0x02, 113e7fc6ae7SShawn Guo .fall_edge = 0x03, 114e7fc6ae7SShawn Guo }; 115e7fc6ae7SShawn Guo 116e7fc6ae7SShawn Guo static enum mxc_gpio_hwtype mxc_gpio_hwtype; 117e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata *mxc_gpio_hwdata; 118e7fc6ae7SShawn Guo 119e7fc6ae7SShawn Guo #define GPIO_DR (mxc_gpio_hwdata->dr_reg) 120e7fc6ae7SShawn Guo #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg) 121e7fc6ae7SShawn Guo #define GPIO_PSR (mxc_gpio_hwdata->psr_reg) 122e7fc6ae7SShawn Guo #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg) 123e7fc6ae7SShawn Guo #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg) 124e7fc6ae7SShawn Guo #define GPIO_IMR (mxc_gpio_hwdata->imr_reg) 125e7fc6ae7SShawn Guo #define GPIO_ISR (mxc_gpio_hwdata->isr_reg) 126aeb27748SBenoît Thébaudeau #define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg) 127e7fc6ae7SShawn Guo 128e7fc6ae7SShawn Guo #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level) 129e7fc6ae7SShawn Guo #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level) 130e7fc6ae7SShawn Guo #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge) 131e7fc6ae7SShawn Guo #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge) 132aeb27748SBenoît Thébaudeau #define GPIO_INT_BOTH_EDGES 0x4 133e7fc6ae7SShawn Guo 134f4f79d40SKrzysztof Kozlowski static const struct platform_device_id mxc_gpio_devtype[] = { 135e7fc6ae7SShawn Guo { 136e7fc6ae7SShawn Guo .name = "imx1-gpio", 137e7fc6ae7SShawn Guo .driver_data = IMX1_GPIO, 138e7fc6ae7SShawn Guo }, { 139e7fc6ae7SShawn Guo .name = "imx21-gpio", 140e7fc6ae7SShawn Guo .driver_data = IMX21_GPIO, 141e7fc6ae7SShawn Guo }, { 142e7fc6ae7SShawn Guo .name = "imx31-gpio", 143e7fc6ae7SShawn Guo .driver_data = IMX31_GPIO, 144e7fc6ae7SShawn Guo }, { 145aeb27748SBenoît Thébaudeau .name = "imx35-gpio", 146aeb27748SBenoît Thébaudeau .driver_data = IMX35_GPIO, 147aeb27748SBenoît Thébaudeau }, { 148e7fc6ae7SShawn Guo /* sentinel */ 149e7fc6ae7SShawn Guo } 150e7fc6ae7SShawn Guo }; 151e7fc6ae7SShawn Guo 1528937cb60SShawn Guo static const struct of_device_id mxc_gpio_dt_ids[] = { 1538937cb60SShawn Guo { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], }, 1548937cb60SShawn Guo { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], }, 1558937cb60SShawn Guo { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], }, 156aeb27748SBenoît Thébaudeau { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], }, 1578937cb60SShawn Guo { /* sentinel */ } 1588937cb60SShawn Guo }; 1598937cb60SShawn Guo 160b78d8e59SShawn Guo /* 161b78d8e59SShawn Guo * MX2 has one interrupt *for all* gpio ports. The list is used 162b78d8e59SShawn Guo * to save the references to all ports, so that mx2_gpio_irq_handler 163b78d8e59SShawn Guo * can walk through all interrupt status registers. 164b78d8e59SShawn Guo */ 165b78d8e59SShawn Guo static LIST_HEAD(mxc_gpio_ports); 166d37a65bbSShawn Guo 167d37a65bbSShawn Guo /* Note: This driver assumes 32 GPIOs are handled in one register */ 168d37a65bbSShawn Guo 169d37a65bbSShawn Guo static int gpio_set_irq_type(struct irq_data *d, u32 type) 170d37a65bbSShawn Guo { 171e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 172e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 173d37a65bbSShawn Guo u32 bit, val; 1741ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 175d37a65bbSShawn Guo int edge; 176d37a65bbSShawn Guo void __iomem *reg = port->base; 177d37a65bbSShawn Guo 1781ab7ef15SShawn Guo port->both_edges &= ~(1 << gpio_idx); 179d37a65bbSShawn Guo switch (type) { 180d37a65bbSShawn Guo case IRQ_TYPE_EDGE_RISING: 181d37a65bbSShawn Guo edge = GPIO_INT_RISE_EDGE; 182d37a65bbSShawn Guo break; 183d37a65bbSShawn Guo case IRQ_TYPE_EDGE_FALLING: 184d37a65bbSShawn Guo edge = GPIO_INT_FALL_EDGE; 185d37a65bbSShawn Guo break; 186d37a65bbSShawn Guo case IRQ_TYPE_EDGE_BOTH: 187aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 188aeb27748SBenoît Thébaudeau edge = GPIO_INT_BOTH_EDGES; 189aeb27748SBenoît Thébaudeau } else { 1908d0bd9a5SLinus Walleij val = port->gc.get(&port->gc, gpio_idx); 191d37a65bbSShawn Guo if (val) { 192d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 1938d0bd9a5SLinus Walleij pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx); 194d37a65bbSShawn Guo } else { 195d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 1968d0bd9a5SLinus Walleij pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx); 197d37a65bbSShawn Guo } 1981ab7ef15SShawn Guo port->both_edges |= 1 << gpio_idx; 199aeb27748SBenoît Thébaudeau } 200d37a65bbSShawn Guo break; 201d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_LOW: 202d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 203d37a65bbSShawn Guo break; 204d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_HIGH: 205d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 206d37a65bbSShawn Guo break; 207d37a65bbSShawn Guo default: 208d37a65bbSShawn Guo return -EINVAL; 209d37a65bbSShawn Guo } 210d37a65bbSShawn Guo 211aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 212aeb27748SBenoît Thébaudeau val = readl(port->base + GPIO_EDGE_SEL); 213aeb27748SBenoît Thébaudeau if (edge == GPIO_INT_BOTH_EDGES) 214f948ad07SLinus Torvalds writel(val | (1 << gpio_idx), 215aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 216aeb27748SBenoît Thébaudeau else 217f948ad07SLinus Torvalds writel(val & ~(1 << gpio_idx), 218aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 219aeb27748SBenoît Thébaudeau } 220aeb27748SBenoît Thébaudeau 221aeb27748SBenoît Thébaudeau if (edge != GPIO_INT_BOTH_EDGES) { 222f948ad07SLinus Torvalds reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ 2231ab7ef15SShawn Guo bit = gpio_idx & 0xf; 224b78d8e59SShawn Guo val = readl(reg) & ~(0x3 << (bit << 1)); 225b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 226aeb27748SBenoît Thébaudeau } 227aeb27748SBenoît Thébaudeau 2281ab7ef15SShawn Guo writel(1 << gpio_idx, port->base + GPIO_ISR); 229d37a65bbSShawn Guo 230d37a65bbSShawn Guo return 0; 231d37a65bbSShawn Guo } 232d37a65bbSShawn Guo 233d37a65bbSShawn Guo static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 234d37a65bbSShawn Guo { 235d37a65bbSShawn Guo void __iomem *reg = port->base; 236d37a65bbSShawn Guo u32 bit, val; 237d37a65bbSShawn Guo int edge; 238d37a65bbSShawn Guo 239d37a65bbSShawn Guo reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 240d37a65bbSShawn Guo bit = gpio & 0xf; 241b78d8e59SShawn Guo val = readl(reg); 242d37a65bbSShawn Guo edge = (val >> (bit << 1)) & 3; 243d37a65bbSShawn Guo val &= ~(0x3 << (bit << 1)); 244d37a65bbSShawn Guo if (edge == GPIO_INT_HIGH_LEV) { 245d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 246d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 247d37a65bbSShawn Guo } else if (edge == GPIO_INT_LOW_LEV) { 248d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 249d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 250d37a65bbSShawn Guo } else { 251d37a65bbSShawn Guo pr_err("mxc: invalid configuration for GPIO %d: %x\n", 252d37a65bbSShawn Guo gpio, edge); 253d37a65bbSShawn Guo return; 254d37a65bbSShawn Guo } 255b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 256d37a65bbSShawn Guo } 257d37a65bbSShawn Guo 258d37a65bbSShawn Guo /* handle 32 interrupts in one status register */ 259d37a65bbSShawn Guo static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 260d37a65bbSShawn Guo { 261d37a65bbSShawn Guo while (irq_stat != 0) { 262d37a65bbSShawn Guo int irqoffset = fls(irq_stat) - 1; 263d37a65bbSShawn Guo 264d37a65bbSShawn Guo if (port->both_edges & (1 << irqoffset)) 265d37a65bbSShawn Guo mxc_flip_edge(port, irqoffset); 266d37a65bbSShawn Guo 2671ab7ef15SShawn Guo generic_handle_irq(irq_find_mapping(port->domain, irqoffset)); 268d37a65bbSShawn Guo 269d37a65bbSShawn Guo irq_stat &= ~(1 << irqoffset); 270d37a65bbSShawn Guo } 271d37a65bbSShawn Guo } 272d37a65bbSShawn Guo 273d37a65bbSShawn Guo /* MX1 and MX3 has one interrupt *per* gpio port */ 274bd0b9ac4SThomas Gleixner static void mx3_gpio_irq_handler(struct irq_desc *desc) 275d37a65bbSShawn Guo { 276d37a65bbSShawn Guo u32 irq_stat; 277476f8b4cSJiang Liu struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); 278476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 2790e44b6ecSShawn Guo 2800e44b6ecSShawn Guo chained_irq_enter(chip, desc); 281d37a65bbSShawn Guo 282b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 283d37a65bbSShawn Guo 284d37a65bbSShawn Guo mxc_gpio_irq_handler(port, irq_stat); 2850e44b6ecSShawn Guo 2860e44b6ecSShawn Guo chained_irq_exit(chip, desc); 287d37a65bbSShawn Guo } 288d37a65bbSShawn Guo 289d37a65bbSShawn Guo /* MX2 has one interrupt *for all* gpio ports */ 290bd0b9ac4SThomas Gleixner static void mx2_gpio_irq_handler(struct irq_desc *desc) 291d37a65bbSShawn Guo { 292d37a65bbSShawn Guo u32 irq_msk, irq_stat; 293b78d8e59SShawn Guo struct mxc_gpio_port *port; 294476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 295c0e811d9SUwe Kleine-König 296c0e811d9SUwe Kleine-König chained_irq_enter(chip, desc); 297d37a65bbSShawn Guo 298d37a65bbSShawn Guo /* walk through all interrupt status registers */ 299b78d8e59SShawn Guo list_for_each_entry(port, &mxc_gpio_ports, node) { 300b78d8e59SShawn Guo irq_msk = readl(port->base + GPIO_IMR); 301d37a65bbSShawn Guo if (!irq_msk) 302d37a65bbSShawn Guo continue; 303d37a65bbSShawn Guo 304b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 305d37a65bbSShawn Guo if (irq_stat) 306b78d8e59SShawn Guo mxc_gpio_irq_handler(port, irq_stat); 307d37a65bbSShawn Guo } 308c0e811d9SUwe Kleine-König chained_irq_exit(chip, desc); 309d37a65bbSShawn Guo } 310d37a65bbSShawn Guo 311d37a65bbSShawn Guo /* 312d37a65bbSShawn Guo * Set interrupt number "irq" in the GPIO as a wake-up source. 313d37a65bbSShawn Guo * While system is running, all registered GPIO interrupts need to have 314d37a65bbSShawn Guo * wake-up enabled. When system is suspended, only selected GPIO interrupts 315d37a65bbSShawn Guo * need to have wake-up enabled. 316d37a65bbSShawn Guo * @param irq interrupt source number 317d37a65bbSShawn Guo * @param enable enable as wake-up if equal to non-zero 318d37a65bbSShawn Guo * @return This function returns 0 on success. 319d37a65bbSShawn Guo */ 320d37a65bbSShawn Guo static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 321d37a65bbSShawn Guo { 322e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 323e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 3241ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 32577a4d757SPhilipp Rosenberger int ret; 326d37a65bbSShawn Guo 327d37a65bbSShawn Guo if (enable) { 328d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 32977a4d757SPhilipp Rosenberger ret = enable_irq_wake(port->irq_high); 330d37a65bbSShawn Guo else 33177a4d757SPhilipp Rosenberger ret = enable_irq_wake(port->irq); 332d37a65bbSShawn Guo } else { 333d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 33477a4d757SPhilipp Rosenberger ret = disable_irq_wake(port->irq_high); 335d37a65bbSShawn Guo else 33677a4d757SPhilipp Rosenberger ret = disable_irq_wake(port->irq); 337d37a65bbSShawn Guo } 338d37a65bbSShawn Guo 33977a4d757SPhilipp Rosenberger return ret; 340d37a65bbSShawn Guo } 341d37a65bbSShawn Guo 3429e26b0b1SPeng Fan static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) 343e4ea9333SShawn Guo { 344e4ea9333SShawn Guo struct irq_chip_generic *gc; 345e4ea9333SShawn Guo struct irq_chip_type *ct; 346db5270acSBartosz Golaszewski int rv; 347d37a65bbSShawn Guo 348db5270acSBartosz Golaszewski gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base, 349e4ea9333SShawn Guo port->base, handle_level_irq); 3509e26b0b1SPeng Fan if (!gc) 3519e26b0b1SPeng Fan return -ENOMEM; 352e4ea9333SShawn Guo gc->private = port; 353e4ea9333SShawn Guo 354e4ea9333SShawn Guo ct = gc->chip_types; 355591567a5SShawn Guo ct->chip.irq_ack = irq_gc_ack_set_bit; 356e4ea9333SShawn Guo ct->chip.irq_mask = irq_gc_mask_clr_bit; 357e4ea9333SShawn Guo ct->chip.irq_unmask = irq_gc_mask_set_bit; 358e4ea9333SShawn Guo ct->chip.irq_set_type = gpio_set_irq_type; 359591567a5SShawn Guo ct->chip.irq_set_wake = gpio_set_wake_irq; 360952cfbd3SUlises Brindis ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND; 361e4ea9333SShawn Guo ct->regs.ack = GPIO_ISR; 362e4ea9333SShawn Guo ct->regs.mask = GPIO_IMR; 363e4ea9333SShawn Guo 364db5270acSBartosz Golaszewski rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), 365db5270acSBartosz Golaszewski IRQ_GC_INIT_NESTED_LOCK, 366e4ea9333SShawn Guo IRQ_NOREQUEST, 0); 3679e26b0b1SPeng Fan 368db5270acSBartosz Golaszewski return rv; 369e4ea9333SShawn Guo } 370d37a65bbSShawn Guo 3713836309dSBill Pemberton static void mxc_gpio_get_hw(struct platform_device *pdev) 372e7fc6ae7SShawn Guo { 3738937cb60SShawn Guo const struct of_device_id *of_id = 3748937cb60SShawn Guo of_match_device(mxc_gpio_dt_ids, &pdev->dev); 3758937cb60SShawn Guo enum mxc_gpio_hwtype hwtype; 3768937cb60SShawn Guo 3778937cb60SShawn Guo if (of_id) 3788937cb60SShawn Guo pdev->id_entry = of_id->data; 3798937cb60SShawn Guo hwtype = pdev->id_entry->driver_data; 380e7fc6ae7SShawn Guo 381e7fc6ae7SShawn Guo if (mxc_gpio_hwtype) { 382e7fc6ae7SShawn Guo /* 383e7fc6ae7SShawn Guo * The driver works with a reasonable presupposition, 384e7fc6ae7SShawn Guo * that is all gpio ports must be the same type when 385e7fc6ae7SShawn Guo * running on one soc. 386e7fc6ae7SShawn Guo */ 387e7fc6ae7SShawn Guo BUG_ON(mxc_gpio_hwtype != hwtype); 388e7fc6ae7SShawn Guo return; 389e7fc6ae7SShawn Guo } 390e7fc6ae7SShawn Guo 391aeb27748SBenoît Thébaudeau if (hwtype == IMX35_GPIO) 392aeb27748SBenoît Thébaudeau mxc_gpio_hwdata = &imx35_gpio_hwdata; 393aeb27748SBenoît Thébaudeau else if (hwtype == IMX31_GPIO) 394e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx31_gpio_hwdata; 395e7fc6ae7SShawn Guo else 396e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata; 397e7fc6ae7SShawn Guo 398e7fc6ae7SShawn Guo mxc_gpio_hwtype = hwtype; 399e7fc6ae7SShawn Guo } 400e7fc6ae7SShawn Guo 40109ad8039SShawn Guo static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 40209ad8039SShawn Guo { 4030f4630f3SLinus Walleij struct mxc_gpio_port *port = gpiochip_get_data(gc); 40409ad8039SShawn Guo 4051ab7ef15SShawn Guo return irq_find_mapping(port->domain, offset); 40609ad8039SShawn Guo } 40709ad8039SShawn Guo 4083836309dSBill Pemberton static int mxc_gpio_probe(struct platform_device *pdev) 409d37a65bbSShawn Guo { 4108937cb60SShawn Guo struct device_node *np = pdev->dev.of_node; 411b78d8e59SShawn Guo struct mxc_gpio_port *port; 412b78d8e59SShawn Guo struct resource *iores; 4131ab7ef15SShawn Guo int irq_base; 414e4ea9333SShawn Guo int err; 415d37a65bbSShawn Guo 416e7fc6ae7SShawn Guo mxc_gpio_get_hw(pdev); 417e7fc6ae7SShawn Guo 4188cd73e4eSFabio Estevam port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 419b78d8e59SShawn Guo if (!port) 420b78d8e59SShawn Guo return -ENOMEM; 421d37a65bbSShawn Guo 422db5270acSBartosz Golaszewski port->dev = &pdev->dev; 423db5270acSBartosz Golaszewski 424b78d8e59SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4258cd73e4eSFabio Estevam port->base = devm_ioremap_resource(&pdev->dev, iores); 4268cd73e4eSFabio Estevam if (IS_ERR(port->base)) 4278cd73e4eSFabio Estevam return PTR_ERR(port->base); 428b78d8e59SShawn Guo 429b78d8e59SShawn Guo port->irq_high = platform_get_irq(pdev, 1); 430cc9269f8SPhilipp Rosenberger if (port->irq_high < 0) 431cc9269f8SPhilipp Rosenberger port->irq_high = 0; 432cc9269f8SPhilipp Rosenberger 433b78d8e59SShawn Guo port->irq = platform_get_irq(pdev, 0); 4348cd73e4eSFabio Estevam if (port->irq < 0) 4355ea80e49SSachin Kamat return port->irq; 436b78d8e59SShawn Guo 437d37a65bbSShawn Guo /* disable the interrupt and clear the status */ 438b78d8e59SShawn Guo writel(0, port->base + GPIO_IMR); 439b78d8e59SShawn Guo writel(~0, port->base + GPIO_ISR); 440d37a65bbSShawn Guo 441e7fc6ae7SShawn Guo if (mxc_gpio_hwtype == IMX21_GPIO) { 44233a4e985SUwe Kleine-König /* 44333a4e985SUwe Kleine-König * Setup one handler for all GPIO interrupts. Actually setting 44433a4e985SUwe Kleine-König * the handler is needed only once, but doing it for every port 44533a4e985SUwe Kleine-König * is more robust and easier. 44633a4e985SUwe Kleine-König */ 44733a4e985SUwe Kleine-König irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); 448b78d8e59SShawn Guo } else { 449b78d8e59SShawn Guo /* setup one handler for each entry */ 450e65eea54SRussell King irq_set_chained_handler_and_data(port->irq, 451e65eea54SRussell King mx3_gpio_irq_handler, port); 452e65eea54SRussell King if (port->irq_high > 0) 453b78d8e59SShawn Guo /* setup handler for GPIO 16 to 31 */ 454e65eea54SRussell King irq_set_chained_handler_and_data(port->irq_high, 455e65eea54SRussell King mx3_gpio_irq_handler, 456e65eea54SRussell King port); 457d37a65bbSShawn Guo } 458d37a65bbSShawn Guo 4590f4630f3SLinus Walleij err = bgpio_init(&port->gc, &pdev->dev, 4, 4602ce420daSShawn Guo port->base + GPIO_PSR, 4612ce420daSShawn Guo port->base + GPIO_DR, NULL, 462442b2494SVladimir Zapolskiy port->base + GPIO_GDIR, NULL, 463442b2494SVladimir Zapolskiy BGPIOF_READ_OUTPUT_REG_SET); 464b78d8e59SShawn Guo if (err) 4658cd73e4eSFabio Estevam goto out_bgio; 466b78d8e59SShawn Guo 4674c806c98SVladimir Zapolskiy if (of_property_read_bool(np, "gpio-ranges")) { 4684c806c98SVladimir Zapolskiy port->gc.request = gpiochip_generic_request; 4694c806c98SVladimir Zapolskiy port->gc.free = gpiochip_generic_free; 4704c806c98SVladimir Zapolskiy } 4714c806c98SVladimir Zapolskiy 4720f4630f3SLinus Walleij port->gc.to_irq = mxc_gpio_to_irq; 4730f4630f3SLinus Walleij port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : 4747e6086d9SShawn Guo pdev->id * 32; 4752ce420daSShawn Guo 476ffc56630SLaxman Dewangan err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port); 4772ce420daSShawn Guo if (err) 4780f4630f3SLinus Walleij goto out_bgio; 4792ce420daSShawn Guo 480c553c3c4SBartosz Golaszewski irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); 4811ab7ef15SShawn Guo if (irq_base < 0) { 4821ab7ef15SShawn Guo err = irq_base; 483ffc56630SLaxman Dewangan goto out_bgio; 4841ab7ef15SShawn Guo } 4851ab7ef15SShawn Guo 4861ab7ef15SShawn Guo port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, 4871ab7ef15SShawn Guo &irq_domain_simple_ops, NULL); 4881ab7ef15SShawn Guo if (!port->domain) { 4891ab7ef15SShawn Guo err = -ENODEV; 490c553c3c4SBartosz Golaszewski goto out_bgio; 4911ab7ef15SShawn Guo } 4928937cb60SShawn Guo 4938937cb60SShawn Guo /* gpio-mxc can be a generic irq chip */ 4949e26b0b1SPeng Fan err = mxc_gpio_init_gc(port, irq_base); 4959e26b0b1SPeng Fan if (err < 0) 4969e26b0b1SPeng Fan goto out_irqdomain_remove; 4978937cb60SShawn Guo 498b78d8e59SShawn Guo list_add_tail(&port->node, &mxc_gpio_ports); 499b78d8e59SShawn Guo 500d37a65bbSShawn Guo return 0; 501b78d8e59SShawn Guo 5029e26b0b1SPeng Fan out_irqdomain_remove: 5039e26b0b1SPeng Fan irq_domain_remove(port->domain); 5048cd73e4eSFabio Estevam out_bgio: 505b78d8e59SShawn Guo dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 506b78d8e59SShawn Guo return err; 507d37a65bbSShawn Guo } 508b78d8e59SShawn Guo 509b78d8e59SShawn Guo static struct platform_driver mxc_gpio_driver = { 510b78d8e59SShawn Guo .driver = { 511b78d8e59SShawn Guo .name = "gpio-mxc", 5128937cb60SShawn Guo .of_match_table = mxc_gpio_dt_ids, 51390e1fc4cSBartosz Golaszewski .suppress_bind_attrs = true, 514b78d8e59SShawn Guo }, 515b78d8e59SShawn Guo .probe = mxc_gpio_probe, 516e7fc6ae7SShawn Guo .id_table = mxc_gpio_devtype, 517b78d8e59SShawn Guo }; 518b78d8e59SShawn Guo 519b78d8e59SShawn Guo static int __init gpio_mxc_init(void) 520b78d8e59SShawn Guo { 521b78d8e59SShawn Guo return platform_driver_register(&mxc_gpio_driver); 522b78d8e59SShawn Guo } 523e188cbf7SVladimir Zapolskiy subsys_initcall(gpio_mxc_init); 524