1d37a65bbSShawn Guo /* 2d37a65bbSShawn Guo * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 3d37a65bbSShawn Guo * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 4d37a65bbSShawn Guo * 5d37a65bbSShawn Guo * Based on code from Freescale, 6d37a65bbSShawn Guo * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 7d37a65bbSShawn Guo * 8d37a65bbSShawn Guo * This program is free software; you can redistribute it and/or 9d37a65bbSShawn Guo * modify it under the terms of the GNU General Public License 10d37a65bbSShawn Guo * as published by the Free Software Foundation; either version 2 11d37a65bbSShawn Guo * of the License, or (at your option) any later version. 12d37a65bbSShawn Guo * This program is distributed in the hope that it will be useful, 13d37a65bbSShawn Guo * but WITHOUT ANY WARRANTY; without even the implied warranty of 14d37a65bbSShawn Guo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15d37a65bbSShawn Guo * GNU General Public License for more details. 16d37a65bbSShawn Guo * 17d37a65bbSShawn Guo * You should have received a copy of the GNU General Public License 18d37a65bbSShawn Guo * along with this program; if not, write to the Free Software 19d37a65bbSShawn Guo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 20d37a65bbSShawn Guo */ 21d37a65bbSShawn Guo 22d37a65bbSShawn Guo #include <linux/init.h> 23d37a65bbSShawn Guo #include <linux/interrupt.h> 24d37a65bbSShawn Guo #include <linux/io.h> 25d37a65bbSShawn Guo #include <linux/irq.h> 26d37a65bbSShawn Guo #include <linux/gpio.h> 27b78d8e59SShawn Guo #include <linux/platform_device.h> 28b78d8e59SShawn Guo #include <linux/slab.h> 292ce420daSShawn Guo #include <linux/basic_mmio_gpio.h> 308937cb60SShawn Guo #include <linux/of.h> 318937cb60SShawn Guo #include <linux/of_device.h> 32d37a65bbSShawn Guo #include <asm-generic/bug.h> 33d37a65bbSShawn Guo 34e7fc6ae7SShawn Guo enum mxc_gpio_hwtype { 35e7fc6ae7SShawn Guo IMX1_GPIO, /* runs on i.mx1 */ 36e7fc6ae7SShawn Guo IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ 37e7fc6ae7SShawn Guo IMX31_GPIO, /* runs on all other i.mx */ 38e7fc6ae7SShawn Guo }; 39e7fc6ae7SShawn Guo 40e7fc6ae7SShawn Guo /* device type dependent stuff */ 41e7fc6ae7SShawn Guo struct mxc_gpio_hwdata { 42e7fc6ae7SShawn Guo unsigned dr_reg; 43e7fc6ae7SShawn Guo unsigned gdir_reg; 44e7fc6ae7SShawn Guo unsigned psr_reg; 45e7fc6ae7SShawn Guo unsigned icr1_reg; 46e7fc6ae7SShawn Guo unsigned icr2_reg; 47e7fc6ae7SShawn Guo unsigned imr_reg; 48e7fc6ae7SShawn Guo unsigned isr_reg; 49e7fc6ae7SShawn Guo unsigned low_level; 50e7fc6ae7SShawn Guo unsigned high_level; 51e7fc6ae7SShawn Guo unsigned rise_edge; 52e7fc6ae7SShawn Guo unsigned fall_edge; 53e7fc6ae7SShawn Guo }; 54e7fc6ae7SShawn Guo 55b78d8e59SShawn Guo struct mxc_gpio_port { 56b78d8e59SShawn Guo struct list_head node; 57b78d8e59SShawn Guo void __iomem *base; 58b78d8e59SShawn Guo int irq; 59b78d8e59SShawn Guo int irq_high; 60b78d8e59SShawn Guo int virtual_irq_start; 612ce420daSShawn Guo struct bgpio_chip bgc; 62b78d8e59SShawn Guo u32 both_edges; 63b78d8e59SShawn Guo }; 64b78d8e59SShawn Guo 65e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 66e7fc6ae7SShawn Guo .dr_reg = 0x1c, 67e7fc6ae7SShawn Guo .gdir_reg = 0x00, 68e7fc6ae7SShawn Guo .psr_reg = 0x24, 69e7fc6ae7SShawn Guo .icr1_reg = 0x28, 70e7fc6ae7SShawn Guo .icr2_reg = 0x2c, 71e7fc6ae7SShawn Guo .imr_reg = 0x30, 72e7fc6ae7SShawn Guo .isr_reg = 0x34, 73e7fc6ae7SShawn Guo .low_level = 0x03, 74e7fc6ae7SShawn Guo .high_level = 0x02, 75e7fc6ae7SShawn Guo .rise_edge = 0x00, 76e7fc6ae7SShawn Guo .fall_edge = 0x01, 77e7fc6ae7SShawn Guo }; 78e7fc6ae7SShawn Guo 79e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 80e7fc6ae7SShawn Guo .dr_reg = 0x00, 81e7fc6ae7SShawn Guo .gdir_reg = 0x04, 82e7fc6ae7SShawn Guo .psr_reg = 0x08, 83e7fc6ae7SShawn Guo .icr1_reg = 0x0c, 84e7fc6ae7SShawn Guo .icr2_reg = 0x10, 85e7fc6ae7SShawn Guo .imr_reg = 0x14, 86e7fc6ae7SShawn Guo .isr_reg = 0x18, 87e7fc6ae7SShawn Guo .low_level = 0x00, 88e7fc6ae7SShawn Guo .high_level = 0x01, 89e7fc6ae7SShawn Guo .rise_edge = 0x02, 90e7fc6ae7SShawn Guo .fall_edge = 0x03, 91e7fc6ae7SShawn Guo }; 92e7fc6ae7SShawn Guo 93e7fc6ae7SShawn Guo static enum mxc_gpio_hwtype mxc_gpio_hwtype; 94e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata *mxc_gpio_hwdata; 95e7fc6ae7SShawn Guo 96e7fc6ae7SShawn Guo #define GPIO_DR (mxc_gpio_hwdata->dr_reg) 97e7fc6ae7SShawn Guo #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg) 98e7fc6ae7SShawn Guo #define GPIO_PSR (mxc_gpio_hwdata->psr_reg) 99e7fc6ae7SShawn Guo #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg) 100e7fc6ae7SShawn Guo #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg) 101e7fc6ae7SShawn Guo #define GPIO_IMR (mxc_gpio_hwdata->imr_reg) 102e7fc6ae7SShawn Guo #define GPIO_ISR (mxc_gpio_hwdata->isr_reg) 103e7fc6ae7SShawn Guo 104e7fc6ae7SShawn Guo #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level) 105e7fc6ae7SShawn Guo #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level) 106e7fc6ae7SShawn Guo #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge) 107e7fc6ae7SShawn Guo #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge) 108e7fc6ae7SShawn Guo #define GPIO_INT_NONE 0x4 109e7fc6ae7SShawn Guo 110e7fc6ae7SShawn Guo static struct platform_device_id mxc_gpio_devtype[] = { 111e7fc6ae7SShawn Guo { 112e7fc6ae7SShawn Guo .name = "imx1-gpio", 113e7fc6ae7SShawn Guo .driver_data = IMX1_GPIO, 114e7fc6ae7SShawn Guo }, { 115e7fc6ae7SShawn Guo .name = "imx21-gpio", 116e7fc6ae7SShawn Guo .driver_data = IMX21_GPIO, 117e7fc6ae7SShawn Guo }, { 118e7fc6ae7SShawn Guo .name = "imx31-gpio", 119e7fc6ae7SShawn Guo .driver_data = IMX31_GPIO, 120e7fc6ae7SShawn Guo }, { 121e7fc6ae7SShawn Guo /* sentinel */ 122e7fc6ae7SShawn Guo } 123e7fc6ae7SShawn Guo }; 124e7fc6ae7SShawn Guo 1258937cb60SShawn Guo static const struct of_device_id mxc_gpio_dt_ids[] = { 1268937cb60SShawn Guo { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], }, 1278937cb60SShawn Guo { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], }, 1288937cb60SShawn Guo { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], }, 1298937cb60SShawn Guo { /* sentinel */ } 1308937cb60SShawn Guo }; 1318937cb60SShawn Guo 132b78d8e59SShawn Guo /* 133b78d8e59SShawn Guo * MX2 has one interrupt *for all* gpio ports. The list is used 134b78d8e59SShawn Guo * to save the references to all ports, so that mx2_gpio_irq_handler 135b78d8e59SShawn Guo * can walk through all interrupt status registers. 136b78d8e59SShawn Guo */ 137b78d8e59SShawn Guo static LIST_HEAD(mxc_gpio_ports); 138d37a65bbSShawn Guo 139d37a65bbSShawn Guo /* Note: This driver assumes 32 GPIOs are handled in one register */ 140d37a65bbSShawn Guo 141d37a65bbSShawn Guo static int gpio_set_irq_type(struct irq_data *d, u32 type) 142d37a65bbSShawn Guo { 143d37a65bbSShawn Guo u32 gpio = irq_to_gpio(d->irq); 144e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 145e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 146d37a65bbSShawn Guo u32 bit, val; 147d37a65bbSShawn Guo int edge; 148d37a65bbSShawn Guo void __iomem *reg = port->base; 149d37a65bbSShawn Guo 150d37a65bbSShawn Guo port->both_edges &= ~(1 << (gpio & 31)); 151d37a65bbSShawn Guo switch (type) { 152d37a65bbSShawn Guo case IRQ_TYPE_EDGE_RISING: 153d37a65bbSShawn Guo edge = GPIO_INT_RISE_EDGE; 154d37a65bbSShawn Guo break; 155d37a65bbSShawn Guo case IRQ_TYPE_EDGE_FALLING: 156d37a65bbSShawn Guo edge = GPIO_INT_FALL_EDGE; 157d37a65bbSShawn Guo break; 158d37a65bbSShawn Guo case IRQ_TYPE_EDGE_BOTH: 1595523f86bSShawn Guo val = gpio_get_value(gpio); 160d37a65bbSShawn Guo if (val) { 161d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 162d37a65bbSShawn Guo pr_debug("mxc: set GPIO %d to low trigger\n", gpio); 163d37a65bbSShawn Guo } else { 164d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 165d37a65bbSShawn Guo pr_debug("mxc: set GPIO %d to high trigger\n", gpio); 166d37a65bbSShawn Guo } 167d37a65bbSShawn Guo port->both_edges |= 1 << (gpio & 31); 168d37a65bbSShawn Guo break; 169d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_LOW: 170d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 171d37a65bbSShawn Guo break; 172d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_HIGH: 173d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 174d37a65bbSShawn Guo break; 175d37a65bbSShawn Guo default: 176d37a65bbSShawn Guo return -EINVAL; 177d37a65bbSShawn Guo } 178d37a65bbSShawn Guo 179d37a65bbSShawn Guo reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 180d37a65bbSShawn Guo bit = gpio & 0xf; 181b78d8e59SShawn Guo val = readl(reg) & ~(0x3 << (bit << 1)); 182b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 183e4ea9333SShawn Guo writel(1 << (gpio & 0x1f), port->base + GPIO_ISR); 184d37a65bbSShawn Guo 185d37a65bbSShawn Guo return 0; 186d37a65bbSShawn Guo } 187d37a65bbSShawn Guo 188d37a65bbSShawn Guo static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 189d37a65bbSShawn Guo { 190d37a65bbSShawn Guo void __iomem *reg = port->base; 191d37a65bbSShawn Guo u32 bit, val; 192d37a65bbSShawn Guo int edge; 193d37a65bbSShawn Guo 194d37a65bbSShawn Guo reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 195d37a65bbSShawn Guo bit = gpio & 0xf; 196b78d8e59SShawn Guo val = readl(reg); 197d37a65bbSShawn Guo edge = (val >> (bit << 1)) & 3; 198d37a65bbSShawn Guo val &= ~(0x3 << (bit << 1)); 199d37a65bbSShawn Guo if (edge == GPIO_INT_HIGH_LEV) { 200d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 201d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 202d37a65bbSShawn Guo } else if (edge == GPIO_INT_LOW_LEV) { 203d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 204d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 205d37a65bbSShawn Guo } else { 206d37a65bbSShawn Guo pr_err("mxc: invalid configuration for GPIO %d: %x\n", 207d37a65bbSShawn Guo gpio, edge); 208d37a65bbSShawn Guo return; 209d37a65bbSShawn Guo } 210b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 211d37a65bbSShawn Guo } 212d37a65bbSShawn Guo 213d37a65bbSShawn Guo /* handle 32 interrupts in one status register */ 214d37a65bbSShawn Guo static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 215d37a65bbSShawn Guo { 216d37a65bbSShawn Guo u32 gpio_irq_no_base = port->virtual_irq_start; 217d37a65bbSShawn Guo 218d37a65bbSShawn Guo while (irq_stat != 0) { 219d37a65bbSShawn Guo int irqoffset = fls(irq_stat) - 1; 220d37a65bbSShawn Guo 221d37a65bbSShawn Guo if (port->both_edges & (1 << irqoffset)) 222d37a65bbSShawn Guo mxc_flip_edge(port, irqoffset); 223d37a65bbSShawn Guo 224d37a65bbSShawn Guo generic_handle_irq(gpio_irq_no_base + irqoffset); 225d37a65bbSShawn Guo 226d37a65bbSShawn Guo irq_stat &= ~(1 << irqoffset); 227d37a65bbSShawn Guo } 228d37a65bbSShawn Guo } 229d37a65bbSShawn Guo 230d37a65bbSShawn Guo /* MX1 and MX3 has one interrupt *per* gpio port */ 231d37a65bbSShawn Guo static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) 232d37a65bbSShawn Guo { 233d37a65bbSShawn Guo u32 irq_stat; 234d37a65bbSShawn Guo struct mxc_gpio_port *port = irq_get_handler_data(irq); 235d37a65bbSShawn Guo 236b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 237d37a65bbSShawn Guo 238d37a65bbSShawn Guo mxc_gpio_irq_handler(port, irq_stat); 239d37a65bbSShawn Guo } 240d37a65bbSShawn Guo 241d37a65bbSShawn Guo /* MX2 has one interrupt *for all* gpio ports */ 242d37a65bbSShawn Guo static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) 243d37a65bbSShawn Guo { 244d37a65bbSShawn Guo u32 irq_msk, irq_stat; 245b78d8e59SShawn Guo struct mxc_gpio_port *port; 246d37a65bbSShawn Guo 247d37a65bbSShawn Guo /* walk through all interrupt status registers */ 248b78d8e59SShawn Guo list_for_each_entry(port, &mxc_gpio_ports, node) { 249b78d8e59SShawn Guo irq_msk = readl(port->base + GPIO_IMR); 250d37a65bbSShawn Guo if (!irq_msk) 251d37a65bbSShawn Guo continue; 252d37a65bbSShawn Guo 253b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 254d37a65bbSShawn Guo if (irq_stat) 255b78d8e59SShawn Guo mxc_gpio_irq_handler(port, irq_stat); 256d37a65bbSShawn Guo } 257d37a65bbSShawn Guo } 258d37a65bbSShawn Guo 259d37a65bbSShawn Guo /* 260d37a65bbSShawn Guo * Set interrupt number "irq" in the GPIO as a wake-up source. 261d37a65bbSShawn Guo * While system is running, all registered GPIO interrupts need to have 262d37a65bbSShawn Guo * wake-up enabled. When system is suspended, only selected GPIO interrupts 263d37a65bbSShawn Guo * need to have wake-up enabled. 264d37a65bbSShawn Guo * @param irq interrupt source number 265d37a65bbSShawn Guo * @param enable enable as wake-up if equal to non-zero 266d37a65bbSShawn Guo * @return This function returns 0 on success. 267d37a65bbSShawn Guo */ 268d37a65bbSShawn Guo static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 269d37a65bbSShawn Guo { 270d37a65bbSShawn Guo u32 gpio = irq_to_gpio(d->irq); 271d37a65bbSShawn Guo u32 gpio_idx = gpio & 0x1F; 272e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 273e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 274d37a65bbSShawn Guo 275d37a65bbSShawn Guo if (enable) { 276d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 277d37a65bbSShawn Guo enable_irq_wake(port->irq_high); 278d37a65bbSShawn Guo else 279d37a65bbSShawn Guo enable_irq_wake(port->irq); 280d37a65bbSShawn Guo } else { 281d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 282d37a65bbSShawn Guo disable_irq_wake(port->irq_high); 283d37a65bbSShawn Guo else 284d37a65bbSShawn Guo disable_irq_wake(port->irq); 285d37a65bbSShawn Guo } 286d37a65bbSShawn Guo 287d37a65bbSShawn Guo return 0; 288d37a65bbSShawn Guo } 289d37a65bbSShawn Guo 290e4ea9333SShawn Guo static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port) 291e4ea9333SShawn Guo { 292e4ea9333SShawn Guo struct irq_chip_generic *gc; 293e4ea9333SShawn Guo struct irq_chip_type *ct; 294d37a65bbSShawn Guo 295e4ea9333SShawn Guo gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start, 296e4ea9333SShawn Guo port->base, handle_level_irq); 297e4ea9333SShawn Guo gc->private = port; 298e4ea9333SShawn Guo 299e4ea9333SShawn Guo ct = gc->chip_types; 300e4ea9333SShawn Guo ct->chip.irq_ack = irq_gc_ack, 301e4ea9333SShawn Guo ct->chip.irq_mask = irq_gc_mask_clr_bit; 302e4ea9333SShawn Guo ct->chip.irq_unmask = irq_gc_mask_set_bit; 303e4ea9333SShawn Guo ct->chip.irq_set_type = gpio_set_irq_type; 304e4ea9333SShawn Guo ct->chip.irq_set_wake = gpio_set_wake_irq, 305e4ea9333SShawn Guo ct->regs.ack = GPIO_ISR; 306e4ea9333SShawn Guo ct->regs.mask = GPIO_IMR; 307e4ea9333SShawn Guo 308e4ea9333SShawn Guo irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK, 309e4ea9333SShawn Guo IRQ_NOREQUEST, 0); 310e4ea9333SShawn Guo } 311d37a65bbSShawn Guo 312e7fc6ae7SShawn Guo static void __devinit mxc_gpio_get_hw(struct platform_device *pdev) 313e7fc6ae7SShawn Guo { 3148937cb60SShawn Guo const struct of_device_id *of_id = 3158937cb60SShawn Guo of_match_device(mxc_gpio_dt_ids, &pdev->dev); 3168937cb60SShawn Guo enum mxc_gpio_hwtype hwtype; 3178937cb60SShawn Guo 3188937cb60SShawn Guo if (of_id) 3198937cb60SShawn Guo pdev->id_entry = of_id->data; 3208937cb60SShawn Guo hwtype = pdev->id_entry->driver_data; 321e7fc6ae7SShawn Guo 322e7fc6ae7SShawn Guo if (mxc_gpio_hwtype) { 323e7fc6ae7SShawn Guo /* 324e7fc6ae7SShawn Guo * The driver works with a reasonable presupposition, 325e7fc6ae7SShawn Guo * that is all gpio ports must be the same type when 326e7fc6ae7SShawn Guo * running on one soc. 327e7fc6ae7SShawn Guo */ 328e7fc6ae7SShawn Guo BUG_ON(mxc_gpio_hwtype != hwtype); 329e7fc6ae7SShawn Guo return; 330e7fc6ae7SShawn Guo } 331e7fc6ae7SShawn Guo 332e7fc6ae7SShawn Guo if (hwtype == IMX31_GPIO) 333e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx31_gpio_hwdata; 334e7fc6ae7SShawn Guo else 335e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata; 336e7fc6ae7SShawn Guo 337e7fc6ae7SShawn Guo mxc_gpio_hwtype = hwtype; 338e7fc6ae7SShawn Guo } 339e7fc6ae7SShawn Guo 340b78d8e59SShawn Guo static int __devinit mxc_gpio_probe(struct platform_device *pdev) 341d37a65bbSShawn Guo { 3428937cb60SShawn Guo struct device_node *np = pdev->dev.of_node; 343b78d8e59SShawn Guo struct mxc_gpio_port *port; 344b78d8e59SShawn Guo struct resource *iores; 345e4ea9333SShawn Guo int err; 346d37a65bbSShawn Guo 347e7fc6ae7SShawn Guo mxc_gpio_get_hw(pdev); 348e7fc6ae7SShawn Guo 349b78d8e59SShawn Guo port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL); 350b78d8e59SShawn Guo if (!port) 351b78d8e59SShawn Guo return -ENOMEM; 352d37a65bbSShawn Guo 353b78d8e59SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 354b78d8e59SShawn Guo if (!iores) { 355b78d8e59SShawn Guo err = -ENODEV; 356b78d8e59SShawn Guo goto out_kfree; 357b78d8e59SShawn Guo } 358b78d8e59SShawn Guo 359b78d8e59SShawn Guo if (!request_mem_region(iores->start, resource_size(iores), 360b78d8e59SShawn Guo pdev->name)) { 361b78d8e59SShawn Guo err = -EBUSY; 362b78d8e59SShawn Guo goto out_kfree; 363b78d8e59SShawn Guo } 364b78d8e59SShawn Guo 365b78d8e59SShawn Guo port->base = ioremap(iores->start, resource_size(iores)); 366b78d8e59SShawn Guo if (!port->base) { 367b78d8e59SShawn Guo err = -ENOMEM; 368b78d8e59SShawn Guo goto out_release_mem; 369b78d8e59SShawn Guo } 370b78d8e59SShawn Guo 371b78d8e59SShawn Guo port->irq_high = platform_get_irq(pdev, 1); 372b78d8e59SShawn Guo port->irq = platform_get_irq(pdev, 0); 373b78d8e59SShawn Guo if (port->irq < 0) { 374b78d8e59SShawn Guo err = -EINVAL; 375b78d8e59SShawn Guo goto out_iounmap; 376b78d8e59SShawn Guo } 377b78d8e59SShawn Guo 378d37a65bbSShawn Guo /* disable the interrupt and clear the status */ 379b78d8e59SShawn Guo writel(0, port->base + GPIO_IMR); 380b78d8e59SShawn Guo writel(~0, port->base + GPIO_ISR); 381d37a65bbSShawn Guo 382e7fc6ae7SShawn Guo if (mxc_gpio_hwtype == IMX21_GPIO) { 383d37a65bbSShawn Guo /* setup one handler for all GPIO interrupts */ 384b78d8e59SShawn Guo if (pdev->id == 0) 385b78d8e59SShawn Guo irq_set_chained_handler(port->irq, 386b78d8e59SShawn Guo mx2_gpio_irq_handler); 387b78d8e59SShawn Guo } else { 388b78d8e59SShawn Guo /* setup one handler for each entry */ 389b78d8e59SShawn Guo irq_set_chained_handler(port->irq, mx3_gpio_irq_handler); 390b78d8e59SShawn Guo irq_set_handler_data(port->irq, port); 391b78d8e59SShawn Guo if (port->irq_high > 0) { 392b78d8e59SShawn Guo /* setup handler for GPIO 16 to 31 */ 393b78d8e59SShawn Guo irq_set_chained_handler(port->irq_high, 394b78d8e59SShawn Guo mx3_gpio_irq_handler); 395b78d8e59SShawn Guo irq_set_handler_data(port->irq_high, port); 396b78d8e59SShawn Guo } 397d37a65bbSShawn Guo } 398d37a65bbSShawn Guo 3992ce420daSShawn Guo err = bgpio_init(&port->bgc, &pdev->dev, 4, 4002ce420daSShawn Guo port->base + GPIO_PSR, 4012ce420daSShawn Guo port->base + GPIO_DR, NULL, 4022ce420daSShawn Guo port->base + GPIO_GDIR, NULL, false); 403b78d8e59SShawn Guo if (err) 404b78d8e59SShawn Guo goto out_iounmap; 405b78d8e59SShawn Guo 4062ce420daSShawn Guo port->bgc.gc.base = pdev->id * 32; 407fb149218SLothar Waßmann port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir); 408fb149218SLothar Waßmann port->bgc.data = port->bgc.read_reg(port->bgc.reg_set); 4092ce420daSShawn Guo 4102ce420daSShawn Guo err = gpiochip_add(&port->bgc.gc); 4112ce420daSShawn Guo if (err) 4122ce420daSShawn Guo goto out_bgpio_remove; 4132ce420daSShawn Guo 4148937cb60SShawn Guo /* 4158937cb60SShawn Guo * In dt case, we use gpio number range dynamically 4168937cb60SShawn Guo * allocated by gpio core. 4178937cb60SShawn Guo */ 4188937cb60SShawn Guo port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base : 4198937cb60SShawn Guo pdev->id * 32); 4208937cb60SShawn Guo 4218937cb60SShawn Guo /* gpio-mxc can be a generic irq chip */ 4228937cb60SShawn Guo mxc_gpio_init_gc(port); 4238937cb60SShawn Guo 424b78d8e59SShawn Guo list_add_tail(&port->node, &mxc_gpio_ports); 425b78d8e59SShawn Guo 426d37a65bbSShawn Guo return 0; 427b78d8e59SShawn Guo 4282ce420daSShawn Guo out_bgpio_remove: 4292ce420daSShawn Guo bgpio_remove(&port->bgc); 430b78d8e59SShawn Guo out_iounmap: 431b78d8e59SShawn Guo iounmap(port->base); 432b78d8e59SShawn Guo out_release_mem: 433b78d8e59SShawn Guo release_mem_region(iores->start, resource_size(iores)); 434b78d8e59SShawn Guo out_kfree: 435b78d8e59SShawn Guo kfree(port); 436b78d8e59SShawn Guo dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 437b78d8e59SShawn Guo return err; 438d37a65bbSShawn Guo } 439b78d8e59SShawn Guo 440b78d8e59SShawn Guo static struct platform_driver mxc_gpio_driver = { 441b78d8e59SShawn Guo .driver = { 442b78d8e59SShawn Guo .name = "gpio-mxc", 443b78d8e59SShawn Guo .owner = THIS_MODULE, 4448937cb60SShawn Guo .of_match_table = mxc_gpio_dt_ids, 445b78d8e59SShawn Guo }, 446b78d8e59SShawn Guo .probe = mxc_gpio_probe, 447e7fc6ae7SShawn Guo .id_table = mxc_gpio_devtype, 448b78d8e59SShawn Guo }; 449b78d8e59SShawn Guo 450b78d8e59SShawn Guo static int __init gpio_mxc_init(void) 451b78d8e59SShawn Guo { 452b78d8e59SShawn Guo return platform_driver_register(&mxc_gpio_driver); 453b78d8e59SShawn Guo } 454b78d8e59SShawn Guo postcore_initcall(gpio_mxc_init); 455b78d8e59SShawn Guo 456b78d8e59SShawn Guo MODULE_AUTHOR("Freescale Semiconductor, " 457b78d8e59SShawn Guo "Daniel Mack <danielncaiaq.de>, " 458b78d8e59SShawn Guo "Juergen Beisert <kernel@pengutronix.de>"); 459b78d8e59SShawn Guo MODULE_DESCRIPTION("Freescale MXC GPIO"); 460b78d8e59SShawn Guo MODULE_LICENSE("GPL"); 461