1d37a65bbSShawn Guo /* 2d37a65bbSShawn Guo * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 3d37a65bbSShawn Guo * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 4d37a65bbSShawn Guo * 5d37a65bbSShawn Guo * Based on code from Freescale, 6d37a65bbSShawn Guo * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 7d37a65bbSShawn Guo * 8d37a65bbSShawn Guo * This program is free software; you can redistribute it and/or 9d37a65bbSShawn Guo * modify it under the terms of the GNU General Public License 10d37a65bbSShawn Guo * as published by the Free Software Foundation; either version 2 11d37a65bbSShawn Guo * of the License, or (at your option) any later version. 12d37a65bbSShawn Guo * This program is distributed in the hope that it will be useful, 13d37a65bbSShawn Guo * but WITHOUT ANY WARRANTY; without even the implied warranty of 14d37a65bbSShawn Guo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15d37a65bbSShawn Guo * GNU General Public License for more details. 16d37a65bbSShawn Guo * 17d37a65bbSShawn Guo * You should have received a copy of the GNU General Public License 18d37a65bbSShawn Guo * along with this program; if not, write to the Free Software 19d37a65bbSShawn Guo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 20d37a65bbSShawn Guo */ 21d37a65bbSShawn Guo 2218f92b19SFabio Estevam #include <linux/err.h> 23d37a65bbSShawn Guo #include <linux/init.h> 24d37a65bbSShawn Guo #include <linux/interrupt.h> 25d37a65bbSShawn Guo #include <linux/io.h> 26d37a65bbSShawn Guo #include <linux/irq.h> 271ab7ef15SShawn Guo #include <linux/irqdomain.h> 28de88cbb7SCatalin Marinas #include <linux/irqchip/chained_irq.h> 29b78d8e59SShawn Guo #include <linux/platform_device.h> 30b78d8e59SShawn Guo #include <linux/slab.h> 310f4630f3SLinus Walleij #include <linux/gpio/driver.h> 320f4630f3SLinus Walleij /* FIXME: for gpio_get_value() replace this with direct register read */ 330f4630f3SLinus Walleij #include <linux/gpio.h> 348937cb60SShawn Guo #include <linux/of.h> 358937cb60SShawn Guo #include <linux/of_device.h> 36bb207ef1SPaul Gortmaker #include <linux/module.h> 3716c3bd35SChristoph Hellwig #include <linux/bug.h> 38d37a65bbSShawn Guo 39e7fc6ae7SShawn Guo enum mxc_gpio_hwtype { 40e7fc6ae7SShawn Guo IMX1_GPIO, /* runs on i.mx1 */ 41e7fc6ae7SShawn Guo IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ 42aeb27748SBenoît Thébaudeau IMX31_GPIO, /* runs on i.mx31 */ 43aeb27748SBenoît Thébaudeau IMX35_GPIO, /* runs on all other i.mx */ 44e7fc6ae7SShawn Guo }; 45e7fc6ae7SShawn Guo 46e7fc6ae7SShawn Guo /* device type dependent stuff */ 47e7fc6ae7SShawn Guo struct mxc_gpio_hwdata { 48e7fc6ae7SShawn Guo unsigned dr_reg; 49e7fc6ae7SShawn Guo unsigned gdir_reg; 50e7fc6ae7SShawn Guo unsigned psr_reg; 51e7fc6ae7SShawn Guo unsigned icr1_reg; 52e7fc6ae7SShawn Guo unsigned icr2_reg; 53e7fc6ae7SShawn Guo unsigned imr_reg; 54e7fc6ae7SShawn Guo unsigned isr_reg; 55aeb27748SBenoît Thébaudeau int edge_sel_reg; 56e7fc6ae7SShawn Guo unsigned low_level; 57e7fc6ae7SShawn Guo unsigned high_level; 58e7fc6ae7SShawn Guo unsigned rise_edge; 59e7fc6ae7SShawn Guo unsigned fall_edge; 60e7fc6ae7SShawn Guo }; 61e7fc6ae7SShawn Guo 62b78d8e59SShawn Guo struct mxc_gpio_port { 63b78d8e59SShawn Guo struct list_head node; 64b78d8e59SShawn Guo void __iomem *base; 65b78d8e59SShawn Guo int irq; 66b78d8e59SShawn Guo int irq_high; 671ab7ef15SShawn Guo struct irq_domain *domain; 680f4630f3SLinus Walleij struct gpio_chip gc; 69b78d8e59SShawn Guo u32 both_edges; 70b78d8e59SShawn Guo }; 71b78d8e59SShawn Guo 72e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 73e7fc6ae7SShawn Guo .dr_reg = 0x1c, 74e7fc6ae7SShawn Guo .gdir_reg = 0x00, 75e7fc6ae7SShawn Guo .psr_reg = 0x24, 76e7fc6ae7SShawn Guo .icr1_reg = 0x28, 77e7fc6ae7SShawn Guo .icr2_reg = 0x2c, 78e7fc6ae7SShawn Guo .imr_reg = 0x30, 79e7fc6ae7SShawn Guo .isr_reg = 0x34, 80aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 81e7fc6ae7SShawn Guo .low_level = 0x03, 82e7fc6ae7SShawn Guo .high_level = 0x02, 83e7fc6ae7SShawn Guo .rise_edge = 0x00, 84e7fc6ae7SShawn Guo .fall_edge = 0x01, 85e7fc6ae7SShawn Guo }; 86e7fc6ae7SShawn Guo 87e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 88e7fc6ae7SShawn Guo .dr_reg = 0x00, 89e7fc6ae7SShawn Guo .gdir_reg = 0x04, 90e7fc6ae7SShawn Guo .psr_reg = 0x08, 91e7fc6ae7SShawn Guo .icr1_reg = 0x0c, 92e7fc6ae7SShawn Guo .icr2_reg = 0x10, 93e7fc6ae7SShawn Guo .imr_reg = 0x14, 94e7fc6ae7SShawn Guo .isr_reg = 0x18, 95aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 96aeb27748SBenoît Thébaudeau .low_level = 0x00, 97aeb27748SBenoît Thébaudeau .high_level = 0x01, 98aeb27748SBenoît Thébaudeau .rise_edge = 0x02, 99aeb27748SBenoît Thébaudeau .fall_edge = 0x03, 100aeb27748SBenoît Thébaudeau }; 101aeb27748SBenoît Thébaudeau 102aeb27748SBenoît Thébaudeau static struct mxc_gpio_hwdata imx35_gpio_hwdata = { 103aeb27748SBenoît Thébaudeau .dr_reg = 0x00, 104aeb27748SBenoît Thébaudeau .gdir_reg = 0x04, 105aeb27748SBenoît Thébaudeau .psr_reg = 0x08, 106aeb27748SBenoît Thébaudeau .icr1_reg = 0x0c, 107aeb27748SBenoît Thébaudeau .icr2_reg = 0x10, 108aeb27748SBenoît Thébaudeau .imr_reg = 0x14, 109aeb27748SBenoît Thébaudeau .isr_reg = 0x18, 110aeb27748SBenoît Thébaudeau .edge_sel_reg = 0x1c, 111e7fc6ae7SShawn Guo .low_level = 0x00, 112e7fc6ae7SShawn Guo .high_level = 0x01, 113e7fc6ae7SShawn Guo .rise_edge = 0x02, 114e7fc6ae7SShawn Guo .fall_edge = 0x03, 115e7fc6ae7SShawn Guo }; 116e7fc6ae7SShawn Guo 117e7fc6ae7SShawn Guo static enum mxc_gpio_hwtype mxc_gpio_hwtype; 118e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata *mxc_gpio_hwdata; 119e7fc6ae7SShawn Guo 120e7fc6ae7SShawn Guo #define GPIO_DR (mxc_gpio_hwdata->dr_reg) 121e7fc6ae7SShawn Guo #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg) 122e7fc6ae7SShawn Guo #define GPIO_PSR (mxc_gpio_hwdata->psr_reg) 123e7fc6ae7SShawn Guo #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg) 124e7fc6ae7SShawn Guo #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg) 125e7fc6ae7SShawn Guo #define GPIO_IMR (mxc_gpio_hwdata->imr_reg) 126e7fc6ae7SShawn Guo #define GPIO_ISR (mxc_gpio_hwdata->isr_reg) 127aeb27748SBenoît Thébaudeau #define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg) 128e7fc6ae7SShawn Guo 129e7fc6ae7SShawn Guo #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level) 130e7fc6ae7SShawn Guo #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level) 131e7fc6ae7SShawn Guo #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge) 132e7fc6ae7SShawn Guo #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge) 133aeb27748SBenoît Thébaudeau #define GPIO_INT_BOTH_EDGES 0x4 134e7fc6ae7SShawn Guo 135f4f79d40SKrzysztof Kozlowski static const struct platform_device_id mxc_gpio_devtype[] = { 136e7fc6ae7SShawn Guo { 137e7fc6ae7SShawn Guo .name = "imx1-gpio", 138e7fc6ae7SShawn Guo .driver_data = IMX1_GPIO, 139e7fc6ae7SShawn Guo }, { 140e7fc6ae7SShawn Guo .name = "imx21-gpio", 141e7fc6ae7SShawn Guo .driver_data = IMX21_GPIO, 142e7fc6ae7SShawn Guo }, { 143e7fc6ae7SShawn Guo .name = "imx31-gpio", 144e7fc6ae7SShawn Guo .driver_data = IMX31_GPIO, 145e7fc6ae7SShawn Guo }, { 146aeb27748SBenoît Thébaudeau .name = "imx35-gpio", 147aeb27748SBenoît Thébaudeau .driver_data = IMX35_GPIO, 148aeb27748SBenoît Thébaudeau }, { 149e7fc6ae7SShawn Guo /* sentinel */ 150e7fc6ae7SShawn Guo } 151e7fc6ae7SShawn Guo }; 152e7fc6ae7SShawn Guo 1538937cb60SShawn Guo static const struct of_device_id mxc_gpio_dt_ids[] = { 1548937cb60SShawn Guo { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], }, 1558937cb60SShawn Guo { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], }, 1568937cb60SShawn Guo { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], }, 157aeb27748SBenoît Thébaudeau { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], }, 1588937cb60SShawn Guo { /* sentinel */ } 1598937cb60SShawn Guo }; 1608937cb60SShawn Guo 161b78d8e59SShawn Guo /* 162b78d8e59SShawn Guo * MX2 has one interrupt *for all* gpio ports. The list is used 163b78d8e59SShawn Guo * to save the references to all ports, so that mx2_gpio_irq_handler 164b78d8e59SShawn Guo * can walk through all interrupt status registers. 165b78d8e59SShawn Guo */ 166b78d8e59SShawn Guo static LIST_HEAD(mxc_gpio_ports); 167d37a65bbSShawn Guo 168d37a65bbSShawn Guo /* Note: This driver assumes 32 GPIOs are handled in one register */ 169d37a65bbSShawn Guo 170d37a65bbSShawn Guo static int gpio_set_irq_type(struct irq_data *d, u32 type) 171d37a65bbSShawn Guo { 172e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 173e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 174d37a65bbSShawn Guo u32 bit, val; 1751ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 1760f4630f3SLinus Walleij u32 gpio = port->gc.base + gpio_idx; 177d37a65bbSShawn Guo int edge; 178d37a65bbSShawn Guo void __iomem *reg = port->base; 179d37a65bbSShawn Guo 1801ab7ef15SShawn Guo port->both_edges &= ~(1 << gpio_idx); 181d37a65bbSShawn Guo switch (type) { 182d37a65bbSShawn Guo case IRQ_TYPE_EDGE_RISING: 183d37a65bbSShawn Guo edge = GPIO_INT_RISE_EDGE; 184d37a65bbSShawn Guo break; 185d37a65bbSShawn Guo case IRQ_TYPE_EDGE_FALLING: 186d37a65bbSShawn Guo edge = GPIO_INT_FALL_EDGE; 187d37a65bbSShawn Guo break; 188d37a65bbSShawn Guo case IRQ_TYPE_EDGE_BOTH: 189aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 190aeb27748SBenoît Thébaudeau edge = GPIO_INT_BOTH_EDGES; 191aeb27748SBenoît Thébaudeau } else { 1925523f86bSShawn Guo val = gpio_get_value(gpio); 193d37a65bbSShawn Guo if (val) { 194d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 195d37a65bbSShawn Guo pr_debug("mxc: set GPIO %d to low trigger\n", gpio); 196d37a65bbSShawn Guo } else { 197d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 198d37a65bbSShawn Guo pr_debug("mxc: set GPIO %d to high trigger\n", gpio); 199d37a65bbSShawn Guo } 2001ab7ef15SShawn Guo port->both_edges |= 1 << gpio_idx; 201aeb27748SBenoît Thébaudeau } 202d37a65bbSShawn Guo break; 203d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_LOW: 204d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 205d37a65bbSShawn Guo break; 206d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_HIGH: 207d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 208d37a65bbSShawn Guo break; 209d37a65bbSShawn Guo default: 210d37a65bbSShawn Guo return -EINVAL; 211d37a65bbSShawn Guo } 212d37a65bbSShawn Guo 213aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 214aeb27748SBenoît Thébaudeau val = readl(port->base + GPIO_EDGE_SEL); 215aeb27748SBenoît Thébaudeau if (edge == GPIO_INT_BOTH_EDGES) 216f948ad07SLinus Torvalds writel(val | (1 << gpio_idx), 217aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 218aeb27748SBenoît Thébaudeau else 219f948ad07SLinus Torvalds writel(val & ~(1 << gpio_idx), 220aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 221aeb27748SBenoît Thébaudeau } 222aeb27748SBenoît Thébaudeau 223aeb27748SBenoît Thébaudeau if (edge != GPIO_INT_BOTH_EDGES) { 224f948ad07SLinus Torvalds reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ 2251ab7ef15SShawn Guo bit = gpio_idx & 0xf; 226b78d8e59SShawn Guo val = readl(reg) & ~(0x3 << (bit << 1)); 227b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 228aeb27748SBenoît Thébaudeau } 229aeb27748SBenoît Thébaudeau 2301ab7ef15SShawn Guo writel(1 << gpio_idx, port->base + GPIO_ISR); 231d37a65bbSShawn Guo 232d37a65bbSShawn Guo return 0; 233d37a65bbSShawn Guo } 234d37a65bbSShawn Guo 235d37a65bbSShawn Guo static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 236d37a65bbSShawn Guo { 237d37a65bbSShawn Guo void __iomem *reg = port->base; 238d37a65bbSShawn Guo u32 bit, val; 239d37a65bbSShawn Guo int edge; 240d37a65bbSShawn Guo 241d37a65bbSShawn Guo reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 242d37a65bbSShawn Guo bit = gpio & 0xf; 243b78d8e59SShawn Guo val = readl(reg); 244d37a65bbSShawn Guo edge = (val >> (bit << 1)) & 3; 245d37a65bbSShawn Guo val &= ~(0x3 << (bit << 1)); 246d37a65bbSShawn Guo if (edge == GPIO_INT_HIGH_LEV) { 247d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 248d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 249d37a65bbSShawn Guo } else if (edge == GPIO_INT_LOW_LEV) { 250d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 251d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 252d37a65bbSShawn Guo } else { 253d37a65bbSShawn Guo pr_err("mxc: invalid configuration for GPIO %d: %x\n", 254d37a65bbSShawn Guo gpio, edge); 255d37a65bbSShawn Guo return; 256d37a65bbSShawn Guo } 257b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 258d37a65bbSShawn Guo } 259d37a65bbSShawn Guo 260d37a65bbSShawn Guo /* handle 32 interrupts in one status register */ 261d37a65bbSShawn Guo static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 262d37a65bbSShawn Guo { 263d37a65bbSShawn Guo while (irq_stat != 0) { 264d37a65bbSShawn Guo int irqoffset = fls(irq_stat) - 1; 265d37a65bbSShawn Guo 266d37a65bbSShawn Guo if (port->both_edges & (1 << irqoffset)) 267d37a65bbSShawn Guo mxc_flip_edge(port, irqoffset); 268d37a65bbSShawn Guo 2691ab7ef15SShawn Guo generic_handle_irq(irq_find_mapping(port->domain, irqoffset)); 270d37a65bbSShawn Guo 271d37a65bbSShawn Guo irq_stat &= ~(1 << irqoffset); 272d37a65bbSShawn Guo } 273d37a65bbSShawn Guo } 274d37a65bbSShawn Guo 275d37a65bbSShawn Guo /* MX1 and MX3 has one interrupt *per* gpio port */ 276bd0b9ac4SThomas Gleixner static void mx3_gpio_irq_handler(struct irq_desc *desc) 277d37a65bbSShawn Guo { 278d37a65bbSShawn Guo u32 irq_stat; 279476f8b4cSJiang Liu struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); 280476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 2810e44b6ecSShawn Guo 2820e44b6ecSShawn Guo chained_irq_enter(chip, desc); 283d37a65bbSShawn Guo 284b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 285d37a65bbSShawn Guo 286d37a65bbSShawn Guo mxc_gpio_irq_handler(port, irq_stat); 2870e44b6ecSShawn Guo 2880e44b6ecSShawn Guo chained_irq_exit(chip, desc); 289d37a65bbSShawn Guo } 290d37a65bbSShawn Guo 291d37a65bbSShawn Guo /* MX2 has one interrupt *for all* gpio ports */ 292bd0b9ac4SThomas Gleixner static void mx2_gpio_irq_handler(struct irq_desc *desc) 293d37a65bbSShawn Guo { 294d37a65bbSShawn Guo u32 irq_msk, irq_stat; 295b78d8e59SShawn Guo struct mxc_gpio_port *port; 296476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 297c0e811d9SUwe Kleine-König 298c0e811d9SUwe Kleine-König chained_irq_enter(chip, desc); 299d37a65bbSShawn Guo 300d37a65bbSShawn Guo /* walk through all interrupt status registers */ 301b78d8e59SShawn Guo list_for_each_entry(port, &mxc_gpio_ports, node) { 302b78d8e59SShawn Guo irq_msk = readl(port->base + GPIO_IMR); 303d37a65bbSShawn Guo if (!irq_msk) 304d37a65bbSShawn Guo continue; 305d37a65bbSShawn Guo 306b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 307d37a65bbSShawn Guo if (irq_stat) 308b78d8e59SShawn Guo mxc_gpio_irq_handler(port, irq_stat); 309d37a65bbSShawn Guo } 310c0e811d9SUwe Kleine-König chained_irq_exit(chip, desc); 311d37a65bbSShawn Guo } 312d37a65bbSShawn Guo 313d37a65bbSShawn Guo /* 314d37a65bbSShawn Guo * Set interrupt number "irq" in the GPIO as a wake-up source. 315d37a65bbSShawn Guo * While system is running, all registered GPIO interrupts need to have 316d37a65bbSShawn Guo * wake-up enabled. When system is suspended, only selected GPIO interrupts 317d37a65bbSShawn Guo * need to have wake-up enabled. 318d37a65bbSShawn Guo * @param irq interrupt source number 319d37a65bbSShawn Guo * @param enable enable as wake-up if equal to non-zero 320d37a65bbSShawn Guo * @return This function returns 0 on success. 321d37a65bbSShawn Guo */ 322d37a65bbSShawn Guo static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 323d37a65bbSShawn Guo { 324e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 325e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 3261ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 327d37a65bbSShawn Guo 328d37a65bbSShawn Guo if (enable) { 329d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 330d37a65bbSShawn Guo enable_irq_wake(port->irq_high); 331d37a65bbSShawn Guo else 332d37a65bbSShawn Guo enable_irq_wake(port->irq); 333d37a65bbSShawn Guo } else { 334d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 335d37a65bbSShawn Guo disable_irq_wake(port->irq_high); 336d37a65bbSShawn Guo else 337d37a65bbSShawn Guo disable_irq_wake(port->irq); 338d37a65bbSShawn Guo } 339d37a65bbSShawn Guo 340d37a65bbSShawn Guo return 0; 341d37a65bbSShawn Guo } 342d37a65bbSShawn Guo 3439e26b0b1SPeng Fan static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) 344e4ea9333SShawn Guo { 345e4ea9333SShawn Guo struct irq_chip_generic *gc; 346e4ea9333SShawn Guo struct irq_chip_type *ct; 347d37a65bbSShawn Guo 3481ab7ef15SShawn Guo gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base, 349e4ea9333SShawn Guo port->base, handle_level_irq); 3509e26b0b1SPeng Fan if (!gc) 3519e26b0b1SPeng Fan return -ENOMEM; 352e4ea9333SShawn Guo gc->private = port; 353e4ea9333SShawn Guo 354e4ea9333SShawn Guo ct = gc->chip_types; 355591567a5SShawn Guo ct->chip.irq_ack = irq_gc_ack_set_bit; 356e4ea9333SShawn Guo ct->chip.irq_mask = irq_gc_mask_clr_bit; 357e4ea9333SShawn Guo ct->chip.irq_unmask = irq_gc_mask_set_bit; 358e4ea9333SShawn Guo ct->chip.irq_set_type = gpio_set_irq_type; 359591567a5SShawn Guo ct->chip.irq_set_wake = gpio_set_wake_irq; 360952cfbd3SUlises Brindis ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND; 361e4ea9333SShawn Guo ct->regs.ack = GPIO_ISR; 362e4ea9333SShawn Guo ct->regs.mask = GPIO_IMR; 363e4ea9333SShawn Guo 364e4ea9333SShawn Guo irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK, 365e4ea9333SShawn Guo IRQ_NOREQUEST, 0); 3669e26b0b1SPeng Fan 3679e26b0b1SPeng Fan return 0; 368e4ea9333SShawn Guo } 369d37a65bbSShawn Guo 3703836309dSBill Pemberton static void mxc_gpio_get_hw(struct platform_device *pdev) 371e7fc6ae7SShawn Guo { 3728937cb60SShawn Guo const struct of_device_id *of_id = 3738937cb60SShawn Guo of_match_device(mxc_gpio_dt_ids, &pdev->dev); 3748937cb60SShawn Guo enum mxc_gpio_hwtype hwtype; 3758937cb60SShawn Guo 3768937cb60SShawn Guo if (of_id) 3778937cb60SShawn Guo pdev->id_entry = of_id->data; 3788937cb60SShawn Guo hwtype = pdev->id_entry->driver_data; 379e7fc6ae7SShawn Guo 380e7fc6ae7SShawn Guo if (mxc_gpio_hwtype) { 381e7fc6ae7SShawn Guo /* 382e7fc6ae7SShawn Guo * The driver works with a reasonable presupposition, 383e7fc6ae7SShawn Guo * that is all gpio ports must be the same type when 384e7fc6ae7SShawn Guo * running on one soc. 385e7fc6ae7SShawn Guo */ 386e7fc6ae7SShawn Guo BUG_ON(mxc_gpio_hwtype != hwtype); 387e7fc6ae7SShawn Guo return; 388e7fc6ae7SShawn Guo } 389e7fc6ae7SShawn Guo 390aeb27748SBenoît Thébaudeau if (hwtype == IMX35_GPIO) 391aeb27748SBenoît Thébaudeau mxc_gpio_hwdata = &imx35_gpio_hwdata; 392aeb27748SBenoît Thébaudeau else if (hwtype == IMX31_GPIO) 393e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx31_gpio_hwdata; 394e7fc6ae7SShawn Guo else 395e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata; 396e7fc6ae7SShawn Guo 397e7fc6ae7SShawn Guo mxc_gpio_hwtype = hwtype; 398e7fc6ae7SShawn Guo } 399e7fc6ae7SShawn Guo 40009ad8039SShawn Guo static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 40109ad8039SShawn Guo { 4020f4630f3SLinus Walleij struct mxc_gpio_port *port = gpiochip_get_data(gc); 40309ad8039SShawn Guo 4041ab7ef15SShawn Guo return irq_find_mapping(port->domain, offset); 40509ad8039SShawn Guo } 40609ad8039SShawn Guo 4073836309dSBill Pemberton static int mxc_gpio_probe(struct platform_device *pdev) 408d37a65bbSShawn Guo { 4098937cb60SShawn Guo struct device_node *np = pdev->dev.of_node; 410b78d8e59SShawn Guo struct mxc_gpio_port *port; 411b78d8e59SShawn Guo struct resource *iores; 4121ab7ef15SShawn Guo int irq_base; 413e4ea9333SShawn Guo int err; 414d37a65bbSShawn Guo 415e7fc6ae7SShawn Guo mxc_gpio_get_hw(pdev); 416e7fc6ae7SShawn Guo 4178cd73e4eSFabio Estevam port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 418b78d8e59SShawn Guo if (!port) 419b78d8e59SShawn Guo return -ENOMEM; 420d37a65bbSShawn Guo 421b78d8e59SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4228cd73e4eSFabio Estevam port->base = devm_ioremap_resource(&pdev->dev, iores); 4238cd73e4eSFabio Estevam if (IS_ERR(port->base)) 4248cd73e4eSFabio Estevam return PTR_ERR(port->base); 425b78d8e59SShawn Guo 426b78d8e59SShawn Guo port->irq_high = platform_get_irq(pdev, 1); 427b78d8e59SShawn Guo port->irq = platform_get_irq(pdev, 0); 4288cd73e4eSFabio Estevam if (port->irq < 0) 4295ea80e49SSachin Kamat return port->irq; 430b78d8e59SShawn Guo 431d37a65bbSShawn Guo /* disable the interrupt and clear the status */ 432b78d8e59SShawn Guo writel(0, port->base + GPIO_IMR); 433b78d8e59SShawn Guo writel(~0, port->base + GPIO_ISR); 434d37a65bbSShawn Guo 435e7fc6ae7SShawn Guo if (mxc_gpio_hwtype == IMX21_GPIO) { 43633a4e985SUwe Kleine-König /* 43733a4e985SUwe Kleine-König * Setup one handler for all GPIO interrupts. Actually setting 43833a4e985SUwe Kleine-König * the handler is needed only once, but doing it for every port 43933a4e985SUwe Kleine-König * is more robust and easier. 44033a4e985SUwe Kleine-König */ 44133a4e985SUwe Kleine-König irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); 442b78d8e59SShawn Guo } else { 443b78d8e59SShawn Guo /* setup one handler for each entry */ 444e65eea54SRussell King irq_set_chained_handler_and_data(port->irq, 445e65eea54SRussell King mx3_gpio_irq_handler, port); 446e65eea54SRussell King if (port->irq_high > 0) 447b78d8e59SShawn Guo /* setup handler for GPIO 16 to 31 */ 448e65eea54SRussell King irq_set_chained_handler_and_data(port->irq_high, 449e65eea54SRussell King mx3_gpio_irq_handler, 450e65eea54SRussell King port); 451d37a65bbSShawn Guo } 452d37a65bbSShawn Guo 4530f4630f3SLinus Walleij err = bgpio_init(&port->gc, &pdev->dev, 4, 4542ce420daSShawn Guo port->base + GPIO_PSR, 4552ce420daSShawn Guo port->base + GPIO_DR, NULL, 456442b2494SVladimir Zapolskiy port->base + GPIO_GDIR, NULL, 457442b2494SVladimir Zapolskiy BGPIOF_READ_OUTPUT_REG_SET); 458b78d8e59SShawn Guo if (err) 4598cd73e4eSFabio Estevam goto out_bgio; 460b78d8e59SShawn Guo 4614c806c98SVladimir Zapolskiy if (of_property_read_bool(np, "gpio-ranges")) { 4624c806c98SVladimir Zapolskiy port->gc.request = gpiochip_generic_request; 4634c806c98SVladimir Zapolskiy port->gc.free = gpiochip_generic_free; 4644c806c98SVladimir Zapolskiy } 4654c806c98SVladimir Zapolskiy 4660f4630f3SLinus Walleij port->gc.to_irq = mxc_gpio_to_irq; 4670f4630f3SLinus Walleij port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : 4687e6086d9SShawn Guo pdev->id * 32; 4692ce420daSShawn Guo 470ffc56630SLaxman Dewangan err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port); 4712ce420daSShawn Guo if (err) 4720f4630f3SLinus Walleij goto out_bgio; 4732ce420daSShawn Guo 4741ab7ef15SShawn Guo irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id()); 4751ab7ef15SShawn Guo if (irq_base < 0) { 4761ab7ef15SShawn Guo err = irq_base; 477ffc56630SLaxman Dewangan goto out_bgio; 4781ab7ef15SShawn Guo } 4791ab7ef15SShawn Guo 4801ab7ef15SShawn Guo port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, 4811ab7ef15SShawn Guo &irq_domain_simple_ops, NULL); 4821ab7ef15SShawn Guo if (!port->domain) { 4831ab7ef15SShawn Guo err = -ENODEV; 4841ab7ef15SShawn Guo goto out_irqdesc_free; 4851ab7ef15SShawn Guo } 4868937cb60SShawn Guo 4878937cb60SShawn Guo /* gpio-mxc can be a generic irq chip */ 4889e26b0b1SPeng Fan err = mxc_gpio_init_gc(port, irq_base); 4899e26b0b1SPeng Fan if (err < 0) 4909e26b0b1SPeng Fan goto out_irqdomain_remove; 4918937cb60SShawn Guo 492b78d8e59SShawn Guo list_add_tail(&port->node, &mxc_gpio_ports); 493b78d8e59SShawn Guo 494d37a65bbSShawn Guo return 0; 495b78d8e59SShawn Guo 4969e26b0b1SPeng Fan out_irqdomain_remove: 4979e26b0b1SPeng Fan irq_domain_remove(port->domain); 4981ab7ef15SShawn Guo out_irqdesc_free: 4991ab7ef15SShawn Guo irq_free_descs(irq_base, 32); 5008cd73e4eSFabio Estevam out_bgio: 501b78d8e59SShawn Guo dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 502b78d8e59SShawn Guo return err; 503d37a65bbSShawn Guo } 504b78d8e59SShawn Guo 505b78d8e59SShawn Guo static struct platform_driver mxc_gpio_driver = { 506b78d8e59SShawn Guo .driver = { 507b78d8e59SShawn Guo .name = "gpio-mxc", 5088937cb60SShawn Guo .of_match_table = mxc_gpio_dt_ids, 509b78d8e59SShawn Guo }, 510b78d8e59SShawn Guo .probe = mxc_gpio_probe, 511e7fc6ae7SShawn Guo .id_table = mxc_gpio_devtype, 512b78d8e59SShawn Guo }; 513b78d8e59SShawn Guo 514b78d8e59SShawn Guo static int __init gpio_mxc_init(void) 515b78d8e59SShawn Guo { 516b78d8e59SShawn Guo return platform_driver_register(&mxc_gpio_driver); 517b78d8e59SShawn Guo } 518e188cbf7SVladimir Zapolskiy subsys_initcall(gpio_mxc_init); 519b78d8e59SShawn Guo 520b78d8e59SShawn Guo MODULE_AUTHOR("Freescale Semiconductor, " 521b78d8e59SShawn Guo "Daniel Mack <danielncaiaq.de>, " 522b78d8e59SShawn Guo "Juergen Beisert <kernel@pengutronix.de>"); 523b78d8e59SShawn Guo MODULE_DESCRIPTION("Freescale MXC GPIO"); 524b78d8e59SShawn Guo MODULE_LICENSE("GPL"); 525