1d37a65bbSShawn Guo /* 2d37a65bbSShawn Guo * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 3d37a65bbSShawn Guo * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 4d37a65bbSShawn Guo * 5d37a65bbSShawn Guo * Based on code from Freescale, 6d37a65bbSShawn Guo * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 7d37a65bbSShawn Guo * 8d37a65bbSShawn Guo * This program is free software; you can redistribute it and/or 9d37a65bbSShawn Guo * modify it under the terms of the GNU General Public License 10d37a65bbSShawn Guo * as published by the Free Software Foundation; either version 2 11d37a65bbSShawn Guo * of the License, or (at your option) any later version. 12d37a65bbSShawn Guo * This program is distributed in the hope that it will be useful, 13d37a65bbSShawn Guo * but WITHOUT ANY WARRANTY; without even the implied warranty of 14d37a65bbSShawn Guo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15d37a65bbSShawn Guo * GNU General Public License for more details. 16d37a65bbSShawn Guo * 17d37a65bbSShawn Guo * You should have received a copy of the GNU General Public License 18d37a65bbSShawn Guo * along with this program; if not, write to the Free Software 19d37a65bbSShawn Guo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 20d37a65bbSShawn Guo */ 21d37a65bbSShawn Guo 22d37a65bbSShawn Guo #include <linux/init.h> 23d37a65bbSShawn Guo #include <linux/interrupt.h> 24d37a65bbSShawn Guo #include <linux/io.h> 25d37a65bbSShawn Guo #include <linux/irq.h> 26d37a65bbSShawn Guo #include <linux/gpio.h> 27b78d8e59SShawn Guo #include <linux/platform_device.h> 28b78d8e59SShawn Guo #include <linux/slab.h> 292ce420daSShawn Guo #include <linux/basic_mmio_gpio.h> 30d37a65bbSShawn Guo #include <mach/hardware.h> 31d37a65bbSShawn Guo #include <asm-generic/bug.h> 32d37a65bbSShawn Guo 33b78d8e59SShawn Guo struct mxc_gpio_port { 34b78d8e59SShawn Guo struct list_head node; 35b78d8e59SShawn Guo void __iomem *base; 36b78d8e59SShawn Guo int irq; 37b78d8e59SShawn Guo int irq_high; 38b78d8e59SShawn Guo int virtual_irq_start; 392ce420daSShawn Guo struct bgpio_chip bgc; 40b78d8e59SShawn Guo u32 both_edges; 41b78d8e59SShawn Guo }; 42b78d8e59SShawn Guo 43b78d8e59SShawn Guo /* 44b78d8e59SShawn Guo * MX2 has one interrupt *for all* gpio ports. The list is used 45b78d8e59SShawn Guo * to save the references to all ports, so that mx2_gpio_irq_handler 46b78d8e59SShawn Guo * can walk through all interrupt status registers. 47b78d8e59SShawn Guo */ 48b78d8e59SShawn Guo static LIST_HEAD(mxc_gpio_ports); 49d37a65bbSShawn Guo 50d37a65bbSShawn Guo #define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2()) 51d37a65bbSShawn Guo 52d37a65bbSShawn Guo #define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00) 53d37a65bbSShawn Guo #define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04) 54d37a65bbSShawn Guo #define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08) 55d37a65bbSShawn Guo #define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C) 56d37a65bbSShawn Guo #define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10) 57d37a65bbSShawn Guo #define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14) 58d37a65bbSShawn Guo #define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18) 59d37a65bbSShawn Guo 60d37a65bbSShawn Guo #define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0) 61d37a65bbSShawn Guo #define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1) 62d37a65bbSShawn Guo #define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2) 63d37a65bbSShawn Guo #define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3) 64d37a65bbSShawn Guo #define GPIO_INT_NONE 0x4 65d37a65bbSShawn Guo 66d37a65bbSShawn Guo /* Note: This driver assumes 32 GPIOs are handled in one register */ 67d37a65bbSShawn Guo 68d37a65bbSShawn Guo static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index) 69d37a65bbSShawn Guo { 70b78d8e59SShawn Guo writel(1 << index, port->base + GPIO_ISR); 71d37a65bbSShawn Guo } 72d37a65bbSShawn Guo 73d37a65bbSShawn Guo static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index, 74d37a65bbSShawn Guo int enable) 75d37a65bbSShawn Guo { 76d37a65bbSShawn Guo u32 l; 77d37a65bbSShawn Guo 78b78d8e59SShawn Guo l = readl(port->base + GPIO_IMR); 79d37a65bbSShawn Guo l = (l & (~(1 << index))) | (!!enable << index); 80b78d8e59SShawn Guo writel(l, port->base + GPIO_IMR); 81d37a65bbSShawn Guo } 82d37a65bbSShawn Guo 83d37a65bbSShawn Guo static void gpio_ack_irq(struct irq_data *d) 84d37a65bbSShawn Guo { 85b78d8e59SShawn Guo struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d); 86d37a65bbSShawn Guo u32 gpio = irq_to_gpio(d->irq); 87b78d8e59SShawn Guo _clear_gpio_irqstatus(port, gpio & 0x1f); 88d37a65bbSShawn Guo } 89d37a65bbSShawn Guo 90d37a65bbSShawn Guo static void gpio_mask_irq(struct irq_data *d) 91d37a65bbSShawn Guo { 92b78d8e59SShawn Guo struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d); 93d37a65bbSShawn Guo u32 gpio = irq_to_gpio(d->irq); 94b78d8e59SShawn Guo _set_gpio_irqenable(port, gpio & 0x1f, 0); 95d37a65bbSShawn Guo } 96d37a65bbSShawn Guo 97d37a65bbSShawn Guo static void gpio_unmask_irq(struct irq_data *d) 98d37a65bbSShawn Guo { 99b78d8e59SShawn Guo struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d); 100d37a65bbSShawn Guo u32 gpio = irq_to_gpio(d->irq); 101b78d8e59SShawn Guo _set_gpio_irqenable(port, gpio & 0x1f, 1); 102d37a65bbSShawn Guo } 103d37a65bbSShawn Guo 104d37a65bbSShawn Guo static int gpio_set_irq_type(struct irq_data *d, u32 type) 105d37a65bbSShawn Guo { 106d37a65bbSShawn Guo u32 gpio = irq_to_gpio(d->irq); 107b78d8e59SShawn Guo struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d); 108d37a65bbSShawn Guo u32 bit, val; 109d37a65bbSShawn Guo int edge; 110d37a65bbSShawn Guo void __iomem *reg = port->base; 111d37a65bbSShawn Guo 112d37a65bbSShawn Guo port->both_edges &= ~(1 << (gpio & 31)); 113d37a65bbSShawn Guo switch (type) { 114d37a65bbSShawn Guo case IRQ_TYPE_EDGE_RISING: 115d37a65bbSShawn Guo edge = GPIO_INT_RISE_EDGE; 116d37a65bbSShawn Guo break; 117d37a65bbSShawn Guo case IRQ_TYPE_EDGE_FALLING: 118d37a65bbSShawn Guo edge = GPIO_INT_FALL_EDGE; 119d37a65bbSShawn Guo break; 120d37a65bbSShawn Guo case IRQ_TYPE_EDGE_BOTH: 1212ce420daSShawn Guo val = gpio_get_value(gpio & 31); 122d37a65bbSShawn Guo if (val) { 123d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 124d37a65bbSShawn Guo pr_debug("mxc: set GPIO %d to low trigger\n", gpio); 125d37a65bbSShawn Guo } else { 126d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 127d37a65bbSShawn Guo pr_debug("mxc: set GPIO %d to high trigger\n", gpio); 128d37a65bbSShawn Guo } 129d37a65bbSShawn Guo port->both_edges |= 1 << (gpio & 31); 130d37a65bbSShawn Guo break; 131d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_LOW: 132d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 133d37a65bbSShawn Guo break; 134d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_HIGH: 135d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 136d37a65bbSShawn Guo break; 137d37a65bbSShawn Guo default: 138d37a65bbSShawn Guo return -EINVAL; 139d37a65bbSShawn Guo } 140d37a65bbSShawn Guo 141d37a65bbSShawn Guo reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 142d37a65bbSShawn Guo bit = gpio & 0xf; 143b78d8e59SShawn Guo val = readl(reg) & ~(0x3 << (bit << 1)); 144b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 145d37a65bbSShawn Guo _clear_gpio_irqstatus(port, gpio & 0x1f); 146d37a65bbSShawn Guo 147d37a65bbSShawn Guo return 0; 148d37a65bbSShawn Guo } 149d37a65bbSShawn Guo 150d37a65bbSShawn Guo static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 151d37a65bbSShawn Guo { 152d37a65bbSShawn Guo void __iomem *reg = port->base; 153d37a65bbSShawn Guo u32 bit, val; 154d37a65bbSShawn Guo int edge; 155d37a65bbSShawn Guo 156d37a65bbSShawn Guo reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 157d37a65bbSShawn Guo bit = gpio & 0xf; 158b78d8e59SShawn Guo val = readl(reg); 159d37a65bbSShawn Guo edge = (val >> (bit << 1)) & 3; 160d37a65bbSShawn Guo val &= ~(0x3 << (bit << 1)); 161d37a65bbSShawn Guo if (edge == GPIO_INT_HIGH_LEV) { 162d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 163d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 164d37a65bbSShawn Guo } else if (edge == GPIO_INT_LOW_LEV) { 165d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 166d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 167d37a65bbSShawn Guo } else { 168d37a65bbSShawn Guo pr_err("mxc: invalid configuration for GPIO %d: %x\n", 169d37a65bbSShawn Guo gpio, edge); 170d37a65bbSShawn Guo return; 171d37a65bbSShawn Guo } 172b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 173d37a65bbSShawn Guo } 174d37a65bbSShawn Guo 175d37a65bbSShawn Guo /* handle 32 interrupts in one status register */ 176d37a65bbSShawn Guo static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 177d37a65bbSShawn Guo { 178d37a65bbSShawn Guo u32 gpio_irq_no_base = port->virtual_irq_start; 179d37a65bbSShawn Guo 180d37a65bbSShawn Guo while (irq_stat != 0) { 181d37a65bbSShawn Guo int irqoffset = fls(irq_stat) - 1; 182d37a65bbSShawn Guo 183d37a65bbSShawn Guo if (port->both_edges & (1 << irqoffset)) 184d37a65bbSShawn Guo mxc_flip_edge(port, irqoffset); 185d37a65bbSShawn Guo 186d37a65bbSShawn Guo generic_handle_irq(gpio_irq_no_base + irqoffset); 187d37a65bbSShawn Guo 188d37a65bbSShawn Guo irq_stat &= ~(1 << irqoffset); 189d37a65bbSShawn Guo } 190d37a65bbSShawn Guo } 191d37a65bbSShawn Guo 192d37a65bbSShawn Guo /* MX1 and MX3 has one interrupt *per* gpio port */ 193d37a65bbSShawn Guo static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) 194d37a65bbSShawn Guo { 195d37a65bbSShawn Guo u32 irq_stat; 196d37a65bbSShawn Guo struct mxc_gpio_port *port = irq_get_handler_data(irq); 197d37a65bbSShawn Guo 198b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 199d37a65bbSShawn Guo 200d37a65bbSShawn Guo mxc_gpio_irq_handler(port, irq_stat); 201d37a65bbSShawn Guo } 202d37a65bbSShawn Guo 203d37a65bbSShawn Guo /* MX2 has one interrupt *for all* gpio ports */ 204d37a65bbSShawn Guo static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) 205d37a65bbSShawn Guo { 206d37a65bbSShawn Guo u32 irq_msk, irq_stat; 207b78d8e59SShawn Guo struct mxc_gpio_port *port; 208d37a65bbSShawn Guo 209d37a65bbSShawn Guo /* walk through all interrupt status registers */ 210b78d8e59SShawn Guo list_for_each_entry(port, &mxc_gpio_ports, node) { 211b78d8e59SShawn Guo irq_msk = readl(port->base + GPIO_IMR); 212d37a65bbSShawn Guo if (!irq_msk) 213d37a65bbSShawn Guo continue; 214d37a65bbSShawn Guo 215b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 216d37a65bbSShawn Guo if (irq_stat) 217b78d8e59SShawn Guo mxc_gpio_irq_handler(port, irq_stat); 218d37a65bbSShawn Guo } 219d37a65bbSShawn Guo } 220d37a65bbSShawn Guo 221d37a65bbSShawn Guo /* 222d37a65bbSShawn Guo * Set interrupt number "irq" in the GPIO as a wake-up source. 223d37a65bbSShawn Guo * While system is running, all registered GPIO interrupts need to have 224d37a65bbSShawn Guo * wake-up enabled. When system is suspended, only selected GPIO interrupts 225d37a65bbSShawn Guo * need to have wake-up enabled. 226d37a65bbSShawn Guo * @param irq interrupt source number 227d37a65bbSShawn Guo * @param enable enable as wake-up if equal to non-zero 228d37a65bbSShawn Guo * @return This function returns 0 on success. 229d37a65bbSShawn Guo */ 230d37a65bbSShawn Guo static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 231d37a65bbSShawn Guo { 232d37a65bbSShawn Guo u32 gpio = irq_to_gpio(d->irq); 233d37a65bbSShawn Guo u32 gpio_idx = gpio & 0x1F; 234b78d8e59SShawn Guo struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d); 235d37a65bbSShawn Guo 236d37a65bbSShawn Guo if (enable) { 237d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 238d37a65bbSShawn Guo enable_irq_wake(port->irq_high); 239d37a65bbSShawn Guo else 240d37a65bbSShawn Guo enable_irq_wake(port->irq); 241d37a65bbSShawn Guo } else { 242d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 243d37a65bbSShawn Guo disable_irq_wake(port->irq_high); 244d37a65bbSShawn Guo else 245d37a65bbSShawn Guo disable_irq_wake(port->irq); 246d37a65bbSShawn Guo } 247d37a65bbSShawn Guo 248d37a65bbSShawn Guo return 0; 249d37a65bbSShawn Guo } 250d37a65bbSShawn Guo 251d37a65bbSShawn Guo static struct irq_chip gpio_irq_chip = { 252d37a65bbSShawn Guo .name = "GPIO", 253d37a65bbSShawn Guo .irq_ack = gpio_ack_irq, 254d37a65bbSShawn Guo .irq_mask = gpio_mask_irq, 255d37a65bbSShawn Guo .irq_unmask = gpio_unmask_irq, 256d37a65bbSShawn Guo .irq_set_type = gpio_set_irq_type, 257d37a65bbSShawn Guo .irq_set_wake = gpio_set_wake_irq, 258d37a65bbSShawn Guo }; 259d37a65bbSShawn Guo 260d37a65bbSShawn Guo /* 261d37a65bbSShawn Guo * This lock class tells lockdep that GPIO irqs are in a different 262d37a65bbSShawn Guo * category than their parents, so it won't report false recursion. 263d37a65bbSShawn Guo */ 264d37a65bbSShawn Guo static struct lock_class_key gpio_lock_class; 265d37a65bbSShawn Guo 266b78d8e59SShawn Guo static int __devinit mxc_gpio_probe(struct platform_device *pdev) 267d37a65bbSShawn Guo { 268b78d8e59SShawn Guo struct mxc_gpio_port *port; 269b78d8e59SShawn Guo struct resource *iores; 270b78d8e59SShawn Guo int err, i; 271d37a65bbSShawn Guo 272b78d8e59SShawn Guo port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL); 273b78d8e59SShawn Guo if (!port) 274b78d8e59SShawn Guo return -ENOMEM; 275d37a65bbSShawn Guo 276b78d8e59SShawn Guo port->virtual_irq_start = MXC_GPIO_IRQ_START + pdev->id * 32; 277d37a65bbSShawn Guo 278b78d8e59SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 279b78d8e59SShawn Guo if (!iores) { 280b78d8e59SShawn Guo err = -ENODEV; 281b78d8e59SShawn Guo goto out_kfree; 282b78d8e59SShawn Guo } 283b78d8e59SShawn Guo 284b78d8e59SShawn Guo if (!request_mem_region(iores->start, resource_size(iores), 285b78d8e59SShawn Guo pdev->name)) { 286b78d8e59SShawn Guo err = -EBUSY; 287b78d8e59SShawn Guo goto out_kfree; 288b78d8e59SShawn Guo } 289b78d8e59SShawn Guo 290b78d8e59SShawn Guo port->base = ioremap(iores->start, resource_size(iores)); 291b78d8e59SShawn Guo if (!port->base) { 292b78d8e59SShawn Guo err = -ENOMEM; 293b78d8e59SShawn Guo goto out_release_mem; 294b78d8e59SShawn Guo } 295b78d8e59SShawn Guo 296b78d8e59SShawn Guo port->irq_high = platform_get_irq(pdev, 1); 297b78d8e59SShawn Guo port->irq = platform_get_irq(pdev, 0); 298b78d8e59SShawn Guo if (port->irq < 0) { 299b78d8e59SShawn Guo err = -EINVAL; 300b78d8e59SShawn Guo goto out_iounmap; 301b78d8e59SShawn Guo } 302b78d8e59SShawn Guo 303d37a65bbSShawn Guo /* disable the interrupt and clear the status */ 304b78d8e59SShawn Guo writel(0, port->base + GPIO_IMR); 305b78d8e59SShawn Guo writel(~0, port->base + GPIO_ISR); 306d37a65bbSShawn Guo 307b78d8e59SShawn Guo for (i = port->virtual_irq_start; 308b78d8e59SShawn Guo i < port->virtual_irq_start + 32; i++) { 309b78d8e59SShawn Guo irq_set_lockdep_class(i, &gpio_lock_class); 310b78d8e59SShawn Guo irq_set_chip_and_handler(i, &gpio_irq_chip, handle_level_irq); 311b78d8e59SShawn Guo set_irq_flags(i, IRQF_VALID); 312b78d8e59SShawn Guo irq_set_chip_data(i, port); 313d37a65bbSShawn Guo } 314d37a65bbSShawn Guo 315d37a65bbSShawn Guo if (cpu_is_mx2()) { 316d37a65bbSShawn Guo /* setup one handler for all GPIO interrupts */ 317b78d8e59SShawn Guo if (pdev->id == 0) 318b78d8e59SShawn Guo irq_set_chained_handler(port->irq, 319b78d8e59SShawn Guo mx2_gpio_irq_handler); 320b78d8e59SShawn Guo } else { 321b78d8e59SShawn Guo /* setup one handler for each entry */ 322b78d8e59SShawn Guo irq_set_chained_handler(port->irq, mx3_gpio_irq_handler); 323b78d8e59SShawn Guo irq_set_handler_data(port->irq, port); 324b78d8e59SShawn Guo if (port->irq_high > 0) { 325b78d8e59SShawn Guo /* setup handler for GPIO 16 to 31 */ 326b78d8e59SShawn Guo irq_set_chained_handler(port->irq_high, 327b78d8e59SShawn Guo mx3_gpio_irq_handler); 328b78d8e59SShawn Guo irq_set_handler_data(port->irq_high, port); 329b78d8e59SShawn Guo } 330d37a65bbSShawn Guo } 331d37a65bbSShawn Guo 3322ce420daSShawn Guo err = bgpio_init(&port->bgc, &pdev->dev, 4, 3332ce420daSShawn Guo port->base + GPIO_PSR, 3342ce420daSShawn Guo port->base + GPIO_DR, NULL, 3352ce420daSShawn Guo port->base + GPIO_GDIR, NULL, false); 336b78d8e59SShawn Guo if (err) 337b78d8e59SShawn Guo goto out_iounmap; 338b78d8e59SShawn Guo 3392ce420daSShawn Guo port->bgc.gc.base = pdev->id * 32; 3402ce420daSShawn Guo 3412ce420daSShawn Guo err = gpiochip_add(&port->bgc.gc); 3422ce420daSShawn Guo if (err) 3432ce420daSShawn Guo goto out_bgpio_remove; 3442ce420daSShawn Guo 345b78d8e59SShawn Guo list_add_tail(&port->node, &mxc_gpio_ports); 346b78d8e59SShawn Guo 347d37a65bbSShawn Guo return 0; 348b78d8e59SShawn Guo 3492ce420daSShawn Guo out_bgpio_remove: 3502ce420daSShawn Guo bgpio_remove(&port->bgc); 351b78d8e59SShawn Guo out_iounmap: 352b78d8e59SShawn Guo iounmap(port->base); 353b78d8e59SShawn Guo out_release_mem: 354b78d8e59SShawn Guo release_mem_region(iores->start, resource_size(iores)); 355b78d8e59SShawn Guo out_kfree: 356b78d8e59SShawn Guo kfree(port); 357b78d8e59SShawn Guo dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 358b78d8e59SShawn Guo return err; 359d37a65bbSShawn Guo } 360b78d8e59SShawn Guo 361b78d8e59SShawn Guo static struct platform_driver mxc_gpio_driver = { 362b78d8e59SShawn Guo .driver = { 363b78d8e59SShawn Guo .name = "gpio-mxc", 364b78d8e59SShawn Guo .owner = THIS_MODULE, 365b78d8e59SShawn Guo }, 366b78d8e59SShawn Guo .probe = mxc_gpio_probe, 367b78d8e59SShawn Guo }; 368b78d8e59SShawn Guo 369b78d8e59SShawn Guo static int __init gpio_mxc_init(void) 370b78d8e59SShawn Guo { 371b78d8e59SShawn Guo return platform_driver_register(&mxc_gpio_driver); 372b78d8e59SShawn Guo } 373b78d8e59SShawn Guo postcore_initcall(gpio_mxc_init); 374b78d8e59SShawn Guo 375b78d8e59SShawn Guo MODULE_AUTHOR("Freescale Semiconductor, " 376b78d8e59SShawn Guo "Daniel Mack <danielncaiaq.de>, " 377b78d8e59SShawn Guo "Juergen Beisert <kernel@pengutronix.de>"); 378b78d8e59SShawn Guo MODULE_DESCRIPTION("Freescale MXC GPIO"); 379b78d8e59SShawn Guo MODULE_LICENSE("GPL"); 380