1014e420dSFabio Estevam // SPDX-License-Identifier: GPL-2.0+ 2014e420dSFabio Estevam // 3014e420dSFabio Estevam // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 4014e420dSFabio Estevam // Copyright 2008 Juergen Beisert, kernel@pengutronix.de 5014e420dSFabio Estevam // 6014e420dSFabio Estevam // Based on code from Freescale Semiconductor, 7014e420dSFabio Estevam // Authors: Daniel Mack, Juergen Beisert. 8014e420dSFabio Estevam // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9d37a65bbSShawn Guo 102808801aSAnson Huang #include <linux/clk.h> 1118f92b19SFabio Estevam #include <linux/err.h> 12d37a65bbSShawn Guo #include <linux/init.h> 13d37a65bbSShawn Guo #include <linux/interrupt.h> 14d37a65bbSShawn Guo #include <linux/io.h> 15d37a65bbSShawn Guo #include <linux/irq.h> 161ab7ef15SShawn Guo #include <linux/irqdomain.h> 17de88cbb7SCatalin Marinas #include <linux/irqchip/chained_irq.h> 1812d16b39SAnson Huang #include <linux/module.h> 19b78d8e59SShawn Guo #include <linux/platform_device.h> 20b78d8e59SShawn Guo #include <linux/slab.h> 211a5287a3SAnson Huang #include <linux/syscore_ops.h> 220f4630f3SLinus Walleij #include <linux/gpio/driver.h> 238937cb60SShawn Guo #include <linux/of.h> 248937cb60SShawn Guo #include <linux/of_device.h> 2516c3bd35SChristoph Hellwig #include <linux/bug.h> 26d37a65bbSShawn Guo 27e7fc6ae7SShawn Guo enum mxc_gpio_hwtype { 28e7fc6ae7SShawn Guo IMX1_GPIO, /* runs on i.mx1 */ 29e7fc6ae7SShawn Guo IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ 30aeb27748SBenoît Thébaudeau IMX31_GPIO, /* runs on i.mx31 */ 31aeb27748SBenoît Thébaudeau IMX35_GPIO, /* runs on all other i.mx */ 32e7fc6ae7SShawn Guo }; 33e7fc6ae7SShawn Guo 34e7fc6ae7SShawn Guo /* device type dependent stuff */ 35e7fc6ae7SShawn Guo struct mxc_gpio_hwdata { 36e7fc6ae7SShawn Guo unsigned dr_reg; 37e7fc6ae7SShawn Guo unsigned gdir_reg; 38e7fc6ae7SShawn Guo unsigned psr_reg; 39e7fc6ae7SShawn Guo unsigned icr1_reg; 40e7fc6ae7SShawn Guo unsigned icr2_reg; 41e7fc6ae7SShawn Guo unsigned imr_reg; 42e7fc6ae7SShawn Guo unsigned isr_reg; 43aeb27748SBenoît Thébaudeau int edge_sel_reg; 44e7fc6ae7SShawn Guo unsigned low_level; 45e7fc6ae7SShawn Guo unsigned high_level; 46e7fc6ae7SShawn Guo unsigned rise_edge; 47e7fc6ae7SShawn Guo unsigned fall_edge; 48e7fc6ae7SShawn Guo }; 49e7fc6ae7SShawn Guo 50c19fdaeeSAnson Huang struct mxc_gpio_reg_saved { 51c19fdaeeSAnson Huang u32 icr1; 52c19fdaeeSAnson Huang u32 icr2; 53c19fdaeeSAnson Huang u32 imr; 54c19fdaeeSAnson Huang u32 gdir; 55c19fdaeeSAnson Huang u32 edge_sel; 56c19fdaeeSAnson Huang u32 dr; 57c19fdaeeSAnson Huang }; 58c19fdaeeSAnson Huang 59b78d8e59SShawn Guo struct mxc_gpio_port { 60b78d8e59SShawn Guo struct list_head node; 61b78d8e59SShawn Guo void __iomem *base; 622808801aSAnson Huang struct clk *clk; 63b78d8e59SShawn Guo int irq; 64b78d8e59SShawn Guo int irq_high; 651ab7ef15SShawn Guo struct irq_domain *domain; 660f4630f3SLinus Walleij struct gpio_chip gc; 67db5270acSBartosz Golaszewski struct device *dev; 68b78d8e59SShawn Guo u32 both_edges; 69c19fdaeeSAnson Huang struct mxc_gpio_reg_saved gpio_saved_reg; 70c19fdaeeSAnson Huang bool power_off; 71b78d8e59SShawn Guo }; 72b78d8e59SShawn Guo 73e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 74e7fc6ae7SShawn Guo .dr_reg = 0x1c, 75e7fc6ae7SShawn Guo .gdir_reg = 0x00, 76e7fc6ae7SShawn Guo .psr_reg = 0x24, 77e7fc6ae7SShawn Guo .icr1_reg = 0x28, 78e7fc6ae7SShawn Guo .icr2_reg = 0x2c, 79e7fc6ae7SShawn Guo .imr_reg = 0x30, 80e7fc6ae7SShawn Guo .isr_reg = 0x34, 81aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 82e7fc6ae7SShawn Guo .low_level = 0x03, 83e7fc6ae7SShawn Guo .high_level = 0x02, 84e7fc6ae7SShawn Guo .rise_edge = 0x00, 85e7fc6ae7SShawn Guo .fall_edge = 0x01, 86e7fc6ae7SShawn Guo }; 87e7fc6ae7SShawn Guo 88e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 89e7fc6ae7SShawn Guo .dr_reg = 0x00, 90e7fc6ae7SShawn Guo .gdir_reg = 0x04, 91e7fc6ae7SShawn Guo .psr_reg = 0x08, 92e7fc6ae7SShawn Guo .icr1_reg = 0x0c, 93e7fc6ae7SShawn Guo .icr2_reg = 0x10, 94e7fc6ae7SShawn Guo .imr_reg = 0x14, 95e7fc6ae7SShawn Guo .isr_reg = 0x18, 96aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 97aeb27748SBenoît Thébaudeau .low_level = 0x00, 98aeb27748SBenoît Thébaudeau .high_level = 0x01, 99aeb27748SBenoît Thébaudeau .rise_edge = 0x02, 100aeb27748SBenoît Thébaudeau .fall_edge = 0x03, 101aeb27748SBenoît Thébaudeau }; 102aeb27748SBenoît Thébaudeau 103aeb27748SBenoît Thébaudeau static struct mxc_gpio_hwdata imx35_gpio_hwdata = { 104aeb27748SBenoît Thébaudeau .dr_reg = 0x00, 105aeb27748SBenoît Thébaudeau .gdir_reg = 0x04, 106aeb27748SBenoît Thébaudeau .psr_reg = 0x08, 107aeb27748SBenoît Thébaudeau .icr1_reg = 0x0c, 108aeb27748SBenoît Thébaudeau .icr2_reg = 0x10, 109aeb27748SBenoît Thébaudeau .imr_reg = 0x14, 110aeb27748SBenoît Thébaudeau .isr_reg = 0x18, 111aeb27748SBenoît Thébaudeau .edge_sel_reg = 0x1c, 112e7fc6ae7SShawn Guo .low_level = 0x00, 113e7fc6ae7SShawn Guo .high_level = 0x01, 114e7fc6ae7SShawn Guo .rise_edge = 0x02, 115e7fc6ae7SShawn Guo .fall_edge = 0x03, 116e7fc6ae7SShawn Guo }; 117e7fc6ae7SShawn Guo 118e7fc6ae7SShawn Guo static enum mxc_gpio_hwtype mxc_gpio_hwtype; 119e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata *mxc_gpio_hwdata; 120e7fc6ae7SShawn Guo 121e7fc6ae7SShawn Guo #define GPIO_DR (mxc_gpio_hwdata->dr_reg) 122e7fc6ae7SShawn Guo #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg) 123e7fc6ae7SShawn Guo #define GPIO_PSR (mxc_gpio_hwdata->psr_reg) 124e7fc6ae7SShawn Guo #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg) 125e7fc6ae7SShawn Guo #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg) 126e7fc6ae7SShawn Guo #define GPIO_IMR (mxc_gpio_hwdata->imr_reg) 127e7fc6ae7SShawn Guo #define GPIO_ISR (mxc_gpio_hwdata->isr_reg) 128aeb27748SBenoît Thébaudeau #define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg) 129e7fc6ae7SShawn Guo 130e7fc6ae7SShawn Guo #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level) 131e7fc6ae7SShawn Guo #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level) 132e7fc6ae7SShawn Guo #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge) 133e7fc6ae7SShawn Guo #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge) 134aeb27748SBenoît Thébaudeau #define GPIO_INT_BOTH_EDGES 0x4 135e7fc6ae7SShawn Guo 136f4f79d40SKrzysztof Kozlowski static const struct platform_device_id mxc_gpio_devtype[] = { 137e7fc6ae7SShawn Guo { 138e7fc6ae7SShawn Guo .name = "imx1-gpio", 139e7fc6ae7SShawn Guo .driver_data = IMX1_GPIO, 140e7fc6ae7SShawn Guo }, { 141e7fc6ae7SShawn Guo .name = "imx21-gpio", 142e7fc6ae7SShawn Guo .driver_data = IMX21_GPIO, 143e7fc6ae7SShawn Guo }, { 144e7fc6ae7SShawn Guo .name = "imx31-gpio", 145e7fc6ae7SShawn Guo .driver_data = IMX31_GPIO, 146e7fc6ae7SShawn Guo }, { 147aeb27748SBenoît Thébaudeau .name = "imx35-gpio", 148aeb27748SBenoît Thébaudeau .driver_data = IMX35_GPIO, 149aeb27748SBenoît Thébaudeau }, { 150e7fc6ae7SShawn Guo /* sentinel */ 151e7fc6ae7SShawn Guo } 152e7fc6ae7SShawn Guo }; 153e7fc6ae7SShawn Guo 1548937cb60SShawn Guo static const struct of_device_id mxc_gpio_dt_ids[] = { 1558937cb60SShawn Guo { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], }, 1568937cb60SShawn Guo { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], }, 1578937cb60SShawn Guo { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], }, 158aeb27748SBenoît Thébaudeau { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], }, 159c19fdaeeSAnson Huang { .compatible = "fsl,imx7d-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], }, 1608937cb60SShawn Guo { /* sentinel */ } 1618937cb60SShawn Guo }; 16212d16b39SAnson Huang MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids); 1638937cb60SShawn Guo 164b78d8e59SShawn Guo /* 165b78d8e59SShawn Guo * MX2 has one interrupt *for all* gpio ports. The list is used 166b78d8e59SShawn Guo * to save the references to all ports, so that mx2_gpio_irq_handler 167b78d8e59SShawn Guo * can walk through all interrupt status registers. 168b78d8e59SShawn Guo */ 169b78d8e59SShawn Guo static LIST_HEAD(mxc_gpio_ports); 170d37a65bbSShawn Guo 171d37a65bbSShawn Guo /* Note: This driver assumes 32 GPIOs are handled in one register */ 172d37a65bbSShawn Guo 173d37a65bbSShawn Guo static int gpio_set_irq_type(struct irq_data *d, u32 type) 174d37a65bbSShawn Guo { 175e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 176e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 177d37a65bbSShawn Guo u32 bit, val; 1781ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 179d37a65bbSShawn Guo int edge; 180d37a65bbSShawn Guo void __iomem *reg = port->base; 181d37a65bbSShawn Guo 1821ab7ef15SShawn Guo port->both_edges &= ~(1 << gpio_idx); 183d37a65bbSShawn Guo switch (type) { 184d37a65bbSShawn Guo case IRQ_TYPE_EDGE_RISING: 185d37a65bbSShawn Guo edge = GPIO_INT_RISE_EDGE; 186d37a65bbSShawn Guo break; 187d37a65bbSShawn Guo case IRQ_TYPE_EDGE_FALLING: 188d37a65bbSShawn Guo edge = GPIO_INT_FALL_EDGE; 189d37a65bbSShawn Guo break; 190d37a65bbSShawn Guo case IRQ_TYPE_EDGE_BOTH: 191aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 192aeb27748SBenoît Thébaudeau edge = GPIO_INT_BOTH_EDGES; 193aeb27748SBenoît Thébaudeau } else { 1948d0bd9a5SLinus Walleij val = port->gc.get(&port->gc, gpio_idx); 195d37a65bbSShawn Guo if (val) { 196d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 1978d0bd9a5SLinus Walleij pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx); 198d37a65bbSShawn Guo } else { 199d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 2008d0bd9a5SLinus Walleij pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx); 201d37a65bbSShawn Guo } 2021ab7ef15SShawn Guo port->both_edges |= 1 << gpio_idx; 203aeb27748SBenoît Thébaudeau } 204d37a65bbSShawn Guo break; 205d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_LOW: 206d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 207d37a65bbSShawn Guo break; 208d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_HIGH: 209d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 210d37a65bbSShawn Guo break; 211d37a65bbSShawn Guo default: 212d37a65bbSShawn Guo return -EINVAL; 213d37a65bbSShawn Guo } 214d37a65bbSShawn Guo 215aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 216aeb27748SBenoît Thébaudeau val = readl(port->base + GPIO_EDGE_SEL); 217aeb27748SBenoît Thébaudeau if (edge == GPIO_INT_BOTH_EDGES) 218f948ad07SLinus Torvalds writel(val | (1 << gpio_idx), 219aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 220aeb27748SBenoît Thébaudeau else 221f948ad07SLinus Torvalds writel(val & ~(1 << gpio_idx), 222aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 223aeb27748SBenoît Thébaudeau } 224aeb27748SBenoît Thébaudeau 225aeb27748SBenoît Thébaudeau if (edge != GPIO_INT_BOTH_EDGES) { 226f948ad07SLinus Torvalds reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ 2271ab7ef15SShawn Guo bit = gpio_idx & 0xf; 228b78d8e59SShawn Guo val = readl(reg) & ~(0x3 << (bit << 1)); 229b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 230aeb27748SBenoît Thébaudeau } 231aeb27748SBenoît Thébaudeau 2321ab7ef15SShawn Guo writel(1 << gpio_idx, port->base + GPIO_ISR); 233d37a65bbSShawn Guo 234d37a65bbSShawn Guo return 0; 235d37a65bbSShawn Guo } 236d37a65bbSShawn Guo 237d37a65bbSShawn Guo static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 238d37a65bbSShawn Guo { 239d37a65bbSShawn Guo void __iomem *reg = port->base; 240d37a65bbSShawn Guo u32 bit, val; 241d37a65bbSShawn Guo int edge; 242d37a65bbSShawn Guo 243d37a65bbSShawn Guo reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 244d37a65bbSShawn Guo bit = gpio & 0xf; 245b78d8e59SShawn Guo val = readl(reg); 246d37a65bbSShawn Guo edge = (val >> (bit << 1)) & 3; 247d37a65bbSShawn Guo val &= ~(0x3 << (bit << 1)); 248d37a65bbSShawn Guo if (edge == GPIO_INT_HIGH_LEV) { 249d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 250d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 251d37a65bbSShawn Guo } else if (edge == GPIO_INT_LOW_LEV) { 252d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 253d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 254d37a65bbSShawn Guo } else { 255d37a65bbSShawn Guo pr_err("mxc: invalid configuration for GPIO %d: %x\n", 256d37a65bbSShawn Guo gpio, edge); 257d37a65bbSShawn Guo return; 258d37a65bbSShawn Guo } 259b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 260d37a65bbSShawn Guo } 261d37a65bbSShawn Guo 262d37a65bbSShawn Guo /* handle 32 interrupts in one status register */ 263d37a65bbSShawn Guo static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 264d37a65bbSShawn Guo { 265d37a65bbSShawn Guo while (irq_stat != 0) { 266d37a65bbSShawn Guo int irqoffset = fls(irq_stat) - 1; 267d37a65bbSShawn Guo 268d37a65bbSShawn Guo if (port->both_edges & (1 << irqoffset)) 269d37a65bbSShawn Guo mxc_flip_edge(port, irqoffset); 270d37a65bbSShawn Guo 2711ab7ef15SShawn Guo generic_handle_irq(irq_find_mapping(port->domain, irqoffset)); 272d37a65bbSShawn Guo 273d37a65bbSShawn Guo irq_stat &= ~(1 << irqoffset); 274d37a65bbSShawn Guo } 275d37a65bbSShawn Guo } 276d37a65bbSShawn Guo 277d37a65bbSShawn Guo /* MX1 and MX3 has one interrupt *per* gpio port */ 278bd0b9ac4SThomas Gleixner static void mx3_gpio_irq_handler(struct irq_desc *desc) 279d37a65bbSShawn Guo { 280d37a65bbSShawn Guo u32 irq_stat; 281476f8b4cSJiang Liu struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); 282476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 2830e44b6ecSShawn Guo 2840e44b6ecSShawn Guo chained_irq_enter(chip, desc); 285d37a65bbSShawn Guo 286b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 287d37a65bbSShawn Guo 288d37a65bbSShawn Guo mxc_gpio_irq_handler(port, irq_stat); 2890e44b6ecSShawn Guo 2900e44b6ecSShawn Guo chained_irq_exit(chip, desc); 291d37a65bbSShawn Guo } 292d37a65bbSShawn Guo 293d37a65bbSShawn Guo /* MX2 has one interrupt *for all* gpio ports */ 294bd0b9ac4SThomas Gleixner static void mx2_gpio_irq_handler(struct irq_desc *desc) 295d37a65bbSShawn Guo { 296d37a65bbSShawn Guo u32 irq_msk, irq_stat; 297b78d8e59SShawn Guo struct mxc_gpio_port *port; 298476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 299c0e811d9SUwe Kleine-König 300c0e811d9SUwe Kleine-König chained_irq_enter(chip, desc); 301d37a65bbSShawn Guo 302d37a65bbSShawn Guo /* walk through all interrupt status registers */ 303b78d8e59SShawn Guo list_for_each_entry(port, &mxc_gpio_ports, node) { 304b78d8e59SShawn Guo irq_msk = readl(port->base + GPIO_IMR); 305d37a65bbSShawn Guo if (!irq_msk) 306d37a65bbSShawn Guo continue; 307d37a65bbSShawn Guo 308b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 309d37a65bbSShawn Guo if (irq_stat) 310b78d8e59SShawn Guo mxc_gpio_irq_handler(port, irq_stat); 311d37a65bbSShawn Guo } 312c0e811d9SUwe Kleine-König chained_irq_exit(chip, desc); 313d37a65bbSShawn Guo } 314d37a65bbSShawn Guo 315d37a65bbSShawn Guo /* 316d37a65bbSShawn Guo * Set interrupt number "irq" in the GPIO as a wake-up source. 317d37a65bbSShawn Guo * While system is running, all registered GPIO interrupts need to have 318d37a65bbSShawn Guo * wake-up enabled. When system is suspended, only selected GPIO interrupts 319d37a65bbSShawn Guo * need to have wake-up enabled. 320d37a65bbSShawn Guo * @param irq interrupt source number 321d37a65bbSShawn Guo * @param enable enable as wake-up if equal to non-zero 322d37a65bbSShawn Guo * @return This function returns 0 on success. 323d37a65bbSShawn Guo */ 324d37a65bbSShawn Guo static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 325d37a65bbSShawn Guo { 326e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 327e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 3281ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 32977a4d757SPhilipp Rosenberger int ret; 330d37a65bbSShawn Guo 331d37a65bbSShawn Guo if (enable) { 332d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 33377a4d757SPhilipp Rosenberger ret = enable_irq_wake(port->irq_high); 334d37a65bbSShawn Guo else 33577a4d757SPhilipp Rosenberger ret = enable_irq_wake(port->irq); 336d37a65bbSShawn Guo } else { 337d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 33877a4d757SPhilipp Rosenberger ret = disable_irq_wake(port->irq_high); 339d37a65bbSShawn Guo else 34077a4d757SPhilipp Rosenberger ret = disable_irq_wake(port->irq); 341d37a65bbSShawn Guo } 342d37a65bbSShawn Guo 34377a4d757SPhilipp Rosenberger return ret; 344d37a65bbSShawn Guo } 345d37a65bbSShawn Guo 3469e26b0b1SPeng Fan static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) 347e4ea9333SShawn Guo { 348e4ea9333SShawn Guo struct irq_chip_generic *gc; 349e4ea9333SShawn Guo struct irq_chip_type *ct; 350db5270acSBartosz Golaszewski int rv; 351d37a65bbSShawn Guo 352db5270acSBartosz Golaszewski gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base, 353e4ea9333SShawn Guo port->base, handle_level_irq); 3549e26b0b1SPeng Fan if (!gc) 3559e26b0b1SPeng Fan return -ENOMEM; 356e4ea9333SShawn Guo gc->private = port; 357e4ea9333SShawn Guo 358e4ea9333SShawn Guo ct = gc->chip_types; 359591567a5SShawn Guo ct->chip.irq_ack = irq_gc_ack_set_bit; 360e4ea9333SShawn Guo ct->chip.irq_mask = irq_gc_mask_clr_bit; 361e4ea9333SShawn Guo ct->chip.irq_unmask = irq_gc_mask_set_bit; 362e4ea9333SShawn Guo ct->chip.irq_set_type = gpio_set_irq_type; 363591567a5SShawn Guo ct->chip.irq_set_wake = gpio_set_wake_irq; 364952cfbd3SUlises Brindis ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND; 365e4ea9333SShawn Guo ct->regs.ack = GPIO_ISR; 366e4ea9333SShawn Guo ct->regs.mask = GPIO_IMR; 367e4ea9333SShawn Guo 368db5270acSBartosz Golaszewski rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), 369db5270acSBartosz Golaszewski IRQ_GC_INIT_NESTED_LOCK, 370e4ea9333SShawn Guo IRQ_NOREQUEST, 0); 3719e26b0b1SPeng Fan 372db5270acSBartosz Golaszewski return rv; 373e4ea9333SShawn Guo } 374d37a65bbSShawn Guo 3753836309dSBill Pemberton static void mxc_gpio_get_hw(struct platform_device *pdev) 376e7fc6ae7SShawn Guo { 3778937cb60SShawn Guo const struct of_device_id *of_id = 3788937cb60SShawn Guo of_match_device(mxc_gpio_dt_ids, &pdev->dev); 3798937cb60SShawn Guo enum mxc_gpio_hwtype hwtype; 3808937cb60SShawn Guo 3818937cb60SShawn Guo if (of_id) 3828937cb60SShawn Guo pdev->id_entry = of_id->data; 3838937cb60SShawn Guo hwtype = pdev->id_entry->driver_data; 384e7fc6ae7SShawn Guo 385e7fc6ae7SShawn Guo if (mxc_gpio_hwtype) { 386e7fc6ae7SShawn Guo /* 387e7fc6ae7SShawn Guo * The driver works with a reasonable presupposition, 388e7fc6ae7SShawn Guo * that is all gpio ports must be the same type when 389e7fc6ae7SShawn Guo * running on one soc. 390e7fc6ae7SShawn Guo */ 391e7fc6ae7SShawn Guo BUG_ON(mxc_gpio_hwtype != hwtype); 392e7fc6ae7SShawn Guo return; 393e7fc6ae7SShawn Guo } 394e7fc6ae7SShawn Guo 395aeb27748SBenoît Thébaudeau if (hwtype == IMX35_GPIO) 396aeb27748SBenoît Thébaudeau mxc_gpio_hwdata = &imx35_gpio_hwdata; 397aeb27748SBenoît Thébaudeau else if (hwtype == IMX31_GPIO) 398e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx31_gpio_hwdata; 399e7fc6ae7SShawn Guo else 400e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata; 401e7fc6ae7SShawn Guo 402e7fc6ae7SShawn Guo mxc_gpio_hwtype = hwtype; 403e7fc6ae7SShawn Guo } 404e7fc6ae7SShawn Guo 40509ad8039SShawn Guo static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 40609ad8039SShawn Guo { 4070f4630f3SLinus Walleij struct mxc_gpio_port *port = gpiochip_get_data(gc); 40809ad8039SShawn Guo 4091ab7ef15SShawn Guo return irq_find_mapping(port->domain, offset); 41009ad8039SShawn Guo } 41109ad8039SShawn Guo 4123836309dSBill Pemberton static int mxc_gpio_probe(struct platform_device *pdev) 413d37a65bbSShawn Guo { 4148937cb60SShawn Guo struct device_node *np = pdev->dev.of_node; 415b78d8e59SShawn Guo struct mxc_gpio_port *port; 416c8f3d144SAnson Huang int irq_count; 4171ab7ef15SShawn Guo int irq_base; 418e4ea9333SShawn Guo int err; 419d37a65bbSShawn Guo 420e7fc6ae7SShawn Guo mxc_gpio_get_hw(pdev); 421e7fc6ae7SShawn Guo 4228cd73e4eSFabio Estevam port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 423b78d8e59SShawn Guo if (!port) 424b78d8e59SShawn Guo return -ENOMEM; 425d37a65bbSShawn Guo 426db5270acSBartosz Golaszewski port->dev = &pdev->dev; 427db5270acSBartosz Golaszewski 428123ac0e5SEnrico Weigelt, metux IT consult port->base = devm_platform_ioremap_resource(pdev, 0); 4298cd73e4eSFabio Estevam if (IS_ERR(port->base)) 4308cd73e4eSFabio Estevam return PTR_ERR(port->base); 431b78d8e59SShawn Guo 432c8f3d144SAnson Huang irq_count = platform_irq_count(pdev); 433c8f3d144SAnson Huang if (irq_count < 0) 434c8f3d144SAnson Huang return irq_count; 435c8f3d144SAnson Huang 436c8f3d144SAnson Huang if (irq_count > 1) { 437b78d8e59SShawn Guo port->irq_high = platform_get_irq(pdev, 1); 438cc9269f8SPhilipp Rosenberger if (port->irq_high < 0) 439cc9269f8SPhilipp Rosenberger port->irq_high = 0; 440c8f3d144SAnson Huang } 441cc9269f8SPhilipp Rosenberger 442b78d8e59SShawn Guo port->irq = platform_get_irq(pdev, 0); 4438cd73e4eSFabio Estevam if (port->irq < 0) 4445ea80e49SSachin Kamat return port->irq; 445b78d8e59SShawn Guo 4462808801aSAnson Huang /* the controller clock is optional */ 4477beb620fSAnson Huang port->clk = devm_clk_get_optional(&pdev->dev, NULL); 4487beb620fSAnson Huang if (IS_ERR(port->clk)) 4497beb620fSAnson Huang return PTR_ERR(port->clk); 4502808801aSAnson Huang 4512808801aSAnson Huang err = clk_prepare_enable(port->clk); 4522808801aSAnson Huang if (err) { 4532808801aSAnson Huang dev_err(&pdev->dev, "Unable to enable clock.\n"); 4542808801aSAnson Huang return err; 4552808801aSAnson Huang } 4562808801aSAnson Huang 457c19fdaeeSAnson Huang if (of_device_is_compatible(np, "fsl,imx7d-gpio")) 458c19fdaeeSAnson Huang port->power_off = true; 459c19fdaeeSAnson Huang 460d37a65bbSShawn Guo /* disable the interrupt and clear the status */ 461b78d8e59SShawn Guo writel(0, port->base + GPIO_IMR); 462b78d8e59SShawn Guo writel(~0, port->base + GPIO_ISR); 463d37a65bbSShawn Guo 464e7fc6ae7SShawn Guo if (mxc_gpio_hwtype == IMX21_GPIO) { 46533a4e985SUwe Kleine-König /* 46633a4e985SUwe Kleine-König * Setup one handler for all GPIO interrupts. Actually setting 46733a4e985SUwe Kleine-König * the handler is needed only once, but doing it for every port 46833a4e985SUwe Kleine-König * is more robust and easier. 46933a4e985SUwe Kleine-König */ 47033a4e985SUwe Kleine-König irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); 471b78d8e59SShawn Guo } else { 472b78d8e59SShawn Guo /* setup one handler for each entry */ 473e65eea54SRussell King irq_set_chained_handler_and_data(port->irq, 474e65eea54SRussell King mx3_gpio_irq_handler, port); 475e65eea54SRussell King if (port->irq_high > 0) 476b78d8e59SShawn Guo /* setup handler for GPIO 16 to 31 */ 477e65eea54SRussell King irq_set_chained_handler_and_data(port->irq_high, 478e65eea54SRussell King mx3_gpio_irq_handler, 479e65eea54SRussell King port); 480d37a65bbSShawn Guo } 481d37a65bbSShawn Guo 4820f4630f3SLinus Walleij err = bgpio_init(&port->gc, &pdev->dev, 4, 4832ce420daSShawn Guo port->base + GPIO_PSR, 4842ce420daSShawn Guo port->base + GPIO_DR, NULL, 485442b2494SVladimir Zapolskiy port->base + GPIO_GDIR, NULL, 486442b2494SVladimir Zapolskiy BGPIOF_READ_OUTPUT_REG_SET); 487b78d8e59SShawn Guo if (err) 4888cd73e4eSFabio Estevam goto out_bgio; 489b78d8e59SShawn Guo 4904c806c98SVladimir Zapolskiy port->gc.request = gpiochip_generic_request; 4914c806c98SVladimir Zapolskiy port->gc.free = gpiochip_generic_free; 4920f4630f3SLinus Walleij port->gc.to_irq = mxc_gpio_to_irq; 4930f4630f3SLinus Walleij port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : 4947e6086d9SShawn Guo pdev->id * 32; 4952ce420daSShawn Guo 496ffc56630SLaxman Dewangan err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port); 4972ce420daSShawn Guo if (err) 4980f4630f3SLinus Walleij goto out_bgio; 4992ce420daSShawn Guo 500c553c3c4SBartosz Golaszewski irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); 5011ab7ef15SShawn Guo if (irq_base < 0) { 5021ab7ef15SShawn Guo err = irq_base; 503ffc56630SLaxman Dewangan goto out_bgio; 5041ab7ef15SShawn Guo } 5051ab7ef15SShawn Guo 5061ab7ef15SShawn Guo port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, 5071ab7ef15SShawn Guo &irq_domain_simple_ops, NULL); 5081ab7ef15SShawn Guo if (!port->domain) { 5091ab7ef15SShawn Guo err = -ENODEV; 510c553c3c4SBartosz Golaszewski goto out_bgio; 5111ab7ef15SShawn Guo } 5128937cb60SShawn Guo 5138937cb60SShawn Guo /* gpio-mxc can be a generic irq chip */ 5149e26b0b1SPeng Fan err = mxc_gpio_init_gc(port, irq_base); 5159e26b0b1SPeng Fan if (err < 0) 5169e26b0b1SPeng Fan goto out_irqdomain_remove; 5178937cb60SShawn Guo 518b78d8e59SShawn Guo list_add_tail(&port->node, &mxc_gpio_ports); 519b78d8e59SShawn Guo 520c19fdaeeSAnson Huang platform_set_drvdata(pdev, port); 521c19fdaeeSAnson Huang 522d37a65bbSShawn Guo return 0; 523b78d8e59SShawn Guo 5249e26b0b1SPeng Fan out_irqdomain_remove: 5259e26b0b1SPeng Fan irq_domain_remove(port->domain); 5268cd73e4eSFabio Estevam out_bgio: 5272808801aSAnson Huang clk_disable_unprepare(port->clk); 528b78d8e59SShawn Guo dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 529b78d8e59SShawn Guo return err; 530d37a65bbSShawn Guo } 531b78d8e59SShawn Guo 532c19fdaeeSAnson Huang static void mxc_gpio_save_regs(struct mxc_gpio_port *port) 533c19fdaeeSAnson Huang { 534c19fdaeeSAnson Huang if (!port->power_off) 535c19fdaeeSAnson Huang return; 536c19fdaeeSAnson Huang 537c19fdaeeSAnson Huang port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1); 538c19fdaeeSAnson Huang port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2); 539c19fdaeeSAnson Huang port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR); 540c19fdaeeSAnson Huang port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR); 541c19fdaeeSAnson Huang port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL); 542c19fdaeeSAnson Huang port->gpio_saved_reg.dr = readl(port->base + GPIO_DR); 543c19fdaeeSAnson Huang } 544c19fdaeeSAnson Huang 545c19fdaeeSAnson Huang static void mxc_gpio_restore_regs(struct mxc_gpio_port *port) 546c19fdaeeSAnson Huang { 547c19fdaeeSAnson Huang if (!port->power_off) 548c19fdaeeSAnson Huang return; 549c19fdaeeSAnson Huang 550c19fdaeeSAnson Huang writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1); 551c19fdaeeSAnson Huang writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2); 552c19fdaeeSAnson Huang writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR); 553c19fdaeeSAnson Huang writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR); 554c19fdaeeSAnson Huang writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL); 555c19fdaeeSAnson Huang writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); 556c19fdaeeSAnson Huang } 557c19fdaeeSAnson Huang 5581a5287a3SAnson Huang static int mxc_gpio_syscore_suspend(void) 559c19fdaeeSAnson Huang { 5601a5287a3SAnson Huang struct mxc_gpio_port *port; 561c19fdaeeSAnson Huang 5621a5287a3SAnson Huang /* walk through all ports */ 5631a5287a3SAnson Huang list_for_each_entry(port, &mxc_gpio_ports, node) { 564c19fdaeeSAnson Huang mxc_gpio_save_regs(port); 565c19fdaeeSAnson Huang clk_disable_unprepare(port->clk); 5661a5287a3SAnson Huang } 567c19fdaeeSAnson Huang 568c19fdaeeSAnson Huang return 0; 569c19fdaeeSAnson Huang } 570c19fdaeeSAnson Huang 5711a5287a3SAnson Huang static void mxc_gpio_syscore_resume(void) 572c19fdaeeSAnson Huang { 5731a5287a3SAnson Huang struct mxc_gpio_port *port; 574c19fdaeeSAnson Huang int ret; 575c19fdaeeSAnson Huang 5761a5287a3SAnson Huang /* walk through all ports */ 5771a5287a3SAnson Huang list_for_each_entry(port, &mxc_gpio_ports, node) { 578c19fdaeeSAnson Huang ret = clk_prepare_enable(port->clk); 5791a5287a3SAnson Huang if (ret) { 5801a5287a3SAnson Huang pr_err("mxc: failed to enable gpio clock %d\n", ret); 5811a5287a3SAnson Huang return; 5821a5287a3SAnson Huang } 583c19fdaeeSAnson Huang mxc_gpio_restore_regs(port); 5841a5287a3SAnson Huang } 585c19fdaeeSAnson Huang } 586c19fdaeeSAnson Huang 5871a5287a3SAnson Huang static struct syscore_ops mxc_gpio_syscore_ops = { 5881a5287a3SAnson Huang .suspend = mxc_gpio_syscore_suspend, 5891a5287a3SAnson Huang .resume = mxc_gpio_syscore_resume, 590c19fdaeeSAnson Huang }; 591c19fdaeeSAnson Huang 592b78d8e59SShawn Guo static struct platform_driver mxc_gpio_driver = { 593b78d8e59SShawn Guo .driver = { 594b78d8e59SShawn Guo .name = "gpio-mxc", 5958937cb60SShawn Guo .of_match_table = mxc_gpio_dt_ids, 59690e1fc4cSBartosz Golaszewski .suppress_bind_attrs = true, 597b78d8e59SShawn Guo }, 598b78d8e59SShawn Guo .probe = mxc_gpio_probe, 599e7fc6ae7SShawn Guo .id_table = mxc_gpio_devtype, 600b78d8e59SShawn Guo }; 601b78d8e59SShawn Guo 602b78d8e59SShawn Guo static int __init gpio_mxc_init(void) 603b78d8e59SShawn Guo { 6041a5287a3SAnson Huang register_syscore_ops(&mxc_gpio_syscore_ops); 6051a5287a3SAnson Huang 606b78d8e59SShawn Guo return platform_driver_register(&mxc_gpio_driver); 607b78d8e59SShawn Guo } 608e188cbf7SVladimir Zapolskiy subsys_initcall(gpio_mxc_init); 60912d16b39SAnson Huang 61012d16b39SAnson Huang MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 61112d16b39SAnson Huang MODULE_DESCRIPTION("i.MX GPIO Driver"); 61212d16b39SAnson Huang MODULE_LICENSE("GPL"); 613