1014e420dSFabio Estevam // SPDX-License-Identifier: GPL-2.0+ 2014e420dSFabio Estevam // 3014e420dSFabio Estevam // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 4014e420dSFabio Estevam // Copyright 2008 Juergen Beisert, kernel@pengutronix.de 5014e420dSFabio Estevam // 6014e420dSFabio Estevam // Based on code from Freescale Semiconductor, 7014e420dSFabio Estevam // Authors: Daniel Mack, Juergen Beisert. 8014e420dSFabio Estevam // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9d37a65bbSShawn Guo 102808801aSAnson Huang #include <linux/clk.h> 1118f92b19SFabio Estevam #include <linux/err.h> 12d37a65bbSShawn Guo #include <linux/init.h> 13d37a65bbSShawn Guo #include <linux/interrupt.h> 14d37a65bbSShawn Guo #include <linux/io.h> 15d37a65bbSShawn Guo #include <linux/irq.h> 161ab7ef15SShawn Guo #include <linux/irqdomain.h> 17de88cbb7SCatalin Marinas #include <linux/irqchip/chained_irq.h> 18b78d8e59SShawn Guo #include <linux/platform_device.h> 19b78d8e59SShawn Guo #include <linux/slab.h> 200f4630f3SLinus Walleij #include <linux/gpio/driver.h> 218937cb60SShawn Guo #include <linux/of.h> 228937cb60SShawn Guo #include <linux/of_device.h> 2316c3bd35SChristoph Hellwig #include <linux/bug.h> 24d37a65bbSShawn Guo 25e7fc6ae7SShawn Guo enum mxc_gpio_hwtype { 26e7fc6ae7SShawn Guo IMX1_GPIO, /* runs on i.mx1 */ 27e7fc6ae7SShawn Guo IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ 28aeb27748SBenoît Thébaudeau IMX31_GPIO, /* runs on i.mx31 */ 29aeb27748SBenoît Thébaudeau IMX35_GPIO, /* runs on all other i.mx */ 30e7fc6ae7SShawn Guo }; 31e7fc6ae7SShawn Guo 32e7fc6ae7SShawn Guo /* device type dependent stuff */ 33e7fc6ae7SShawn Guo struct mxc_gpio_hwdata { 34e7fc6ae7SShawn Guo unsigned dr_reg; 35e7fc6ae7SShawn Guo unsigned gdir_reg; 36e7fc6ae7SShawn Guo unsigned psr_reg; 37e7fc6ae7SShawn Guo unsigned icr1_reg; 38e7fc6ae7SShawn Guo unsigned icr2_reg; 39e7fc6ae7SShawn Guo unsigned imr_reg; 40e7fc6ae7SShawn Guo unsigned isr_reg; 41aeb27748SBenoît Thébaudeau int edge_sel_reg; 42e7fc6ae7SShawn Guo unsigned low_level; 43e7fc6ae7SShawn Guo unsigned high_level; 44e7fc6ae7SShawn Guo unsigned rise_edge; 45e7fc6ae7SShawn Guo unsigned fall_edge; 46e7fc6ae7SShawn Guo }; 47e7fc6ae7SShawn Guo 48b78d8e59SShawn Guo struct mxc_gpio_port { 49b78d8e59SShawn Guo struct list_head node; 50b78d8e59SShawn Guo void __iomem *base; 512808801aSAnson Huang struct clk *clk; 52b78d8e59SShawn Guo int irq; 53b78d8e59SShawn Guo int irq_high; 541ab7ef15SShawn Guo struct irq_domain *domain; 550f4630f3SLinus Walleij struct gpio_chip gc; 56db5270acSBartosz Golaszewski struct device *dev; 57b78d8e59SShawn Guo u32 both_edges; 58b78d8e59SShawn Guo }; 59b78d8e59SShawn Guo 60e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 61e7fc6ae7SShawn Guo .dr_reg = 0x1c, 62e7fc6ae7SShawn Guo .gdir_reg = 0x00, 63e7fc6ae7SShawn Guo .psr_reg = 0x24, 64e7fc6ae7SShawn Guo .icr1_reg = 0x28, 65e7fc6ae7SShawn Guo .icr2_reg = 0x2c, 66e7fc6ae7SShawn Guo .imr_reg = 0x30, 67e7fc6ae7SShawn Guo .isr_reg = 0x34, 68aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 69e7fc6ae7SShawn Guo .low_level = 0x03, 70e7fc6ae7SShawn Guo .high_level = 0x02, 71e7fc6ae7SShawn Guo .rise_edge = 0x00, 72e7fc6ae7SShawn Guo .fall_edge = 0x01, 73e7fc6ae7SShawn Guo }; 74e7fc6ae7SShawn Guo 75e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 76e7fc6ae7SShawn Guo .dr_reg = 0x00, 77e7fc6ae7SShawn Guo .gdir_reg = 0x04, 78e7fc6ae7SShawn Guo .psr_reg = 0x08, 79e7fc6ae7SShawn Guo .icr1_reg = 0x0c, 80e7fc6ae7SShawn Guo .icr2_reg = 0x10, 81e7fc6ae7SShawn Guo .imr_reg = 0x14, 82e7fc6ae7SShawn Guo .isr_reg = 0x18, 83aeb27748SBenoît Thébaudeau .edge_sel_reg = -EINVAL, 84aeb27748SBenoît Thébaudeau .low_level = 0x00, 85aeb27748SBenoît Thébaudeau .high_level = 0x01, 86aeb27748SBenoît Thébaudeau .rise_edge = 0x02, 87aeb27748SBenoît Thébaudeau .fall_edge = 0x03, 88aeb27748SBenoît Thébaudeau }; 89aeb27748SBenoît Thébaudeau 90aeb27748SBenoît Thébaudeau static struct mxc_gpio_hwdata imx35_gpio_hwdata = { 91aeb27748SBenoît Thébaudeau .dr_reg = 0x00, 92aeb27748SBenoît Thébaudeau .gdir_reg = 0x04, 93aeb27748SBenoît Thébaudeau .psr_reg = 0x08, 94aeb27748SBenoît Thébaudeau .icr1_reg = 0x0c, 95aeb27748SBenoît Thébaudeau .icr2_reg = 0x10, 96aeb27748SBenoît Thébaudeau .imr_reg = 0x14, 97aeb27748SBenoît Thébaudeau .isr_reg = 0x18, 98aeb27748SBenoît Thébaudeau .edge_sel_reg = 0x1c, 99e7fc6ae7SShawn Guo .low_level = 0x00, 100e7fc6ae7SShawn Guo .high_level = 0x01, 101e7fc6ae7SShawn Guo .rise_edge = 0x02, 102e7fc6ae7SShawn Guo .fall_edge = 0x03, 103e7fc6ae7SShawn Guo }; 104e7fc6ae7SShawn Guo 105e7fc6ae7SShawn Guo static enum mxc_gpio_hwtype mxc_gpio_hwtype; 106e7fc6ae7SShawn Guo static struct mxc_gpio_hwdata *mxc_gpio_hwdata; 107e7fc6ae7SShawn Guo 108e7fc6ae7SShawn Guo #define GPIO_DR (mxc_gpio_hwdata->dr_reg) 109e7fc6ae7SShawn Guo #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg) 110e7fc6ae7SShawn Guo #define GPIO_PSR (mxc_gpio_hwdata->psr_reg) 111e7fc6ae7SShawn Guo #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg) 112e7fc6ae7SShawn Guo #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg) 113e7fc6ae7SShawn Guo #define GPIO_IMR (mxc_gpio_hwdata->imr_reg) 114e7fc6ae7SShawn Guo #define GPIO_ISR (mxc_gpio_hwdata->isr_reg) 115aeb27748SBenoît Thébaudeau #define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg) 116e7fc6ae7SShawn Guo 117e7fc6ae7SShawn Guo #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level) 118e7fc6ae7SShawn Guo #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level) 119e7fc6ae7SShawn Guo #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge) 120e7fc6ae7SShawn Guo #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge) 121aeb27748SBenoît Thébaudeau #define GPIO_INT_BOTH_EDGES 0x4 122e7fc6ae7SShawn Guo 123f4f79d40SKrzysztof Kozlowski static const struct platform_device_id mxc_gpio_devtype[] = { 124e7fc6ae7SShawn Guo { 125e7fc6ae7SShawn Guo .name = "imx1-gpio", 126e7fc6ae7SShawn Guo .driver_data = IMX1_GPIO, 127e7fc6ae7SShawn Guo }, { 128e7fc6ae7SShawn Guo .name = "imx21-gpio", 129e7fc6ae7SShawn Guo .driver_data = IMX21_GPIO, 130e7fc6ae7SShawn Guo }, { 131e7fc6ae7SShawn Guo .name = "imx31-gpio", 132e7fc6ae7SShawn Guo .driver_data = IMX31_GPIO, 133e7fc6ae7SShawn Guo }, { 134aeb27748SBenoît Thébaudeau .name = "imx35-gpio", 135aeb27748SBenoît Thébaudeau .driver_data = IMX35_GPIO, 136aeb27748SBenoît Thébaudeau }, { 137e7fc6ae7SShawn Guo /* sentinel */ 138e7fc6ae7SShawn Guo } 139e7fc6ae7SShawn Guo }; 140e7fc6ae7SShawn Guo 1418937cb60SShawn Guo static const struct of_device_id mxc_gpio_dt_ids[] = { 1428937cb60SShawn Guo { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], }, 1438937cb60SShawn Guo { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], }, 1448937cb60SShawn Guo { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], }, 145aeb27748SBenoît Thébaudeau { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], }, 1468937cb60SShawn Guo { /* sentinel */ } 1478937cb60SShawn Guo }; 1488937cb60SShawn Guo 149b78d8e59SShawn Guo /* 150b78d8e59SShawn Guo * MX2 has one interrupt *for all* gpio ports. The list is used 151b78d8e59SShawn Guo * to save the references to all ports, so that mx2_gpio_irq_handler 152b78d8e59SShawn Guo * can walk through all interrupt status registers. 153b78d8e59SShawn Guo */ 154b78d8e59SShawn Guo static LIST_HEAD(mxc_gpio_ports); 155d37a65bbSShawn Guo 156d37a65bbSShawn Guo /* Note: This driver assumes 32 GPIOs are handled in one register */ 157d37a65bbSShawn Guo 158d37a65bbSShawn Guo static int gpio_set_irq_type(struct irq_data *d, u32 type) 159d37a65bbSShawn Guo { 160e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 161e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 162d37a65bbSShawn Guo u32 bit, val; 1631ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 164d37a65bbSShawn Guo int edge; 165d37a65bbSShawn Guo void __iomem *reg = port->base; 166d37a65bbSShawn Guo 1671ab7ef15SShawn Guo port->both_edges &= ~(1 << gpio_idx); 168d37a65bbSShawn Guo switch (type) { 169d37a65bbSShawn Guo case IRQ_TYPE_EDGE_RISING: 170d37a65bbSShawn Guo edge = GPIO_INT_RISE_EDGE; 171d37a65bbSShawn Guo break; 172d37a65bbSShawn Guo case IRQ_TYPE_EDGE_FALLING: 173d37a65bbSShawn Guo edge = GPIO_INT_FALL_EDGE; 174d37a65bbSShawn Guo break; 175d37a65bbSShawn Guo case IRQ_TYPE_EDGE_BOTH: 176aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 177aeb27748SBenoît Thébaudeau edge = GPIO_INT_BOTH_EDGES; 178aeb27748SBenoît Thébaudeau } else { 1798d0bd9a5SLinus Walleij val = port->gc.get(&port->gc, gpio_idx); 180d37a65bbSShawn Guo if (val) { 181d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 1828d0bd9a5SLinus Walleij pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx); 183d37a65bbSShawn Guo } else { 184d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 1858d0bd9a5SLinus Walleij pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx); 186d37a65bbSShawn Guo } 1871ab7ef15SShawn Guo port->both_edges |= 1 << gpio_idx; 188aeb27748SBenoît Thébaudeau } 189d37a65bbSShawn Guo break; 190d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_LOW: 191d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 192d37a65bbSShawn Guo break; 193d37a65bbSShawn Guo case IRQ_TYPE_LEVEL_HIGH: 194d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 195d37a65bbSShawn Guo break; 196d37a65bbSShawn Guo default: 197d37a65bbSShawn Guo return -EINVAL; 198d37a65bbSShawn Guo } 199d37a65bbSShawn Guo 200aeb27748SBenoît Thébaudeau if (GPIO_EDGE_SEL >= 0) { 201aeb27748SBenoît Thébaudeau val = readl(port->base + GPIO_EDGE_SEL); 202aeb27748SBenoît Thébaudeau if (edge == GPIO_INT_BOTH_EDGES) 203f948ad07SLinus Torvalds writel(val | (1 << gpio_idx), 204aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 205aeb27748SBenoît Thébaudeau else 206f948ad07SLinus Torvalds writel(val & ~(1 << gpio_idx), 207aeb27748SBenoît Thébaudeau port->base + GPIO_EDGE_SEL); 208aeb27748SBenoît Thébaudeau } 209aeb27748SBenoît Thébaudeau 210aeb27748SBenoît Thébaudeau if (edge != GPIO_INT_BOTH_EDGES) { 211f948ad07SLinus Torvalds reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ 2121ab7ef15SShawn Guo bit = gpio_idx & 0xf; 213b78d8e59SShawn Guo val = readl(reg) & ~(0x3 << (bit << 1)); 214b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 215aeb27748SBenoît Thébaudeau } 216aeb27748SBenoît Thébaudeau 2171ab7ef15SShawn Guo writel(1 << gpio_idx, port->base + GPIO_ISR); 218d37a65bbSShawn Guo 219d37a65bbSShawn Guo return 0; 220d37a65bbSShawn Guo } 221d37a65bbSShawn Guo 222d37a65bbSShawn Guo static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 223d37a65bbSShawn Guo { 224d37a65bbSShawn Guo void __iomem *reg = port->base; 225d37a65bbSShawn Guo u32 bit, val; 226d37a65bbSShawn Guo int edge; 227d37a65bbSShawn Guo 228d37a65bbSShawn Guo reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 229d37a65bbSShawn Guo bit = gpio & 0xf; 230b78d8e59SShawn Guo val = readl(reg); 231d37a65bbSShawn Guo edge = (val >> (bit << 1)) & 3; 232d37a65bbSShawn Guo val &= ~(0x3 << (bit << 1)); 233d37a65bbSShawn Guo if (edge == GPIO_INT_HIGH_LEV) { 234d37a65bbSShawn Guo edge = GPIO_INT_LOW_LEV; 235d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 236d37a65bbSShawn Guo } else if (edge == GPIO_INT_LOW_LEV) { 237d37a65bbSShawn Guo edge = GPIO_INT_HIGH_LEV; 238d37a65bbSShawn Guo pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 239d37a65bbSShawn Guo } else { 240d37a65bbSShawn Guo pr_err("mxc: invalid configuration for GPIO %d: %x\n", 241d37a65bbSShawn Guo gpio, edge); 242d37a65bbSShawn Guo return; 243d37a65bbSShawn Guo } 244b78d8e59SShawn Guo writel(val | (edge << (bit << 1)), reg); 245d37a65bbSShawn Guo } 246d37a65bbSShawn Guo 247d37a65bbSShawn Guo /* handle 32 interrupts in one status register */ 248d37a65bbSShawn Guo static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 249d37a65bbSShawn Guo { 250d37a65bbSShawn Guo while (irq_stat != 0) { 251d37a65bbSShawn Guo int irqoffset = fls(irq_stat) - 1; 252d37a65bbSShawn Guo 253d37a65bbSShawn Guo if (port->both_edges & (1 << irqoffset)) 254d37a65bbSShawn Guo mxc_flip_edge(port, irqoffset); 255d37a65bbSShawn Guo 2561ab7ef15SShawn Guo generic_handle_irq(irq_find_mapping(port->domain, irqoffset)); 257d37a65bbSShawn Guo 258d37a65bbSShawn Guo irq_stat &= ~(1 << irqoffset); 259d37a65bbSShawn Guo } 260d37a65bbSShawn Guo } 261d37a65bbSShawn Guo 262d37a65bbSShawn Guo /* MX1 and MX3 has one interrupt *per* gpio port */ 263bd0b9ac4SThomas Gleixner static void mx3_gpio_irq_handler(struct irq_desc *desc) 264d37a65bbSShawn Guo { 265d37a65bbSShawn Guo u32 irq_stat; 266476f8b4cSJiang Liu struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); 267476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 2680e44b6ecSShawn Guo 2690e44b6ecSShawn Guo chained_irq_enter(chip, desc); 270d37a65bbSShawn Guo 271b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 272d37a65bbSShawn Guo 273d37a65bbSShawn Guo mxc_gpio_irq_handler(port, irq_stat); 2740e44b6ecSShawn Guo 2750e44b6ecSShawn Guo chained_irq_exit(chip, desc); 276d37a65bbSShawn Guo } 277d37a65bbSShawn Guo 278d37a65bbSShawn Guo /* MX2 has one interrupt *for all* gpio ports */ 279bd0b9ac4SThomas Gleixner static void mx2_gpio_irq_handler(struct irq_desc *desc) 280d37a65bbSShawn Guo { 281d37a65bbSShawn Guo u32 irq_msk, irq_stat; 282b78d8e59SShawn Guo struct mxc_gpio_port *port; 283476f8b4cSJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 284c0e811d9SUwe Kleine-König 285c0e811d9SUwe Kleine-König chained_irq_enter(chip, desc); 286d37a65bbSShawn Guo 287d37a65bbSShawn Guo /* walk through all interrupt status registers */ 288b78d8e59SShawn Guo list_for_each_entry(port, &mxc_gpio_ports, node) { 289b78d8e59SShawn Guo irq_msk = readl(port->base + GPIO_IMR); 290d37a65bbSShawn Guo if (!irq_msk) 291d37a65bbSShawn Guo continue; 292d37a65bbSShawn Guo 293b78d8e59SShawn Guo irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 294d37a65bbSShawn Guo if (irq_stat) 295b78d8e59SShawn Guo mxc_gpio_irq_handler(port, irq_stat); 296d37a65bbSShawn Guo } 297c0e811d9SUwe Kleine-König chained_irq_exit(chip, desc); 298d37a65bbSShawn Guo } 299d37a65bbSShawn Guo 300d37a65bbSShawn Guo /* 301d37a65bbSShawn Guo * Set interrupt number "irq" in the GPIO as a wake-up source. 302d37a65bbSShawn Guo * While system is running, all registered GPIO interrupts need to have 303d37a65bbSShawn Guo * wake-up enabled. When system is suspended, only selected GPIO interrupts 304d37a65bbSShawn Guo * need to have wake-up enabled. 305d37a65bbSShawn Guo * @param irq interrupt source number 306d37a65bbSShawn Guo * @param enable enable as wake-up if equal to non-zero 307d37a65bbSShawn Guo * @return This function returns 0 on success. 308d37a65bbSShawn Guo */ 309d37a65bbSShawn Guo static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 310d37a65bbSShawn Guo { 311e4ea9333SShawn Guo struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 312e4ea9333SShawn Guo struct mxc_gpio_port *port = gc->private; 3131ab7ef15SShawn Guo u32 gpio_idx = d->hwirq; 31477a4d757SPhilipp Rosenberger int ret; 315d37a65bbSShawn Guo 316d37a65bbSShawn Guo if (enable) { 317d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 31877a4d757SPhilipp Rosenberger ret = enable_irq_wake(port->irq_high); 319d37a65bbSShawn Guo else 32077a4d757SPhilipp Rosenberger ret = enable_irq_wake(port->irq); 321d37a65bbSShawn Guo } else { 322d37a65bbSShawn Guo if (port->irq_high && (gpio_idx >= 16)) 32377a4d757SPhilipp Rosenberger ret = disable_irq_wake(port->irq_high); 324d37a65bbSShawn Guo else 32577a4d757SPhilipp Rosenberger ret = disable_irq_wake(port->irq); 326d37a65bbSShawn Guo } 327d37a65bbSShawn Guo 32877a4d757SPhilipp Rosenberger return ret; 329d37a65bbSShawn Guo } 330d37a65bbSShawn Guo 3319e26b0b1SPeng Fan static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) 332e4ea9333SShawn Guo { 333e4ea9333SShawn Guo struct irq_chip_generic *gc; 334e4ea9333SShawn Guo struct irq_chip_type *ct; 335db5270acSBartosz Golaszewski int rv; 336d37a65bbSShawn Guo 337db5270acSBartosz Golaszewski gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base, 338e4ea9333SShawn Guo port->base, handle_level_irq); 3399e26b0b1SPeng Fan if (!gc) 3409e26b0b1SPeng Fan return -ENOMEM; 341e4ea9333SShawn Guo gc->private = port; 342e4ea9333SShawn Guo 343e4ea9333SShawn Guo ct = gc->chip_types; 344591567a5SShawn Guo ct->chip.irq_ack = irq_gc_ack_set_bit; 345e4ea9333SShawn Guo ct->chip.irq_mask = irq_gc_mask_clr_bit; 346e4ea9333SShawn Guo ct->chip.irq_unmask = irq_gc_mask_set_bit; 347e4ea9333SShawn Guo ct->chip.irq_set_type = gpio_set_irq_type; 348591567a5SShawn Guo ct->chip.irq_set_wake = gpio_set_wake_irq; 349952cfbd3SUlises Brindis ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND; 350e4ea9333SShawn Guo ct->regs.ack = GPIO_ISR; 351e4ea9333SShawn Guo ct->regs.mask = GPIO_IMR; 352e4ea9333SShawn Guo 353db5270acSBartosz Golaszewski rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), 354db5270acSBartosz Golaszewski IRQ_GC_INIT_NESTED_LOCK, 355e4ea9333SShawn Guo IRQ_NOREQUEST, 0); 3569e26b0b1SPeng Fan 357db5270acSBartosz Golaszewski return rv; 358e4ea9333SShawn Guo } 359d37a65bbSShawn Guo 3603836309dSBill Pemberton static void mxc_gpio_get_hw(struct platform_device *pdev) 361e7fc6ae7SShawn Guo { 3628937cb60SShawn Guo const struct of_device_id *of_id = 3638937cb60SShawn Guo of_match_device(mxc_gpio_dt_ids, &pdev->dev); 3648937cb60SShawn Guo enum mxc_gpio_hwtype hwtype; 3658937cb60SShawn Guo 3668937cb60SShawn Guo if (of_id) 3678937cb60SShawn Guo pdev->id_entry = of_id->data; 3688937cb60SShawn Guo hwtype = pdev->id_entry->driver_data; 369e7fc6ae7SShawn Guo 370e7fc6ae7SShawn Guo if (mxc_gpio_hwtype) { 371e7fc6ae7SShawn Guo /* 372e7fc6ae7SShawn Guo * The driver works with a reasonable presupposition, 373e7fc6ae7SShawn Guo * that is all gpio ports must be the same type when 374e7fc6ae7SShawn Guo * running on one soc. 375e7fc6ae7SShawn Guo */ 376e7fc6ae7SShawn Guo BUG_ON(mxc_gpio_hwtype != hwtype); 377e7fc6ae7SShawn Guo return; 378e7fc6ae7SShawn Guo } 379e7fc6ae7SShawn Guo 380aeb27748SBenoît Thébaudeau if (hwtype == IMX35_GPIO) 381aeb27748SBenoît Thébaudeau mxc_gpio_hwdata = &imx35_gpio_hwdata; 382aeb27748SBenoît Thébaudeau else if (hwtype == IMX31_GPIO) 383e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx31_gpio_hwdata; 384e7fc6ae7SShawn Guo else 385e7fc6ae7SShawn Guo mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata; 386e7fc6ae7SShawn Guo 387e7fc6ae7SShawn Guo mxc_gpio_hwtype = hwtype; 388e7fc6ae7SShawn Guo } 389e7fc6ae7SShawn Guo 39009ad8039SShawn Guo static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 39109ad8039SShawn Guo { 3920f4630f3SLinus Walleij struct mxc_gpio_port *port = gpiochip_get_data(gc); 39309ad8039SShawn Guo 3941ab7ef15SShawn Guo return irq_find_mapping(port->domain, offset); 39509ad8039SShawn Guo } 39609ad8039SShawn Guo 3973836309dSBill Pemberton static int mxc_gpio_probe(struct platform_device *pdev) 398d37a65bbSShawn Guo { 3998937cb60SShawn Guo struct device_node *np = pdev->dev.of_node; 400b78d8e59SShawn Guo struct mxc_gpio_port *port; 401b78d8e59SShawn Guo struct resource *iores; 4021ab7ef15SShawn Guo int irq_base; 403e4ea9333SShawn Guo int err; 404d37a65bbSShawn Guo 405e7fc6ae7SShawn Guo mxc_gpio_get_hw(pdev); 406e7fc6ae7SShawn Guo 4078cd73e4eSFabio Estevam port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 408b78d8e59SShawn Guo if (!port) 409b78d8e59SShawn Guo return -ENOMEM; 410d37a65bbSShawn Guo 411db5270acSBartosz Golaszewski port->dev = &pdev->dev; 412db5270acSBartosz Golaszewski 413b78d8e59SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4148cd73e4eSFabio Estevam port->base = devm_ioremap_resource(&pdev->dev, iores); 4158cd73e4eSFabio Estevam if (IS_ERR(port->base)) 4168cd73e4eSFabio Estevam return PTR_ERR(port->base); 417b78d8e59SShawn Guo 418b78d8e59SShawn Guo port->irq_high = platform_get_irq(pdev, 1); 419cc9269f8SPhilipp Rosenberger if (port->irq_high < 0) 420cc9269f8SPhilipp Rosenberger port->irq_high = 0; 421cc9269f8SPhilipp Rosenberger 422b78d8e59SShawn Guo port->irq = platform_get_irq(pdev, 0); 4238cd73e4eSFabio Estevam if (port->irq < 0) 4245ea80e49SSachin Kamat return port->irq; 425b78d8e59SShawn Guo 4262808801aSAnson Huang /* the controller clock is optional */ 4272808801aSAnson Huang port->clk = devm_clk_get(&pdev->dev, NULL); 4282808801aSAnson Huang if (IS_ERR(port->clk)) 4292808801aSAnson Huang port->clk = NULL; 4302808801aSAnson Huang 4312808801aSAnson Huang err = clk_prepare_enable(port->clk); 4322808801aSAnson Huang if (err) { 4332808801aSAnson Huang dev_err(&pdev->dev, "Unable to enable clock.\n"); 4342808801aSAnson Huang return err; 4352808801aSAnson Huang } 4362808801aSAnson Huang 437d37a65bbSShawn Guo /* disable the interrupt and clear the status */ 438b78d8e59SShawn Guo writel(0, port->base + GPIO_IMR); 439b78d8e59SShawn Guo writel(~0, port->base + GPIO_ISR); 440d37a65bbSShawn Guo 441e7fc6ae7SShawn Guo if (mxc_gpio_hwtype == IMX21_GPIO) { 44233a4e985SUwe Kleine-König /* 44333a4e985SUwe Kleine-König * Setup one handler for all GPIO interrupts. Actually setting 44433a4e985SUwe Kleine-König * the handler is needed only once, but doing it for every port 44533a4e985SUwe Kleine-König * is more robust and easier. 44633a4e985SUwe Kleine-König */ 44733a4e985SUwe Kleine-König irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); 448b78d8e59SShawn Guo } else { 449b78d8e59SShawn Guo /* setup one handler for each entry */ 450e65eea54SRussell King irq_set_chained_handler_and_data(port->irq, 451e65eea54SRussell King mx3_gpio_irq_handler, port); 452e65eea54SRussell King if (port->irq_high > 0) 453b78d8e59SShawn Guo /* setup handler for GPIO 16 to 31 */ 454e65eea54SRussell King irq_set_chained_handler_and_data(port->irq_high, 455e65eea54SRussell King mx3_gpio_irq_handler, 456e65eea54SRussell King port); 457d37a65bbSShawn Guo } 458d37a65bbSShawn Guo 4590f4630f3SLinus Walleij err = bgpio_init(&port->gc, &pdev->dev, 4, 4602ce420daSShawn Guo port->base + GPIO_PSR, 4612ce420daSShawn Guo port->base + GPIO_DR, NULL, 462442b2494SVladimir Zapolskiy port->base + GPIO_GDIR, NULL, 463442b2494SVladimir Zapolskiy BGPIOF_READ_OUTPUT_REG_SET); 464b78d8e59SShawn Guo if (err) 4658cd73e4eSFabio Estevam goto out_bgio; 466b78d8e59SShawn Guo 4674c806c98SVladimir Zapolskiy if (of_property_read_bool(np, "gpio-ranges")) { 4684c806c98SVladimir Zapolskiy port->gc.request = gpiochip_generic_request; 4694c806c98SVladimir Zapolskiy port->gc.free = gpiochip_generic_free; 4704c806c98SVladimir Zapolskiy } 4714c806c98SVladimir Zapolskiy 4720f4630f3SLinus Walleij port->gc.to_irq = mxc_gpio_to_irq; 4730f4630f3SLinus Walleij port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : 4747e6086d9SShawn Guo pdev->id * 32; 4752ce420daSShawn Guo 476ffc56630SLaxman Dewangan err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port); 4772ce420daSShawn Guo if (err) 4780f4630f3SLinus Walleij goto out_bgio; 4792ce420daSShawn Guo 480c553c3c4SBartosz Golaszewski irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); 4811ab7ef15SShawn Guo if (irq_base < 0) { 4821ab7ef15SShawn Guo err = irq_base; 483ffc56630SLaxman Dewangan goto out_bgio; 4841ab7ef15SShawn Guo } 4851ab7ef15SShawn Guo 4861ab7ef15SShawn Guo port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, 4871ab7ef15SShawn Guo &irq_domain_simple_ops, NULL); 4881ab7ef15SShawn Guo if (!port->domain) { 4891ab7ef15SShawn Guo err = -ENODEV; 490c553c3c4SBartosz Golaszewski goto out_bgio; 4911ab7ef15SShawn Guo } 4928937cb60SShawn Guo 4938937cb60SShawn Guo /* gpio-mxc can be a generic irq chip */ 4949e26b0b1SPeng Fan err = mxc_gpio_init_gc(port, irq_base); 4959e26b0b1SPeng Fan if (err < 0) 4969e26b0b1SPeng Fan goto out_irqdomain_remove; 4978937cb60SShawn Guo 498b78d8e59SShawn Guo list_add_tail(&port->node, &mxc_gpio_ports); 499b78d8e59SShawn Guo 500d37a65bbSShawn Guo return 0; 501b78d8e59SShawn Guo 5029e26b0b1SPeng Fan out_irqdomain_remove: 5039e26b0b1SPeng Fan irq_domain_remove(port->domain); 5048cd73e4eSFabio Estevam out_bgio: 5052808801aSAnson Huang clk_disable_unprepare(port->clk); 506b78d8e59SShawn Guo dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 507b78d8e59SShawn Guo return err; 508d37a65bbSShawn Guo } 509b78d8e59SShawn Guo 510b78d8e59SShawn Guo static struct platform_driver mxc_gpio_driver = { 511b78d8e59SShawn Guo .driver = { 512b78d8e59SShawn Guo .name = "gpio-mxc", 5138937cb60SShawn Guo .of_match_table = mxc_gpio_dt_ids, 51490e1fc4cSBartosz Golaszewski .suppress_bind_attrs = true, 515b78d8e59SShawn Guo }, 516b78d8e59SShawn Guo .probe = mxc_gpio_probe, 517e7fc6ae7SShawn Guo .id_table = mxc_gpio_devtype, 518b78d8e59SShawn Guo }; 519b78d8e59SShawn Guo 520b78d8e59SShawn Guo static int __init gpio_mxc_init(void) 521b78d8e59SShawn Guo { 522b78d8e59SShawn Guo return platform_driver_register(&mxc_gpio_driver); 523b78d8e59SShawn Guo } 524e188cbf7SVladimir Zapolskiy subsys_initcall(gpio_mxc_init); 525