1 /* 2 * GPIO driver for Marvell SoCs 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * Andrew Lunn <andrew@lunn.ch> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 * 14 * This driver is a fairly straightforward GPIO driver for the 15 * complete family of Marvell EBU SoC platforms (Orion, Dove, 16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this 17 * driver is the different register layout that exists between the 18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP 19 * platforms (MV78200 from the Discovery family and the Armada 20 * XP). Therefore, this driver handles three variants of the GPIO 21 * block: 22 * - the basic variant, called "orion-gpio", with the simplest 23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and 24 * non-SMP Discovery systems 25 * - the mv78200 variant for MV78200 Discovery systems. This variant 26 * turns the edge mask and level mask registers into CPU0 edge 27 * mask/level mask registers, and adds CPU1 edge mask/level mask 28 * registers. 29 * - the armadaxp variant for Armada XP systems. This variant keeps 30 * the normal cause/edge mask/level mask registers when the global 31 * interrupts are used, but adds per-CPU cause/edge mask/level mask 32 * registers n a separate memory area for the per-CPU GPIO 33 * interrupts. 34 */ 35 36 #include <linux/err.h> 37 #include <linux/module.h> 38 #include <linux/gpio.h> 39 #include <linux/irq.h> 40 #include <linux/slab.h> 41 #include <linux/irqdomain.h> 42 #include <linux/io.h> 43 #include <linux/of_irq.h> 44 #include <linux/of_device.h> 45 #include <linux/clk.h> 46 #include <linux/pinctrl/consumer.h> 47 #include <linux/irqchip/chained_irq.h> 48 49 /* 50 * GPIO unit register offsets. 51 */ 52 #define GPIO_OUT_OFF 0x0000 53 #define GPIO_IO_CONF_OFF 0x0004 54 #define GPIO_BLINK_EN_OFF 0x0008 55 #define GPIO_IN_POL_OFF 0x000c 56 #define GPIO_DATA_IN_OFF 0x0010 57 #define GPIO_EDGE_CAUSE_OFF 0x0014 58 #define GPIO_EDGE_MASK_OFF 0x0018 59 #define GPIO_LEVEL_MASK_OFF 0x001c 60 61 /* The MV78200 has per-CPU registers for edge mask and level mask */ 62 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) 63 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) 64 65 /* The Armada XP has per-CPU registers for interrupt cause, interrupt 66 * mask and interrupt level mask. Those are relative to the 67 * percpu_membase. */ 68 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) 69 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) 70 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) 71 72 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 73 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 74 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 75 76 #define MVEBU_MAX_GPIO_PER_BANK 32 77 78 struct mvebu_gpio_chip { 79 struct gpio_chip chip; 80 spinlock_t lock; 81 void __iomem *membase; 82 void __iomem *percpu_membase; 83 int irqbase; 84 struct irq_domain *domain; 85 int soc_variant; 86 87 /* Used to preserve GPIO registers across suspend/resume */ 88 u32 out_reg; 89 u32 io_conf_reg; 90 u32 blink_en_reg; 91 u32 in_pol_reg; 92 u32 edge_mask_regs[4]; 93 u32 level_mask_regs[4]; 94 }; 95 96 /* 97 * Functions returning addresses of individual registers for a given 98 * GPIO controller. 99 */ 100 static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip) 101 { 102 return mvchip->membase + GPIO_OUT_OFF; 103 } 104 105 static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip) 106 { 107 return mvchip->membase + GPIO_BLINK_EN_OFF; 108 } 109 110 static inline void __iomem * 111 mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip) 112 { 113 return mvchip->membase + GPIO_IO_CONF_OFF; 114 } 115 116 static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip) 117 { 118 return mvchip->membase + GPIO_IN_POL_OFF; 119 } 120 121 static inline void __iomem * 122 mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip) 123 { 124 return mvchip->membase + GPIO_DATA_IN_OFF; 125 } 126 127 static inline void __iomem * 128 mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip) 129 { 130 int cpu; 131 132 switch (mvchip->soc_variant) { 133 case MVEBU_GPIO_SOC_VARIANT_ORION: 134 case MVEBU_GPIO_SOC_VARIANT_MV78200: 135 return mvchip->membase + GPIO_EDGE_CAUSE_OFF; 136 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 137 cpu = smp_processor_id(); 138 return mvchip->percpu_membase + 139 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); 140 default: 141 BUG(); 142 } 143 } 144 145 static inline void __iomem * 146 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) 147 { 148 int cpu; 149 150 switch (mvchip->soc_variant) { 151 case MVEBU_GPIO_SOC_VARIANT_ORION: 152 return mvchip->membase + GPIO_EDGE_MASK_OFF; 153 case MVEBU_GPIO_SOC_VARIANT_MV78200: 154 cpu = smp_processor_id(); 155 return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); 156 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 157 cpu = smp_processor_id(); 158 return mvchip->percpu_membase + 159 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); 160 default: 161 BUG(); 162 } 163 } 164 165 static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip) 166 { 167 int cpu; 168 169 switch (mvchip->soc_variant) { 170 case MVEBU_GPIO_SOC_VARIANT_ORION: 171 return mvchip->membase + GPIO_LEVEL_MASK_OFF; 172 case MVEBU_GPIO_SOC_VARIANT_MV78200: 173 cpu = smp_processor_id(); 174 return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu); 175 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 176 cpu = smp_processor_id(); 177 return mvchip->percpu_membase + 178 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); 179 default: 180 BUG(); 181 } 182 } 183 184 /* 185 * Functions implementing the gpio_chip methods 186 */ 187 188 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value) 189 { 190 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 191 unsigned long flags; 192 u32 u; 193 194 spin_lock_irqsave(&mvchip->lock, flags); 195 u = readl_relaxed(mvebu_gpioreg_out(mvchip)); 196 if (value) 197 u |= 1 << pin; 198 else 199 u &= ~(1 << pin); 200 writel_relaxed(u, mvebu_gpioreg_out(mvchip)); 201 spin_unlock_irqrestore(&mvchip->lock, flags); 202 } 203 204 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin) 205 { 206 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 207 u32 u; 208 209 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) { 210 u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^ 211 readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 212 } else { 213 u = readl_relaxed(mvebu_gpioreg_out(mvchip)); 214 } 215 216 return (u >> pin) & 1; 217 } 218 219 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value) 220 { 221 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 222 unsigned long flags; 223 u32 u; 224 225 spin_lock_irqsave(&mvchip->lock, flags); 226 u = readl_relaxed(mvebu_gpioreg_blink(mvchip)); 227 if (value) 228 u |= 1 << pin; 229 else 230 u &= ~(1 << pin); 231 writel_relaxed(u, mvebu_gpioreg_blink(mvchip)); 232 spin_unlock_irqrestore(&mvchip->lock, flags); 233 } 234 235 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 236 { 237 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 238 unsigned long flags; 239 int ret; 240 u32 u; 241 242 /* Check with the pinctrl driver whether this pin is usable as 243 * an input GPIO */ 244 ret = pinctrl_gpio_direction_input(chip->base + pin); 245 if (ret) 246 return ret; 247 248 spin_lock_irqsave(&mvchip->lock, flags); 249 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); 250 u |= 1 << pin; 251 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); 252 spin_unlock_irqrestore(&mvchip->lock, flags); 253 254 return 0; 255 } 256 257 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin, 258 int value) 259 { 260 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 261 unsigned long flags; 262 int ret; 263 u32 u; 264 265 /* Check with the pinctrl driver whether this pin is usable as 266 * an output GPIO */ 267 ret = pinctrl_gpio_direction_output(chip->base + pin); 268 if (ret) 269 return ret; 270 271 mvebu_gpio_blink(chip, pin, 0); 272 mvebu_gpio_set(chip, pin, value); 273 274 spin_lock_irqsave(&mvchip->lock, flags); 275 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); 276 u &= ~(1 << pin); 277 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); 278 spin_unlock_irqrestore(&mvchip->lock, flags); 279 280 return 0; 281 } 282 283 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin) 284 { 285 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 286 return irq_create_mapping(mvchip->domain, pin); 287 } 288 289 /* 290 * Functions implementing the irq_chip methods 291 */ 292 static void mvebu_gpio_irq_ack(struct irq_data *d) 293 { 294 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 295 struct mvebu_gpio_chip *mvchip = gc->private; 296 u32 mask = ~(1 << (d->irq - gc->irq_base)); 297 298 irq_gc_lock(gc); 299 writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip)); 300 irq_gc_unlock(gc); 301 } 302 303 static void mvebu_gpio_edge_irq_mask(struct irq_data *d) 304 { 305 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 306 struct mvebu_gpio_chip *mvchip = gc->private; 307 struct irq_chip_type *ct = irq_data_get_chip_type(d); 308 u32 mask = 1 << (d->irq - gc->irq_base); 309 310 irq_gc_lock(gc); 311 ct->mask_cache_priv &= ~mask; 312 313 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip)); 314 irq_gc_unlock(gc); 315 } 316 317 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) 318 { 319 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 320 struct mvebu_gpio_chip *mvchip = gc->private; 321 struct irq_chip_type *ct = irq_data_get_chip_type(d); 322 323 u32 mask = 1 << (d->irq - gc->irq_base); 324 325 irq_gc_lock(gc); 326 ct->mask_cache_priv |= mask; 327 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip)); 328 irq_gc_unlock(gc); 329 } 330 331 static void mvebu_gpio_level_irq_mask(struct irq_data *d) 332 { 333 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 334 struct mvebu_gpio_chip *mvchip = gc->private; 335 struct irq_chip_type *ct = irq_data_get_chip_type(d); 336 337 u32 mask = 1 << (d->irq - gc->irq_base); 338 339 irq_gc_lock(gc); 340 ct->mask_cache_priv &= ~mask; 341 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip)); 342 irq_gc_unlock(gc); 343 } 344 345 static void mvebu_gpio_level_irq_unmask(struct irq_data *d) 346 { 347 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 348 struct mvebu_gpio_chip *mvchip = gc->private; 349 struct irq_chip_type *ct = irq_data_get_chip_type(d); 350 351 u32 mask = 1 << (d->irq - gc->irq_base); 352 353 irq_gc_lock(gc); 354 ct->mask_cache_priv |= mask; 355 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip)); 356 irq_gc_unlock(gc); 357 } 358 359 /***************************************************************************** 360 * MVEBU GPIO IRQ 361 * 362 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same 363 * value of the line or the opposite value. 364 * 365 * Level IRQ handlers: DATA_IN is used directly as cause register. 366 * Interrupt are masked by LEVEL_MASK registers. 367 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. 368 * Interrupt are masked by EDGE_MASK registers. 369 * Both-edge handlers: Similar to regular Edge handlers, but also swaps 370 * the polarity to catch the next line transaction. 371 * This is a race condition that might not perfectly 372 * work on some use cases. 373 * 374 * Every eight GPIO lines are grouped (OR'ed) before going up to main 375 * cause register. 376 * 377 * EDGE cause mask 378 * data-in /--------| |-----| |----\ 379 * -----| |----- ---- to main cause reg 380 * X \----------------| |----/ 381 * polarity LEVEL mask 382 * 383 ****************************************************************************/ 384 385 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) 386 { 387 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 388 struct irq_chip_type *ct = irq_data_get_chip_type(d); 389 struct mvebu_gpio_chip *mvchip = gc->private; 390 int pin; 391 u32 u; 392 393 pin = d->hwirq; 394 395 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin); 396 if (!u) 397 return -EINVAL; 398 399 type &= IRQ_TYPE_SENSE_MASK; 400 if (type == IRQ_TYPE_NONE) 401 return -EINVAL; 402 403 /* Check if we need to change chip and handler */ 404 if (!(ct->type & type)) 405 if (irq_setup_alt_chip(d, type)) 406 return -EINVAL; 407 408 /* 409 * Configure interrupt polarity. 410 */ 411 switch (type) { 412 case IRQ_TYPE_EDGE_RISING: 413 case IRQ_TYPE_LEVEL_HIGH: 414 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 415 u &= ~(1 << pin); 416 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); 417 break; 418 case IRQ_TYPE_EDGE_FALLING: 419 case IRQ_TYPE_LEVEL_LOW: 420 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 421 u |= 1 << pin; 422 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); 423 break; 424 case IRQ_TYPE_EDGE_BOTH: { 425 u32 v; 426 427 v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^ 428 readl_relaxed(mvebu_gpioreg_data_in(mvchip)); 429 430 /* 431 * set initial polarity based on current input level 432 */ 433 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 434 if (v & (1 << pin)) 435 u |= 1 << pin; /* falling */ 436 else 437 u &= ~(1 << pin); /* rising */ 438 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); 439 break; 440 } 441 } 442 return 0; 443 } 444 445 static void mvebu_gpio_irq_handler(struct irq_desc *desc) 446 { 447 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc); 448 struct irq_chip *chip = irq_desc_get_chip(desc); 449 u32 cause, type; 450 int i; 451 452 if (mvchip == NULL) 453 return; 454 455 chained_irq_enter(chip, desc); 456 457 cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) & 458 readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); 459 cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) & 460 readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); 461 462 for (i = 0; i < mvchip->chip.ngpio; i++) { 463 int irq; 464 465 irq = mvchip->irqbase + i; 466 467 if (!(cause & (1 << i))) 468 continue; 469 470 type = irq_get_trigger_type(irq); 471 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 472 /* Swap polarity (race with GPIO line) */ 473 u32 polarity; 474 475 polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 476 polarity ^= 1 << i; 477 writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip)); 478 } 479 480 generic_handle_irq(irq); 481 } 482 483 chained_irq_exit(chip, desc); 484 } 485 486 #ifdef CONFIG_DEBUG_FS 487 #include <linux/seq_file.h> 488 489 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 490 { 491 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 492 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; 493 int i; 494 495 out = readl_relaxed(mvebu_gpioreg_out(mvchip)); 496 io_conf = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); 497 blink = readl_relaxed(mvebu_gpioreg_blink(mvchip)); 498 in_pol = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 499 data_in = readl_relaxed(mvebu_gpioreg_data_in(mvchip)); 500 cause = readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)); 501 edg_msk = readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); 502 lvl_msk = readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); 503 504 for (i = 0; i < chip->ngpio; i++) { 505 const char *label; 506 u32 msk; 507 bool is_out; 508 509 label = gpiochip_is_requested(chip, i); 510 if (!label) 511 continue; 512 513 msk = 1 << i; 514 is_out = !(io_conf & msk); 515 516 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); 517 518 if (is_out) { 519 seq_printf(s, " out %s %s\n", 520 out & msk ? "hi" : "lo", 521 blink & msk ? "(blink )" : ""); 522 continue; 523 } 524 525 seq_printf(s, " in %s (act %s) - IRQ", 526 (data_in ^ in_pol) & msk ? "hi" : "lo", 527 in_pol & msk ? "lo" : "hi"); 528 if (!((edg_msk | lvl_msk) & msk)) { 529 seq_puts(s, " disabled\n"); 530 continue; 531 } 532 if (edg_msk & msk) 533 seq_puts(s, " edge "); 534 if (lvl_msk & msk) 535 seq_puts(s, " level"); 536 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); 537 } 538 } 539 #else 540 #define mvebu_gpio_dbg_show NULL 541 #endif 542 543 static const struct of_device_id mvebu_gpio_of_match[] = { 544 { 545 .compatible = "marvell,orion-gpio", 546 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 547 }, 548 { 549 .compatible = "marvell,mv78200-gpio", 550 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, 551 }, 552 { 553 .compatible = "marvell,armadaxp-gpio", 554 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, 555 }, 556 { 557 /* sentinel */ 558 }, 559 }; 560 MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match); 561 562 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) 563 { 564 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 565 int i; 566 567 mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip)); 568 mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip)); 569 mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip)); 570 mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip)); 571 572 switch (mvchip->soc_variant) { 573 case MVEBU_GPIO_SOC_VARIANT_ORION: 574 mvchip->edge_mask_regs[0] = 575 readl(mvchip->membase + GPIO_EDGE_MASK_OFF); 576 mvchip->level_mask_regs[0] = 577 readl(mvchip->membase + GPIO_LEVEL_MASK_OFF); 578 break; 579 case MVEBU_GPIO_SOC_VARIANT_MV78200: 580 for (i = 0; i < 2; i++) { 581 mvchip->edge_mask_regs[i] = 582 readl(mvchip->membase + 583 GPIO_EDGE_MASK_MV78200_OFF(i)); 584 mvchip->level_mask_regs[i] = 585 readl(mvchip->membase + 586 GPIO_LEVEL_MASK_MV78200_OFF(i)); 587 } 588 break; 589 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 590 for (i = 0; i < 4; i++) { 591 mvchip->edge_mask_regs[i] = 592 readl(mvchip->membase + 593 GPIO_EDGE_MASK_ARMADAXP_OFF(i)); 594 mvchip->level_mask_regs[i] = 595 readl(mvchip->membase + 596 GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); 597 } 598 break; 599 default: 600 BUG(); 601 } 602 603 return 0; 604 } 605 606 static int mvebu_gpio_resume(struct platform_device *pdev) 607 { 608 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 609 int i; 610 611 writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip)); 612 writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip)); 613 writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip)); 614 writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip)); 615 616 switch (mvchip->soc_variant) { 617 case MVEBU_GPIO_SOC_VARIANT_ORION: 618 writel(mvchip->edge_mask_regs[0], 619 mvchip->membase + GPIO_EDGE_MASK_OFF); 620 writel(mvchip->level_mask_regs[0], 621 mvchip->membase + GPIO_LEVEL_MASK_OFF); 622 break; 623 case MVEBU_GPIO_SOC_VARIANT_MV78200: 624 for (i = 0; i < 2; i++) { 625 writel(mvchip->edge_mask_regs[i], 626 mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i)); 627 writel(mvchip->level_mask_regs[i], 628 mvchip->membase + 629 GPIO_LEVEL_MASK_MV78200_OFF(i)); 630 } 631 break; 632 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 633 for (i = 0; i < 4; i++) { 634 writel(mvchip->edge_mask_regs[i], 635 mvchip->membase + 636 GPIO_EDGE_MASK_ARMADAXP_OFF(i)); 637 writel(mvchip->level_mask_regs[i], 638 mvchip->membase + 639 GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); 640 } 641 break; 642 default: 643 BUG(); 644 } 645 646 return 0; 647 } 648 649 static int mvebu_gpio_probe(struct platform_device *pdev) 650 { 651 struct mvebu_gpio_chip *mvchip; 652 const struct of_device_id *match; 653 struct device_node *np = pdev->dev.of_node; 654 struct resource *res; 655 struct irq_chip_generic *gc; 656 struct irq_chip_type *ct; 657 struct clk *clk; 658 unsigned int ngpios; 659 int soc_variant; 660 int i, cpu, id; 661 int err; 662 663 match = of_match_device(mvebu_gpio_of_match, &pdev->dev); 664 if (match) 665 soc_variant = (int) match->data; 666 else 667 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; 668 669 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), 670 GFP_KERNEL); 671 if (!mvchip) 672 return -ENOMEM; 673 674 platform_set_drvdata(pdev, mvchip); 675 676 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { 677 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 678 return -ENODEV; 679 } 680 681 id = of_alias_get_id(pdev->dev.of_node, "gpio"); 682 if (id < 0) { 683 dev_err(&pdev->dev, "Couldn't get OF id\n"); 684 return id; 685 } 686 687 clk = devm_clk_get(&pdev->dev, NULL); 688 /* Not all SoCs require a clock.*/ 689 if (!IS_ERR(clk)) 690 clk_prepare_enable(clk); 691 692 mvchip->soc_variant = soc_variant; 693 mvchip->chip.label = dev_name(&pdev->dev); 694 mvchip->chip.parent = &pdev->dev; 695 mvchip->chip.request = gpiochip_generic_request; 696 mvchip->chip.free = gpiochip_generic_free; 697 mvchip->chip.direction_input = mvebu_gpio_direction_input; 698 mvchip->chip.get = mvebu_gpio_get; 699 mvchip->chip.direction_output = mvebu_gpio_direction_output; 700 mvchip->chip.set = mvebu_gpio_set; 701 mvchip->chip.to_irq = mvebu_gpio_to_irq; 702 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; 703 mvchip->chip.ngpio = ngpios; 704 mvchip->chip.can_sleep = false; 705 mvchip->chip.of_node = np; 706 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; 707 708 spin_lock_init(&mvchip->lock); 709 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 710 mvchip->membase = devm_ioremap_resource(&pdev->dev, res); 711 if (IS_ERR(mvchip->membase)) 712 return PTR_ERR(mvchip->membase); 713 714 /* The Armada XP has a second range of registers for the 715 * per-CPU registers */ 716 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { 717 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 718 mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev, 719 res); 720 if (IS_ERR(mvchip->percpu_membase)) 721 return PTR_ERR(mvchip->percpu_membase); 722 } 723 724 /* 725 * Mask and clear GPIO interrupts. 726 */ 727 switch (soc_variant) { 728 case MVEBU_GPIO_SOC_VARIANT_ORION: 729 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); 730 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); 731 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); 732 break; 733 case MVEBU_GPIO_SOC_VARIANT_MV78200: 734 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); 735 for (cpu = 0; cpu < 2; cpu++) { 736 writel_relaxed(0, mvchip->membase + 737 GPIO_EDGE_MASK_MV78200_OFF(cpu)); 738 writel_relaxed(0, mvchip->membase + 739 GPIO_LEVEL_MASK_MV78200_OFF(cpu)); 740 } 741 break; 742 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 743 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); 744 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); 745 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); 746 for (cpu = 0; cpu < 4; cpu++) { 747 writel_relaxed(0, mvchip->percpu_membase + 748 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu)); 749 writel_relaxed(0, mvchip->percpu_membase + 750 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)); 751 writel_relaxed(0, mvchip->percpu_membase + 752 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu)); 753 } 754 break; 755 default: 756 BUG(); 757 } 758 759 gpiochip_add_data(&mvchip->chip, mvchip); 760 761 /* Some gpio controllers do not provide irq support */ 762 if (!of_irq_count(np)) 763 return 0; 764 765 /* Setup the interrupt handlers. Each chip can have up to 4 766 * interrupt handlers, with each handler dealing with 8 GPIO 767 * pins. */ 768 for (i = 0; i < 4; i++) { 769 int irq = platform_get_irq(pdev, i); 770 771 if (irq < 0) 772 continue; 773 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler, 774 mvchip); 775 } 776 777 mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1); 778 if (mvchip->irqbase < 0) { 779 dev_err(&pdev->dev, "no irqs\n"); 780 err = mvchip->irqbase; 781 goto err_gpiochip_add; 782 } 783 784 gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase, 785 mvchip->membase, handle_level_irq); 786 if (!gc) { 787 dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n"); 788 err = -ENOMEM; 789 goto err_gpiochip_add; 790 } 791 792 gc->private = mvchip; 793 ct = &gc->chip_types[0]; 794 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 795 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; 796 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; 797 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 798 ct->chip.name = mvchip->chip.label; 799 800 ct = &gc->chip_types[1]; 801 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 802 ct->chip.irq_ack = mvebu_gpio_irq_ack; 803 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; 804 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; 805 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 806 ct->handler = handle_edge_irq; 807 ct->chip.name = mvchip->chip.label; 808 809 irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0, 810 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); 811 812 /* Setup irq domain on top of the generic chip. */ 813 mvchip->domain = irq_domain_add_simple(np, mvchip->chip.ngpio, 814 mvchip->irqbase, 815 &irq_domain_simple_ops, 816 mvchip); 817 if (!mvchip->domain) { 818 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", 819 mvchip->chip.label); 820 err = -ENODEV; 821 goto err_generic_chip; 822 } 823 824 return 0; 825 826 err_generic_chip: 827 irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST, 828 IRQ_LEVEL | IRQ_NOPROBE); 829 kfree(gc); 830 831 err_gpiochip_add: 832 gpiochip_remove(&mvchip->chip); 833 834 return err; 835 } 836 837 static struct platform_driver mvebu_gpio_driver = { 838 .driver = { 839 .name = "mvebu-gpio", 840 .of_match_table = mvebu_gpio_of_match, 841 }, 842 .probe = mvebu_gpio_probe, 843 .suspend = mvebu_gpio_suspend, 844 .resume = mvebu_gpio_resume, 845 }; 846 module_platform_driver(mvebu_gpio_driver); 847