1 /* 2 * GPIO driver for Marvell SoCs 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * Andrew Lunn <andrew@lunn.ch> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 * 14 * This driver is a fairly straightforward GPIO driver for the 15 * complete family of Marvell EBU SoC platforms (Orion, Dove, 16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this 17 * driver is the different register layout that exists between the 18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP 19 * platforms (MV78200 from the Discovery family and the Armada 20 * XP). Therefore, this driver handles three variants of the GPIO 21 * block: 22 * - the basic variant, called "orion-gpio", with the simplest 23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and 24 * non-SMP Discovery systems 25 * - the mv78200 variant for MV78200 Discovery systems. This variant 26 * turns the edge mask and level mask registers into CPU0 edge 27 * mask/level mask registers, and adds CPU1 edge mask/level mask 28 * registers. 29 * - the armadaxp variant for Armada XP systems. This variant keeps 30 * the normal cause/edge mask/level mask registers when the global 31 * interrupts are used, but adds per-CPU cause/edge mask/level mask 32 * registers n a separate memory area for the per-CPU GPIO 33 * interrupts. 34 */ 35 36 #include <linux/bitops.h> 37 #include <linux/clk.h> 38 #include <linux/err.h> 39 #include <linux/gpio/driver.h> 40 #include <linux/gpio/consumer.h> 41 #include <linux/gpio/machine.h> 42 #include <linux/init.h> 43 #include <linux/io.h> 44 #include <linux/irq.h> 45 #include <linux/irqchip/chained_irq.h> 46 #include <linux/irqdomain.h> 47 #include <linux/mfd/syscon.h> 48 #include <linux/of_device.h> 49 #include <linux/of_irq.h> 50 #include <linux/pinctrl/consumer.h> 51 #include <linux/platform_device.h> 52 #include <linux/pwm.h> 53 #include <linux/regmap.h> 54 #include <linux/slab.h> 55 56 /* 57 * GPIO unit register offsets. 58 */ 59 #define GPIO_OUT_OFF 0x0000 60 #define GPIO_IO_CONF_OFF 0x0004 61 #define GPIO_BLINK_EN_OFF 0x0008 62 #define GPIO_IN_POL_OFF 0x000c 63 #define GPIO_DATA_IN_OFF 0x0010 64 #define GPIO_EDGE_CAUSE_OFF 0x0014 65 #define GPIO_EDGE_MASK_OFF 0x0018 66 #define GPIO_LEVEL_MASK_OFF 0x001c 67 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020 68 69 /* 70 * PWM register offsets. 71 */ 72 #define PWM_BLINK_ON_DURATION_OFF 0x0 73 #define PWM_BLINK_OFF_DURATION_OFF 0x4 74 75 76 /* The MV78200 has per-CPU registers for edge mask and level mask */ 77 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) 78 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) 79 80 /* 81 * The Armada XP has per-CPU registers for interrupt cause, interrupt 82 * mask and interrupt level mask. Those are relative to the 83 * percpu_membase. 84 */ 85 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) 86 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) 87 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) 88 89 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 90 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 91 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 92 #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4 93 94 #define MVEBU_MAX_GPIO_PER_BANK 32 95 96 struct mvebu_pwm { 97 void __iomem *membase; 98 unsigned long clk_rate; 99 struct gpio_desc *gpiod; 100 struct pwm_chip chip; 101 spinlock_t lock; 102 struct mvebu_gpio_chip *mvchip; 103 104 /* Used to preserve GPIO/PWM registers across suspend/resume */ 105 u32 blink_select; 106 u32 blink_on_duration; 107 u32 blink_off_duration; 108 }; 109 110 struct mvebu_gpio_chip { 111 struct gpio_chip chip; 112 struct regmap *regs; 113 u32 offset; 114 struct regmap *percpu_regs; 115 int irqbase; 116 struct irq_domain *domain; 117 int soc_variant; 118 119 /* Used for PWM support */ 120 struct clk *clk; 121 struct mvebu_pwm *mvpwm; 122 123 /* Used to preserve GPIO registers across suspend/resume */ 124 u32 out_reg; 125 u32 io_conf_reg; 126 u32 blink_en_reg; 127 u32 in_pol_reg; 128 u32 edge_mask_regs[4]; 129 u32 level_mask_regs[4]; 130 }; 131 132 /* 133 * Functions returning addresses of individual registers for a given 134 * GPIO controller. 135 */ 136 137 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip, 138 struct regmap **map, unsigned int *offset) 139 { 140 int cpu; 141 142 switch (mvchip->soc_variant) { 143 case MVEBU_GPIO_SOC_VARIANT_ORION: 144 case MVEBU_GPIO_SOC_VARIANT_MV78200: 145 case MVEBU_GPIO_SOC_VARIANT_A8K: 146 *map = mvchip->regs; 147 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset; 148 break; 149 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 150 cpu = smp_processor_id(); 151 *map = mvchip->percpu_regs; 152 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); 153 break; 154 default: 155 BUG(); 156 } 157 } 158 159 static u32 160 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip) 161 { 162 struct regmap *map; 163 unsigned int offset; 164 u32 val; 165 166 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); 167 regmap_read(map, offset, &val); 168 169 return val; 170 } 171 172 static void 173 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val) 174 { 175 struct regmap *map; 176 unsigned int offset; 177 178 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); 179 regmap_write(map, offset, val); 180 } 181 182 static inline void 183 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip, 184 struct regmap **map, unsigned int *offset) 185 { 186 int cpu; 187 188 switch (mvchip->soc_variant) { 189 case MVEBU_GPIO_SOC_VARIANT_ORION: 190 case MVEBU_GPIO_SOC_VARIANT_A8K: 191 *map = mvchip->regs; 192 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset; 193 break; 194 case MVEBU_GPIO_SOC_VARIANT_MV78200: 195 cpu = smp_processor_id(); 196 *map = mvchip->regs; 197 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu); 198 break; 199 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 200 cpu = smp_processor_id(); 201 *map = mvchip->percpu_regs; 202 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); 203 break; 204 default: 205 BUG(); 206 } 207 } 208 209 static u32 210 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip) 211 { 212 struct regmap *map; 213 unsigned int offset; 214 u32 val; 215 216 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); 217 regmap_read(map, offset, &val); 218 219 return val; 220 } 221 222 static void 223 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val) 224 { 225 struct regmap *map; 226 unsigned int offset; 227 228 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); 229 regmap_write(map, offset, val); 230 } 231 232 static void 233 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip, 234 struct regmap **map, unsigned int *offset) 235 { 236 int cpu; 237 238 switch (mvchip->soc_variant) { 239 case MVEBU_GPIO_SOC_VARIANT_ORION: 240 case MVEBU_GPIO_SOC_VARIANT_A8K: 241 *map = mvchip->regs; 242 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset; 243 break; 244 case MVEBU_GPIO_SOC_VARIANT_MV78200: 245 cpu = smp_processor_id(); 246 *map = mvchip->regs; 247 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu); 248 break; 249 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 250 cpu = smp_processor_id(); 251 *map = mvchip->percpu_regs; 252 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); 253 break; 254 default: 255 BUG(); 256 } 257 } 258 259 static u32 260 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip) 261 { 262 struct regmap *map; 263 unsigned int offset; 264 u32 val; 265 266 mvebu_gpioreg_level_mask(mvchip, &map, &offset); 267 regmap_read(map, offset, &val); 268 269 return val; 270 } 271 272 static void 273 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val) 274 { 275 struct regmap *map; 276 unsigned int offset; 277 278 mvebu_gpioreg_level_mask(mvchip, &map, &offset); 279 regmap_write(map, offset, val); 280 } 281 282 /* 283 * Functions returning addresses of individual registers for a given 284 * PWM controller. 285 */ 286 static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm) 287 { 288 return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF; 289 } 290 291 static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm) 292 { 293 return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF; 294 } 295 296 /* 297 * Functions implementing the gpio_chip methods 298 */ 299 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) 300 { 301 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 302 303 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 304 BIT(pin), value ? BIT(pin) : 0); 305 } 306 307 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin) 308 { 309 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 310 u32 u; 311 312 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 313 314 if (u & BIT(pin)) { 315 u32 data_in, in_pol; 316 317 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, 318 &data_in); 319 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 320 &in_pol); 321 u = data_in ^ in_pol; 322 } else { 323 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u); 324 } 325 326 return (u >> pin) & 1; 327 } 328 329 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin, 330 int value) 331 { 332 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 333 334 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 335 BIT(pin), value ? BIT(pin) : 0); 336 } 337 338 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) 339 { 340 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 341 int ret; 342 343 /* 344 * Check with the pinctrl driver whether this pin is usable as 345 * an input GPIO 346 */ 347 ret = pinctrl_gpio_direction_input(chip->base + pin); 348 if (ret) 349 return ret; 350 351 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 352 BIT(pin), BIT(pin)); 353 354 return 0; 355 } 356 357 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, 358 int value) 359 { 360 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 361 int ret; 362 363 /* 364 * Check with the pinctrl driver whether this pin is usable as 365 * an output GPIO 366 */ 367 ret = pinctrl_gpio_direction_output(chip->base + pin); 368 if (ret) 369 return ret; 370 371 mvebu_gpio_blink(chip, pin, 0); 372 mvebu_gpio_set(chip, pin, value); 373 374 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 375 BIT(pin), 0); 376 377 return 0; 378 } 379 380 static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) 381 { 382 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 383 u32 u; 384 385 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 386 387 return !!(u & BIT(pin)); 388 } 389 390 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin) 391 { 392 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 393 394 return irq_create_mapping(mvchip->domain, pin); 395 } 396 397 /* 398 * Functions implementing the irq_chip methods 399 */ 400 static void mvebu_gpio_irq_ack(struct irq_data *d) 401 { 402 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 403 struct mvebu_gpio_chip *mvchip = gc->private; 404 u32 mask = d->mask; 405 406 irq_gc_lock(gc); 407 mvebu_gpio_write_edge_cause(mvchip, ~mask); 408 irq_gc_unlock(gc); 409 } 410 411 static void mvebu_gpio_edge_irq_mask(struct irq_data *d) 412 { 413 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 414 struct mvebu_gpio_chip *mvchip = gc->private; 415 struct irq_chip_type *ct = irq_data_get_chip_type(d); 416 u32 mask = d->mask; 417 418 irq_gc_lock(gc); 419 ct->mask_cache_priv &= ~mask; 420 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); 421 irq_gc_unlock(gc); 422 } 423 424 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) 425 { 426 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 427 struct mvebu_gpio_chip *mvchip = gc->private; 428 struct irq_chip_type *ct = irq_data_get_chip_type(d); 429 u32 mask = d->mask; 430 431 irq_gc_lock(gc); 432 ct->mask_cache_priv |= mask; 433 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); 434 irq_gc_unlock(gc); 435 } 436 437 static void mvebu_gpio_level_irq_mask(struct irq_data *d) 438 { 439 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 440 struct mvebu_gpio_chip *mvchip = gc->private; 441 struct irq_chip_type *ct = irq_data_get_chip_type(d); 442 u32 mask = d->mask; 443 444 irq_gc_lock(gc); 445 ct->mask_cache_priv &= ~mask; 446 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); 447 irq_gc_unlock(gc); 448 } 449 450 static void mvebu_gpio_level_irq_unmask(struct irq_data *d) 451 { 452 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 453 struct mvebu_gpio_chip *mvchip = gc->private; 454 struct irq_chip_type *ct = irq_data_get_chip_type(d); 455 u32 mask = d->mask; 456 457 irq_gc_lock(gc); 458 ct->mask_cache_priv |= mask; 459 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); 460 irq_gc_unlock(gc); 461 } 462 463 /***************************************************************************** 464 * MVEBU GPIO IRQ 465 * 466 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same 467 * value of the line or the opposite value. 468 * 469 * Level IRQ handlers: DATA_IN is used directly as cause register. 470 * Interrupt are masked by LEVEL_MASK registers. 471 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. 472 * Interrupt are masked by EDGE_MASK registers. 473 * Both-edge handlers: Similar to regular Edge handlers, but also swaps 474 * the polarity to catch the next line transaction. 475 * This is a race condition that might not perfectly 476 * work on some use cases. 477 * 478 * Every eight GPIO lines are grouped (OR'ed) before going up to main 479 * cause register. 480 * 481 * EDGE cause mask 482 * data-in /--------| |-----| |----\ 483 * -----| |----- ---- to main cause reg 484 * X \----------------| |----/ 485 * polarity LEVEL mask 486 * 487 ****************************************************************************/ 488 489 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) 490 { 491 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 492 struct irq_chip_type *ct = irq_data_get_chip_type(d); 493 struct mvebu_gpio_chip *mvchip = gc->private; 494 int pin; 495 u32 u; 496 497 pin = d->hwirq; 498 499 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 500 if ((u & BIT(pin)) == 0) 501 return -EINVAL; 502 503 type &= IRQ_TYPE_SENSE_MASK; 504 if (type == IRQ_TYPE_NONE) 505 return -EINVAL; 506 507 /* Check if we need to change chip and handler */ 508 if (!(ct->type & type)) 509 if (irq_setup_alt_chip(d, type)) 510 return -EINVAL; 511 512 /* 513 * Configure interrupt polarity. 514 */ 515 switch (type) { 516 case IRQ_TYPE_EDGE_RISING: 517 case IRQ_TYPE_LEVEL_HIGH: 518 regmap_update_bits(mvchip->regs, 519 GPIO_IN_POL_OFF + mvchip->offset, 520 BIT(pin), 0); 521 break; 522 case IRQ_TYPE_EDGE_FALLING: 523 case IRQ_TYPE_LEVEL_LOW: 524 regmap_update_bits(mvchip->regs, 525 GPIO_IN_POL_OFF + mvchip->offset, 526 BIT(pin), BIT(pin)); 527 break; 528 case IRQ_TYPE_EDGE_BOTH: { 529 u32 data_in, in_pol, val; 530 531 regmap_read(mvchip->regs, 532 GPIO_IN_POL_OFF + mvchip->offset, &in_pol); 533 regmap_read(mvchip->regs, 534 GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 535 536 /* 537 * set initial polarity based on current input level 538 */ 539 if ((data_in ^ in_pol) & BIT(pin)) 540 val = BIT(pin); /* falling */ 541 else 542 val = 0; /* raising */ 543 544 regmap_update_bits(mvchip->regs, 545 GPIO_IN_POL_OFF + mvchip->offset, 546 BIT(pin), val); 547 break; 548 } 549 } 550 return 0; 551 } 552 553 static void mvebu_gpio_irq_handler(struct irq_desc *desc) 554 { 555 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc); 556 struct irq_chip *chip = irq_desc_get_chip(desc); 557 u32 cause, type, data_in, level_mask, edge_cause, edge_mask; 558 int i; 559 560 if (mvchip == NULL) 561 return; 562 563 chained_irq_enter(chip, desc); 564 565 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 566 level_mask = mvebu_gpio_read_level_mask(mvchip); 567 edge_cause = mvebu_gpio_read_edge_cause(mvchip); 568 edge_mask = mvebu_gpio_read_edge_mask(mvchip); 569 570 cause = (data_in & level_mask) | (edge_cause & edge_mask); 571 572 for (i = 0; i < mvchip->chip.ngpio; i++) { 573 int irq; 574 575 irq = irq_find_mapping(mvchip->domain, i); 576 577 if (!(cause & BIT(i))) 578 continue; 579 580 type = irq_get_trigger_type(irq); 581 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 582 /* Swap polarity (race with GPIO line) */ 583 u32 polarity; 584 585 regmap_read(mvchip->regs, 586 GPIO_IN_POL_OFF + mvchip->offset, 587 &polarity); 588 polarity ^= BIT(i); 589 regmap_write(mvchip->regs, 590 GPIO_IN_POL_OFF + mvchip->offset, 591 polarity); 592 } 593 594 generic_handle_irq(irq); 595 } 596 597 chained_irq_exit(chip, desc); 598 } 599 600 /* 601 * Functions implementing the pwm_chip methods 602 */ 603 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) 604 { 605 return container_of(chip, struct mvebu_pwm, chip); 606 } 607 608 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 609 { 610 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 611 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 612 struct gpio_desc *desc; 613 unsigned long flags; 614 int ret = 0; 615 616 spin_lock_irqsave(&mvpwm->lock, flags); 617 618 if (mvpwm->gpiod) { 619 ret = -EBUSY; 620 } else { 621 desc = gpiochip_request_own_desc(&mvchip->chip, 622 pwm->hwpwm, "mvebu-pwm", 623 GPIO_ACTIVE_HIGH, 624 GPIOD_OUT_LOW); 625 if (IS_ERR(desc)) { 626 ret = PTR_ERR(desc); 627 goto out; 628 } 629 630 mvpwm->gpiod = desc; 631 } 632 out: 633 spin_unlock_irqrestore(&mvpwm->lock, flags); 634 return ret; 635 } 636 637 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 638 { 639 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 640 unsigned long flags; 641 642 spin_lock_irqsave(&mvpwm->lock, flags); 643 gpiochip_free_own_desc(mvpwm->gpiod); 644 mvpwm->gpiod = NULL; 645 spin_unlock_irqrestore(&mvpwm->lock, flags); 646 } 647 648 static void mvebu_pwm_get_state(struct pwm_chip *chip, 649 struct pwm_device *pwm, 650 struct pwm_state *state) { 651 652 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 653 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 654 unsigned long long val; 655 unsigned long flags; 656 u32 u; 657 658 spin_lock_irqsave(&mvpwm->lock, flags); 659 660 val = (unsigned long long) 661 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm)); 662 val *= NSEC_PER_SEC; 663 do_div(val, mvpwm->clk_rate); 664 if (val > UINT_MAX) 665 state->duty_cycle = UINT_MAX; 666 else if (val) 667 state->duty_cycle = val; 668 else 669 state->duty_cycle = 1; 670 671 val = (unsigned long long) 672 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm)); 673 val *= NSEC_PER_SEC; 674 do_div(val, mvpwm->clk_rate); 675 if (val < state->duty_cycle) { 676 state->period = 1; 677 } else { 678 val -= state->duty_cycle; 679 if (val > UINT_MAX) 680 state->period = UINT_MAX; 681 else if (val) 682 state->period = val; 683 else 684 state->period = 1; 685 } 686 687 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); 688 if (u) 689 state->enabled = true; 690 else 691 state->enabled = false; 692 693 spin_unlock_irqrestore(&mvpwm->lock, flags); 694 } 695 696 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 697 const struct pwm_state *state) 698 { 699 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 700 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 701 unsigned long long val; 702 unsigned long flags; 703 unsigned int on, off; 704 705 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; 706 do_div(val, NSEC_PER_SEC); 707 if (val > UINT_MAX) 708 return -EINVAL; 709 if (val) 710 on = val; 711 else 712 on = 1; 713 714 val = (unsigned long long) mvpwm->clk_rate * 715 (state->period - state->duty_cycle); 716 do_div(val, NSEC_PER_SEC); 717 if (val > UINT_MAX) 718 return -EINVAL; 719 if (val) 720 off = val; 721 else 722 off = 1; 723 724 spin_lock_irqsave(&mvpwm->lock, flags); 725 726 writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm)); 727 writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm)); 728 if (state->enabled) 729 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); 730 else 731 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); 732 733 spin_unlock_irqrestore(&mvpwm->lock, flags); 734 735 return 0; 736 } 737 738 static const struct pwm_ops mvebu_pwm_ops = { 739 .request = mvebu_pwm_request, 740 .free = mvebu_pwm_free, 741 .get_state = mvebu_pwm_get_state, 742 .apply = mvebu_pwm_apply, 743 .owner = THIS_MODULE, 744 }; 745 746 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) 747 { 748 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 749 750 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, 751 &mvpwm->blink_select); 752 mvpwm->blink_on_duration = 753 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm)); 754 mvpwm->blink_off_duration = 755 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm)); 756 } 757 758 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) 759 { 760 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 761 762 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, 763 mvpwm->blink_select); 764 writel_relaxed(mvpwm->blink_on_duration, 765 mvebu_pwmreg_blink_on_duration(mvpwm)); 766 writel_relaxed(mvpwm->blink_off_duration, 767 mvebu_pwmreg_blink_off_duration(mvpwm)); 768 } 769 770 static int mvebu_pwm_probe(struct platform_device *pdev, 771 struct mvebu_gpio_chip *mvchip, 772 int id) 773 { 774 struct device *dev = &pdev->dev; 775 struct mvebu_pwm *mvpwm; 776 struct resource *res; 777 u32 set; 778 779 if (!of_device_is_compatible(mvchip->chip.of_node, 780 "marvell,armada-370-gpio")) 781 return 0; 782 783 /* 784 * There are only two sets of PWM configuration registers for 785 * all the GPIO lines on those SoCs which this driver reserves 786 * for the first two GPIO chips. So if the resource is missing 787 * we can't treat it as an error. 788 */ 789 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"); 790 if (!res) 791 return 0; 792 793 if (IS_ERR(mvchip->clk)) 794 return PTR_ERR(mvchip->clk); 795 796 /* 797 * Use set A for lines of GPIO chip with id 0, B for GPIO chip 798 * with id 1. Don't allow further GPIO chips to be used for PWM. 799 */ 800 if (id == 0) 801 set = 0; 802 else if (id == 1) 803 set = U32_MAX; 804 else 805 return -EINVAL; 806 regmap_write(mvchip->regs, 807 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); 808 809 mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL); 810 if (!mvpwm) 811 return -ENOMEM; 812 mvchip->mvpwm = mvpwm; 813 mvpwm->mvchip = mvchip; 814 815 mvpwm->membase = devm_ioremap_resource(dev, res); 816 if (IS_ERR(mvpwm->membase)) 817 return PTR_ERR(mvpwm->membase); 818 819 mvpwm->clk_rate = clk_get_rate(mvchip->clk); 820 if (!mvpwm->clk_rate) { 821 dev_err(dev, "failed to get clock rate\n"); 822 return -EINVAL; 823 } 824 825 mvpwm->chip.dev = dev; 826 mvpwm->chip.ops = &mvebu_pwm_ops; 827 mvpwm->chip.npwm = mvchip->chip.ngpio; 828 /* 829 * There may already be some PWM allocated, so we can't force 830 * mvpwm->chip.base to a fixed point like mvchip->chip.base. 831 * So, we let pwmchip_add() do the numbering and take the next free 832 * region. 833 */ 834 mvpwm->chip.base = -1; 835 836 spin_lock_init(&mvpwm->lock); 837 838 return pwmchip_add(&mvpwm->chip); 839 } 840 841 #ifdef CONFIG_DEBUG_FS 842 #include <linux/seq_file.h> 843 844 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 845 { 846 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 847 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; 848 int i; 849 850 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out); 851 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf); 852 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink); 853 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol); 854 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 855 cause = mvebu_gpio_read_edge_cause(mvchip); 856 edg_msk = mvebu_gpio_read_edge_mask(mvchip); 857 lvl_msk = mvebu_gpio_read_level_mask(mvchip); 858 859 for (i = 0; i < chip->ngpio; i++) { 860 const char *label; 861 u32 msk; 862 bool is_out; 863 864 label = gpiochip_is_requested(chip, i); 865 if (!label) 866 continue; 867 868 msk = BIT(i); 869 is_out = !(io_conf & msk); 870 871 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); 872 873 if (is_out) { 874 seq_printf(s, " out %s %s\n", 875 out & msk ? "hi" : "lo", 876 blink & msk ? "(blink )" : ""); 877 continue; 878 } 879 880 seq_printf(s, " in %s (act %s) - IRQ", 881 (data_in ^ in_pol) & msk ? "hi" : "lo", 882 in_pol & msk ? "lo" : "hi"); 883 if (!((edg_msk | lvl_msk) & msk)) { 884 seq_puts(s, " disabled\n"); 885 continue; 886 } 887 if (edg_msk & msk) 888 seq_puts(s, " edge "); 889 if (lvl_msk & msk) 890 seq_puts(s, " level"); 891 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); 892 } 893 } 894 #else 895 #define mvebu_gpio_dbg_show NULL 896 #endif 897 898 static const struct of_device_id mvebu_gpio_of_match[] = { 899 { 900 .compatible = "marvell,orion-gpio", 901 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 902 }, 903 { 904 .compatible = "marvell,mv78200-gpio", 905 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, 906 }, 907 { 908 .compatible = "marvell,armadaxp-gpio", 909 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, 910 }, 911 { 912 .compatible = "marvell,armada-370-gpio", 913 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 914 }, 915 { 916 .compatible = "marvell,armada-8k-gpio", 917 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K, 918 }, 919 { 920 /* sentinel */ 921 }, 922 }; 923 924 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) 925 { 926 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 927 int i; 928 929 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 930 &mvchip->out_reg); 931 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 932 &mvchip->io_conf_reg); 933 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 934 &mvchip->blink_en_reg); 935 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 936 &mvchip->in_pol_reg); 937 938 switch (mvchip->soc_variant) { 939 case MVEBU_GPIO_SOC_VARIANT_ORION: 940 case MVEBU_GPIO_SOC_VARIANT_A8K: 941 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, 942 &mvchip->edge_mask_regs[0]); 943 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, 944 &mvchip->level_mask_regs[0]); 945 break; 946 case MVEBU_GPIO_SOC_VARIANT_MV78200: 947 for (i = 0; i < 2; i++) { 948 regmap_read(mvchip->regs, 949 GPIO_EDGE_MASK_MV78200_OFF(i), 950 &mvchip->edge_mask_regs[i]); 951 regmap_read(mvchip->regs, 952 GPIO_LEVEL_MASK_MV78200_OFF(i), 953 &mvchip->level_mask_regs[i]); 954 } 955 break; 956 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 957 for (i = 0; i < 4; i++) { 958 regmap_read(mvchip->regs, 959 GPIO_EDGE_MASK_ARMADAXP_OFF(i), 960 &mvchip->edge_mask_regs[i]); 961 regmap_read(mvchip->regs, 962 GPIO_LEVEL_MASK_ARMADAXP_OFF(i), 963 &mvchip->level_mask_regs[i]); 964 } 965 break; 966 default: 967 BUG(); 968 } 969 970 if (IS_ENABLED(CONFIG_PWM)) 971 mvebu_pwm_suspend(mvchip); 972 973 return 0; 974 } 975 976 static int mvebu_gpio_resume(struct platform_device *pdev) 977 { 978 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 979 int i; 980 981 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 982 mvchip->out_reg); 983 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 984 mvchip->io_conf_reg); 985 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 986 mvchip->blink_en_reg); 987 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 988 mvchip->in_pol_reg); 989 990 switch (mvchip->soc_variant) { 991 case MVEBU_GPIO_SOC_VARIANT_ORION: 992 case MVEBU_GPIO_SOC_VARIANT_A8K: 993 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, 994 mvchip->edge_mask_regs[0]); 995 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, 996 mvchip->level_mask_regs[0]); 997 break; 998 case MVEBU_GPIO_SOC_VARIANT_MV78200: 999 for (i = 0; i < 2; i++) { 1000 regmap_write(mvchip->regs, 1001 GPIO_EDGE_MASK_MV78200_OFF(i), 1002 mvchip->edge_mask_regs[i]); 1003 regmap_write(mvchip->regs, 1004 GPIO_LEVEL_MASK_MV78200_OFF(i), 1005 mvchip->level_mask_regs[i]); 1006 } 1007 break; 1008 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 1009 for (i = 0; i < 4; i++) { 1010 regmap_write(mvchip->regs, 1011 GPIO_EDGE_MASK_ARMADAXP_OFF(i), 1012 mvchip->edge_mask_regs[i]); 1013 regmap_write(mvchip->regs, 1014 GPIO_LEVEL_MASK_ARMADAXP_OFF(i), 1015 mvchip->level_mask_regs[i]); 1016 } 1017 break; 1018 default: 1019 BUG(); 1020 } 1021 1022 if (IS_ENABLED(CONFIG_PWM)) 1023 mvebu_pwm_resume(mvchip); 1024 1025 return 0; 1026 } 1027 1028 static const struct regmap_config mvebu_gpio_regmap_config = { 1029 .reg_bits = 32, 1030 .reg_stride = 4, 1031 .val_bits = 32, 1032 .fast_io = true, 1033 }; 1034 1035 static int mvebu_gpio_probe_raw(struct platform_device *pdev, 1036 struct mvebu_gpio_chip *mvchip) 1037 { 1038 void __iomem *base; 1039 1040 base = devm_platform_ioremap_resource(pdev, 0); 1041 if (IS_ERR(base)) 1042 return PTR_ERR(base); 1043 1044 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, 1045 &mvebu_gpio_regmap_config); 1046 if (IS_ERR(mvchip->regs)) 1047 return PTR_ERR(mvchip->regs); 1048 1049 /* 1050 * For the legacy SoCs, the regmap directly maps to the GPIO 1051 * registers, so no offset is needed. 1052 */ 1053 mvchip->offset = 0; 1054 1055 /* 1056 * The Armada XP has a second range of registers for the 1057 * per-CPU registers 1058 */ 1059 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { 1060 base = devm_platform_ioremap_resource(pdev, 1); 1061 if (IS_ERR(base)) 1062 return PTR_ERR(base); 1063 1064 mvchip->percpu_regs = 1065 devm_regmap_init_mmio(&pdev->dev, base, 1066 &mvebu_gpio_regmap_config); 1067 if (IS_ERR(mvchip->percpu_regs)) 1068 return PTR_ERR(mvchip->percpu_regs); 1069 } 1070 1071 return 0; 1072 } 1073 1074 static int mvebu_gpio_probe_syscon(struct platform_device *pdev, 1075 struct mvebu_gpio_chip *mvchip) 1076 { 1077 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); 1078 if (IS_ERR(mvchip->regs)) 1079 return PTR_ERR(mvchip->regs); 1080 1081 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset)) 1082 return -EINVAL; 1083 1084 return 0; 1085 } 1086 1087 static int mvebu_gpio_probe(struct platform_device *pdev) 1088 { 1089 struct mvebu_gpio_chip *mvchip; 1090 const struct of_device_id *match; 1091 struct device_node *np = pdev->dev.of_node; 1092 struct irq_chip_generic *gc; 1093 struct irq_chip_type *ct; 1094 unsigned int ngpios; 1095 bool have_irqs; 1096 int soc_variant; 1097 int i, cpu, id; 1098 int err; 1099 1100 match = of_match_device(mvebu_gpio_of_match, &pdev->dev); 1101 if (match) 1102 soc_variant = (unsigned long) match->data; 1103 else 1104 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; 1105 1106 /* Some gpio controllers do not provide irq support */ 1107 have_irqs = of_irq_count(np) != 0; 1108 1109 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), 1110 GFP_KERNEL); 1111 if (!mvchip) 1112 return -ENOMEM; 1113 1114 platform_set_drvdata(pdev, mvchip); 1115 1116 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { 1117 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 1118 return -ENODEV; 1119 } 1120 1121 id = of_alias_get_id(pdev->dev.of_node, "gpio"); 1122 if (id < 0) { 1123 dev_err(&pdev->dev, "Couldn't get OF id\n"); 1124 return id; 1125 } 1126 1127 mvchip->clk = devm_clk_get(&pdev->dev, NULL); 1128 /* Not all SoCs require a clock.*/ 1129 if (!IS_ERR(mvchip->clk)) 1130 clk_prepare_enable(mvchip->clk); 1131 1132 mvchip->soc_variant = soc_variant; 1133 mvchip->chip.label = dev_name(&pdev->dev); 1134 mvchip->chip.parent = &pdev->dev; 1135 mvchip->chip.request = gpiochip_generic_request; 1136 mvchip->chip.free = gpiochip_generic_free; 1137 mvchip->chip.get_direction = mvebu_gpio_get_direction; 1138 mvchip->chip.direction_input = mvebu_gpio_direction_input; 1139 mvchip->chip.get = mvebu_gpio_get; 1140 mvchip->chip.direction_output = mvebu_gpio_direction_output; 1141 mvchip->chip.set = mvebu_gpio_set; 1142 if (have_irqs) 1143 mvchip->chip.to_irq = mvebu_gpio_to_irq; 1144 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; 1145 mvchip->chip.ngpio = ngpios; 1146 mvchip->chip.can_sleep = false; 1147 mvchip->chip.of_node = np; 1148 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; 1149 1150 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) 1151 err = mvebu_gpio_probe_syscon(pdev, mvchip); 1152 else 1153 err = mvebu_gpio_probe_raw(pdev, mvchip); 1154 1155 if (err) 1156 return err; 1157 1158 /* 1159 * Mask and clear GPIO interrupts. 1160 */ 1161 switch (soc_variant) { 1162 case MVEBU_GPIO_SOC_VARIANT_ORION: 1163 case MVEBU_GPIO_SOC_VARIANT_A8K: 1164 regmap_write(mvchip->regs, 1165 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0); 1166 regmap_write(mvchip->regs, 1167 GPIO_EDGE_MASK_OFF + mvchip->offset, 0); 1168 regmap_write(mvchip->regs, 1169 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0); 1170 break; 1171 case MVEBU_GPIO_SOC_VARIANT_MV78200: 1172 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); 1173 for (cpu = 0; cpu < 2; cpu++) { 1174 regmap_write(mvchip->regs, 1175 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0); 1176 regmap_write(mvchip->regs, 1177 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0); 1178 } 1179 break; 1180 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 1181 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); 1182 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); 1183 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); 1184 for (cpu = 0; cpu < 4; cpu++) { 1185 regmap_write(mvchip->percpu_regs, 1186 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0); 1187 regmap_write(mvchip->percpu_regs, 1188 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0); 1189 regmap_write(mvchip->percpu_regs, 1190 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0); 1191 } 1192 break; 1193 default: 1194 BUG(); 1195 } 1196 1197 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); 1198 1199 /* Some gpio controllers do not provide irq support */ 1200 if (!have_irqs) 1201 return 0; 1202 1203 mvchip->domain = 1204 irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL); 1205 if (!mvchip->domain) { 1206 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", 1207 mvchip->chip.label); 1208 return -ENODEV; 1209 } 1210 1211 err = irq_alloc_domain_generic_chips( 1212 mvchip->domain, ngpios, 2, np->name, handle_level_irq, 1213 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0); 1214 if (err) { 1215 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", 1216 mvchip->chip.label); 1217 goto err_domain; 1218 } 1219 1220 /* 1221 * NOTE: The common accessors cannot be used because of the percpu 1222 * access to the mask registers 1223 */ 1224 gc = irq_get_domain_generic_chip(mvchip->domain, 0); 1225 gc->private = mvchip; 1226 ct = &gc->chip_types[0]; 1227 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 1228 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; 1229 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; 1230 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1231 ct->chip.name = mvchip->chip.label; 1232 1233 ct = &gc->chip_types[1]; 1234 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 1235 ct->chip.irq_ack = mvebu_gpio_irq_ack; 1236 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; 1237 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; 1238 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1239 ct->handler = handle_edge_irq; 1240 ct->chip.name = mvchip->chip.label; 1241 1242 /* 1243 * Setup the interrupt handlers. Each chip can have up to 4 1244 * interrupt handlers, with each handler dealing with 8 GPIO 1245 * pins. 1246 */ 1247 for (i = 0; i < 4; i++) { 1248 int irq = platform_get_irq(pdev, i); 1249 1250 if (irq < 0) 1251 continue; 1252 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler, 1253 mvchip); 1254 } 1255 1256 /* Some MVEBU SoCs have simple PWM support for GPIO lines */ 1257 if (IS_ENABLED(CONFIG_PWM)) 1258 return mvebu_pwm_probe(pdev, mvchip, id); 1259 1260 return 0; 1261 1262 err_domain: 1263 irq_domain_remove(mvchip->domain); 1264 1265 return err; 1266 } 1267 1268 static struct platform_driver mvebu_gpio_driver = { 1269 .driver = { 1270 .name = "mvebu-gpio", 1271 .of_match_table = mvebu_gpio_of_match, 1272 }, 1273 .probe = mvebu_gpio_probe, 1274 .suspend = mvebu_gpio_suspend, 1275 .resume = mvebu_gpio_resume, 1276 }; 1277 builtin_platform_driver(mvebu_gpio_driver); 1278