1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for Marvell SoCs 4 * 5 * Copyright (C) 2012 Marvell 6 * 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 * Andrew Lunn <andrew@lunn.ch> 9 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 10 * 11 * This driver is a fairly straightforward GPIO driver for the 12 * complete family of Marvell EBU SoC platforms (Orion, Dove, 13 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this 14 * driver is the different register layout that exists between the 15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP 16 * platforms (MV78200 from the Discovery family and the Armada 17 * XP). Therefore, this driver handles three variants of the GPIO 18 * block: 19 * - the basic variant, called "orion-gpio", with the simplest 20 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and 21 * non-SMP Discovery systems 22 * - the mv78200 variant for MV78200 Discovery systems. This variant 23 * turns the edge mask and level mask registers into CPU0 edge 24 * mask/level mask registers, and adds CPU1 edge mask/level mask 25 * registers. 26 * - the armadaxp variant for Armada XP systems. This variant keeps 27 * the normal cause/edge mask/level mask registers when the global 28 * interrupts are used, but adds per-CPU cause/edge mask/level mask 29 * registers n a separate memory area for the per-CPU GPIO 30 * interrupts. 31 */ 32 33 #include <linux/bitops.h> 34 #include <linux/clk.h> 35 #include <linux/err.h> 36 #include <linux/gpio/driver.h> 37 #include <linux/gpio/consumer.h> 38 #include <linux/gpio/machine.h> 39 #include <linux/init.h> 40 #include <linux/io.h> 41 #include <linux/irq.h> 42 #include <linux/irqchip/chained_irq.h> 43 #include <linux/irqdomain.h> 44 #include <linux/mfd/syscon.h> 45 #include <linux/of_device.h> 46 #include <linux/pinctrl/consumer.h> 47 #include <linux/platform_device.h> 48 #include <linux/pwm.h> 49 #include <linux/regmap.h> 50 #include <linux/slab.h> 51 52 /* 53 * GPIO unit register offsets. 54 */ 55 #define GPIO_OUT_OFF 0x0000 56 #define GPIO_IO_CONF_OFF 0x0004 57 #define GPIO_BLINK_EN_OFF 0x0008 58 #define GPIO_IN_POL_OFF 0x000c 59 #define GPIO_DATA_IN_OFF 0x0010 60 #define GPIO_EDGE_CAUSE_OFF 0x0014 61 #define GPIO_EDGE_MASK_OFF 0x0018 62 #define GPIO_LEVEL_MASK_OFF 0x001c 63 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020 64 65 /* 66 * PWM register offsets. 67 */ 68 #define PWM_BLINK_ON_DURATION_OFF 0x0 69 #define PWM_BLINK_OFF_DURATION_OFF 0x4 70 #define PWM_BLINK_COUNTER_B_OFF 0x8 71 72 /* Armada 8k variant gpios register offsets */ 73 #define AP80X_GPIO0_OFF_A8K 0x1040 74 #define CP11X_GPIO0_OFF_A8K 0x100 75 #define CP11X_GPIO1_OFF_A8K 0x140 76 77 /* The MV78200 has per-CPU registers for edge mask and level mask */ 78 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) 79 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) 80 81 /* 82 * The Armada XP has per-CPU registers for interrupt cause, interrupt 83 * mask and interrupt level mask. Those are in percpu_regs range. 84 */ 85 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) 86 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) 87 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) 88 89 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 90 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 91 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 92 #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4 93 94 #define MVEBU_MAX_GPIO_PER_BANK 32 95 96 struct mvebu_pwm { 97 struct regmap *regs; 98 u32 offset; 99 unsigned long clk_rate; 100 struct gpio_desc *gpiod; 101 struct pwm_chip chip; 102 spinlock_t lock; 103 struct mvebu_gpio_chip *mvchip; 104 105 /* Used to preserve GPIO/PWM registers across suspend/resume */ 106 u32 blink_select; 107 u32 blink_on_duration; 108 u32 blink_off_duration; 109 }; 110 111 struct mvebu_gpio_chip { 112 struct gpio_chip chip; 113 struct regmap *regs; 114 u32 offset; 115 struct regmap *percpu_regs; 116 int irqbase; 117 struct irq_domain *domain; 118 int soc_variant; 119 120 /* Used for PWM support */ 121 struct clk *clk; 122 struct mvebu_pwm *mvpwm; 123 124 /* Used to preserve GPIO registers across suspend/resume */ 125 u32 out_reg; 126 u32 io_conf_reg; 127 u32 blink_en_reg; 128 u32 in_pol_reg; 129 u32 edge_mask_regs[4]; 130 u32 level_mask_regs[4]; 131 }; 132 133 /* 134 * Functions returning addresses of individual registers for a given 135 * GPIO controller. 136 */ 137 138 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip, 139 struct regmap **map, unsigned int *offset) 140 { 141 int cpu; 142 143 switch (mvchip->soc_variant) { 144 case MVEBU_GPIO_SOC_VARIANT_ORION: 145 case MVEBU_GPIO_SOC_VARIANT_MV78200: 146 case MVEBU_GPIO_SOC_VARIANT_A8K: 147 *map = mvchip->regs; 148 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset; 149 break; 150 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 151 cpu = smp_processor_id(); 152 *map = mvchip->percpu_regs; 153 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); 154 break; 155 default: 156 BUG(); 157 } 158 } 159 160 static u32 161 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip) 162 { 163 struct regmap *map; 164 unsigned int offset; 165 u32 val; 166 167 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); 168 regmap_read(map, offset, &val); 169 170 return val; 171 } 172 173 static void 174 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val) 175 { 176 struct regmap *map; 177 unsigned int offset; 178 179 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); 180 regmap_write(map, offset, val); 181 } 182 183 static inline void 184 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip, 185 struct regmap **map, unsigned int *offset) 186 { 187 int cpu; 188 189 switch (mvchip->soc_variant) { 190 case MVEBU_GPIO_SOC_VARIANT_ORION: 191 case MVEBU_GPIO_SOC_VARIANT_A8K: 192 *map = mvchip->regs; 193 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset; 194 break; 195 case MVEBU_GPIO_SOC_VARIANT_MV78200: 196 cpu = smp_processor_id(); 197 *map = mvchip->regs; 198 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu); 199 break; 200 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 201 cpu = smp_processor_id(); 202 *map = mvchip->percpu_regs; 203 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); 204 break; 205 default: 206 BUG(); 207 } 208 } 209 210 static u32 211 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip) 212 { 213 struct regmap *map; 214 unsigned int offset; 215 u32 val; 216 217 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); 218 regmap_read(map, offset, &val); 219 220 return val; 221 } 222 223 static void 224 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val) 225 { 226 struct regmap *map; 227 unsigned int offset; 228 229 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); 230 regmap_write(map, offset, val); 231 } 232 233 static void 234 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip, 235 struct regmap **map, unsigned int *offset) 236 { 237 int cpu; 238 239 switch (mvchip->soc_variant) { 240 case MVEBU_GPIO_SOC_VARIANT_ORION: 241 case MVEBU_GPIO_SOC_VARIANT_A8K: 242 *map = mvchip->regs; 243 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset; 244 break; 245 case MVEBU_GPIO_SOC_VARIANT_MV78200: 246 cpu = smp_processor_id(); 247 *map = mvchip->regs; 248 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu); 249 break; 250 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 251 cpu = smp_processor_id(); 252 *map = mvchip->percpu_regs; 253 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); 254 break; 255 default: 256 BUG(); 257 } 258 } 259 260 static u32 261 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip) 262 { 263 struct regmap *map; 264 unsigned int offset; 265 u32 val; 266 267 mvebu_gpioreg_level_mask(mvchip, &map, &offset); 268 regmap_read(map, offset, &val); 269 270 return val; 271 } 272 273 static void 274 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val) 275 { 276 struct regmap *map; 277 unsigned int offset; 278 279 mvebu_gpioreg_level_mask(mvchip, &map, &offset); 280 regmap_write(map, offset, val); 281 } 282 283 /* 284 * Functions returning offsets of individual registers for a given 285 * PWM controller. 286 */ 287 static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm) 288 { 289 return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF; 290 } 291 292 static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm) 293 { 294 return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF; 295 } 296 297 /* 298 * Functions implementing the gpio_chip methods 299 */ 300 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) 301 { 302 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 303 304 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 305 BIT(pin), value ? BIT(pin) : 0); 306 } 307 308 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin) 309 { 310 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 311 u32 u; 312 313 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 314 315 if (u & BIT(pin)) { 316 u32 data_in, in_pol; 317 318 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, 319 &data_in); 320 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 321 &in_pol); 322 u = data_in ^ in_pol; 323 } else { 324 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u); 325 } 326 327 return (u >> pin) & 1; 328 } 329 330 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin, 331 int value) 332 { 333 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 334 335 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 336 BIT(pin), value ? BIT(pin) : 0); 337 } 338 339 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) 340 { 341 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 342 int ret; 343 344 /* 345 * Check with the pinctrl driver whether this pin is usable as 346 * an input GPIO 347 */ 348 ret = pinctrl_gpio_direction_input(chip->base + pin); 349 if (ret) 350 return ret; 351 352 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 353 BIT(pin), BIT(pin)); 354 355 return 0; 356 } 357 358 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, 359 int value) 360 { 361 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 362 int ret; 363 364 /* 365 * Check with the pinctrl driver whether this pin is usable as 366 * an output GPIO 367 */ 368 ret = pinctrl_gpio_direction_output(chip->base + pin); 369 if (ret) 370 return ret; 371 372 mvebu_gpio_blink(chip, pin, 0); 373 mvebu_gpio_set(chip, pin, value); 374 375 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 376 BIT(pin), 0); 377 378 return 0; 379 } 380 381 static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) 382 { 383 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 384 u32 u; 385 386 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 387 388 if (u & BIT(pin)) 389 return GPIO_LINE_DIRECTION_IN; 390 391 return GPIO_LINE_DIRECTION_OUT; 392 } 393 394 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin) 395 { 396 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 397 398 return irq_create_mapping(mvchip->domain, pin); 399 } 400 401 /* 402 * Functions implementing the irq_chip methods 403 */ 404 static void mvebu_gpio_irq_ack(struct irq_data *d) 405 { 406 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 407 struct mvebu_gpio_chip *mvchip = gc->private; 408 u32 mask = d->mask; 409 410 irq_gc_lock(gc); 411 mvebu_gpio_write_edge_cause(mvchip, ~mask); 412 irq_gc_unlock(gc); 413 } 414 415 static void mvebu_gpio_edge_irq_mask(struct irq_data *d) 416 { 417 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 418 struct mvebu_gpio_chip *mvchip = gc->private; 419 struct irq_chip_type *ct = irq_data_get_chip_type(d); 420 u32 mask = d->mask; 421 422 irq_gc_lock(gc); 423 ct->mask_cache_priv &= ~mask; 424 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); 425 irq_gc_unlock(gc); 426 } 427 428 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) 429 { 430 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 431 struct mvebu_gpio_chip *mvchip = gc->private; 432 struct irq_chip_type *ct = irq_data_get_chip_type(d); 433 u32 mask = d->mask; 434 435 irq_gc_lock(gc); 436 mvebu_gpio_write_edge_cause(mvchip, ~mask); 437 ct->mask_cache_priv |= mask; 438 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); 439 irq_gc_unlock(gc); 440 } 441 442 static void mvebu_gpio_level_irq_mask(struct irq_data *d) 443 { 444 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 445 struct mvebu_gpio_chip *mvchip = gc->private; 446 struct irq_chip_type *ct = irq_data_get_chip_type(d); 447 u32 mask = d->mask; 448 449 irq_gc_lock(gc); 450 ct->mask_cache_priv &= ~mask; 451 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); 452 irq_gc_unlock(gc); 453 } 454 455 static void mvebu_gpio_level_irq_unmask(struct irq_data *d) 456 { 457 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 458 struct mvebu_gpio_chip *mvchip = gc->private; 459 struct irq_chip_type *ct = irq_data_get_chip_type(d); 460 u32 mask = d->mask; 461 462 irq_gc_lock(gc); 463 ct->mask_cache_priv |= mask; 464 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); 465 irq_gc_unlock(gc); 466 } 467 468 /***************************************************************************** 469 * MVEBU GPIO IRQ 470 * 471 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same 472 * value of the line or the opposite value. 473 * 474 * Level IRQ handlers: DATA_IN is used directly as cause register. 475 * Interrupt are masked by LEVEL_MASK registers. 476 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. 477 * Interrupt are masked by EDGE_MASK registers. 478 * Both-edge handlers: Similar to regular Edge handlers, but also swaps 479 * the polarity to catch the next line transaction. 480 * This is a race condition that might not perfectly 481 * work on some use cases. 482 * 483 * Every eight GPIO lines are grouped (OR'ed) before going up to main 484 * cause register. 485 * 486 * EDGE cause mask 487 * data-in /--------| |-----| |----\ 488 * -----| |----- ---- to main cause reg 489 * X \----------------| |----/ 490 * polarity LEVEL mask 491 * 492 ****************************************************************************/ 493 494 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) 495 { 496 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 497 struct irq_chip_type *ct = irq_data_get_chip_type(d); 498 struct mvebu_gpio_chip *mvchip = gc->private; 499 int pin; 500 u32 u; 501 502 pin = d->hwirq; 503 504 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 505 if ((u & BIT(pin)) == 0) 506 return -EINVAL; 507 508 type &= IRQ_TYPE_SENSE_MASK; 509 if (type == IRQ_TYPE_NONE) 510 return -EINVAL; 511 512 /* Check if we need to change chip and handler */ 513 if (!(ct->type & type)) 514 if (irq_setup_alt_chip(d, type)) 515 return -EINVAL; 516 517 /* 518 * Configure interrupt polarity. 519 */ 520 switch (type) { 521 case IRQ_TYPE_EDGE_RISING: 522 case IRQ_TYPE_LEVEL_HIGH: 523 regmap_update_bits(mvchip->regs, 524 GPIO_IN_POL_OFF + mvchip->offset, 525 BIT(pin), 0); 526 break; 527 case IRQ_TYPE_EDGE_FALLING: 528 case IRQ_TYPE_LEVEL_LOW: 529 regmap_update_bits(mvchip->regs, 530 GPIO_IN_POL_OFF + mvchip->offset, 531 BIT(pin), BIT(pin)); 532 break; 533 case IRQ_TYPE_EDGE_BOTH: { 534 u32 data_in, in_pol, val; 535 536 regmap_read(mvchip->regs, 537 GPIO_IN_POL_OFF + mvchip->offset, &in_pol); 538 regmap_read(mvchip->regs, 539 GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 540 541 /* 542 * set initial polarity based on current input level 543 */ 544 if ((data_in ^ in_pol) & BIT(pin)) 545 val = BIT(pin); /* falling */ 546 else 547 val = 0; /* raising */ 548 549 regmap_update_bits(mvchip->regs, 550 GPIO_IN_POL_OFF + mvchip->offset, 551 BIT(pin), val); 552 break; 553 } 554 } 555 return 0; 556 } 557 558 static void mvebu_gpio_irq_handler(struct irq_desc *desc) 559 { 560 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc); 561 struct irq_chip *chip = irq_desc_get_chip(desc); 562 u32 cause, type, data_in, level_mask, edge_cause, edge_mask; 563 int i; 564 565 if (mvchip == NULL) 566 return; 567 568 chained_irq_enter(chip, desc); 569 570 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 571 level_mask = mvebu_gpio_read_level_mask(mvchip); 572 edge_cause = mvebu_gpio_read_edge_cause(mvchip); 573 edge_mask = mvebu_gpio_read_edge_mask(mvchip); 574 575 cause = (data_in & level_mask) | (edge_cause & edge_mask); 576 577 for (i = 0; i < mvchip->chip.ngpio; i++) { 578 int irq; 579 580 irq = irq_find_mapping(mvchip->domain, i); 581 582 if (!(cause & BIT(i))) 583 continue; 584 585 type = irq_get_trigger_type(irq); 586 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 587 /* Swap polarity (race with GPIO line) */ 588 u32 polarity; 589 590 regmap_read(mvchip->regs, 591 GPIO_IN_POL_OFF + mvchip->offset, 592 &polarity); 593 polarity ^= BIT(i); 594 regmap_write(mvchip->regs, 595 GPIO_IN_POL_OFF + mvchip->offset, 596 polarity); 597 } 598 599 generic_handle_irq(irq); 600 } 601 602 chained_irq_exit(chip, desc); 603 } 604 605 static const struct regmap_config mvebu_gpio_regmap_config = { 606 .reg_bits = 32, 607 .reg_stride = 4, 608 .val_bits = 32, 609 .fast_io = true, 610 }; 611 612 /* 613 * Functions implementing the pwm_chip methods 614 */ 615 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) 616 { 617 return container_of(chip, struct mvebu_pwm, chip); 618 } 619 620 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 621 { 622 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 623 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 624 struct gpio_desc *desc; 625 unsigned long flags; 626 int ret = 0; 627 628 spin_lock_irqsave(&mvpwm->lock, flags); 629 630 if (mvpwm->gpiod) { 631 ret = -EBUSY; 632 } else { 633 desc = gpiochip_request_own_desc(&mvchip->chip, 634 pwm->hwpwm, "mvebu-pwm", 635 GPIO_ACTIVE_HIGH, 636 GPIOD_OUT_LOW); 637 if (IS_ERR(desc)) { 638 ret = PTR_ERR(desc); 639 goto out; 640 } 641 642 mvpwm->gpiod = desc; 643 } 644 out: 645 spin_unlock_irqrestore(&mvpwm->lock, flags); 646 return ret; 647 } 648 649 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 650 { 651 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 652 unsigned long flags; 653 654 spin_lock_irqsave(&mvpwm->lock, flags); 655 gpiochip_free_own_desc(mvpwm->gpiod); 656 mvpwm->gpiod = NULL; 657 spin_unlock_irqrestore(&mvpwm->lock, flags); 658 } 659 660 static void mvebu_pwm_get_state(struct pwm_chip *chip, 661 struct pwm_device *pwm, 662 struct pwm_state *state) { 663 664 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 665 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 666 unsigned long long val; 667 unsigned long flags; 668 u32 u; 669 670 spin_lock_irqsave(&mvpwm->lock, flags); 671 672 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u); 673 /* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */ 674 if (u > 0) 675 val = u; 676 else 677 val = UINT_MAX + 1ULL; 678 state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, 679 mvpwm->clk_rate); 680 681 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u); 682 /* period = on + off duration */ 683 if (u > 0) 684 val += u; 685 else 686 val += UINT_MAX + 1ULL; 687 state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate); 688 689 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); 690 if (u) 691 state->enabled = true; 692 else 693 state->enabled = false; 694 695 spin_unlock_irqrestore(&mvpwm->lock, flags); 696 } 697 698 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 699 const struct pwm_state *state) 700 { 701 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 702 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 703 unsigned long long val; 704 unsigned long flags; 705 unsigned int on, off; 706 707 if (state->polarity != PWM_POLARITY_NORMAL) 708 return -EINVAL; 709 710 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; 711 do_div(val, NSEC_PER_SEC); 712 if (val > UINT_MAX + 1ULL) 713 return -EINVAL; 714 /* 715 * Zero on/off values don't work as expected. Experimentation shows 716 * that zero value is treated as 2^32. This behavior is not documented. 717 */ 718 if (val == UINT_MAX + 1ULL) 719 on = 0; 720 else if (val) 721 on = val; 722 else 723 on = 1; 724 725 val = (unsigned long long) mvpwm->clk_rate * state->period; 726 do_div(val, NSEC_PER_SEC); 727 val -= on; 728 if (val > UINT_MAX + 1ULL) 729 return -EINVAL; 730 if (val == UINT_MAX + 1ULL) 731 off = 0; 732 else if (val) 733 off = val; 734 else 735 off = 1; 736 737 spin_lock_irqsave(&mvpwm->lock, flags); 738 739 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on); 740 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off); 741 if (state->enabled) 742 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); 743 else 744 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); 745 746 spin_unlock_irqrestore(&mvpwm->lock, flags); 747 748 return 0; 749 } 750 751 static const struct pwm_ops mvebu_pwm_ops = { 752 .request = mvebu_pwm_request, 753 .free = mvebu_pwm_free, 754 .get_state = mvebu_pwm_get_state, 755 .apply = mvebu_pwm_apply, 756 .owner = THIS_MODULE, 757 }; 758 759 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) 760 { 761 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 762 763 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, 764 &mvpwm->blink_select); 765 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), 766 &mvpwm->blink_on_duration); 767 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), 768 &mvpwm->blink_off_duration); 769 } 770 771 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) 772 { 773 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 774 775 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, 776 mvpwm->blink_select); 777 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), 778 mvpwm->blink_on_duration); 779 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), 780 mvpwm->blink_off_duration); 781 } 782 783 static int mvebu_pwm_probe(struct platform_device *pdev, 784 struct mvebu_gpio_chip *mvchip, 785 int id) 786 { 787 struct device *dev = &pdev->dev; 788 struct mvebu_pwm *mvpwm; 789 void __iomem *base; 790 u32 offset; 791 u32 set; 792 793 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { 794 int ret = of_property_read_u32(dev->of_node, 795 "marvell,pwm-offset", &offset); 796 if (ret < 0) 797 return 0; 798 } else { 799 /* 800 * There are only two sets of PWM configuration registers for 801 * all the GPIO lines on those SoCs which this driver reserves 802 * for the first two GPIO chips. So if the resource is missing 803 * we can't treat it as an error. 804 */ 805 if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm")) 806 return 0; 807 offset = 0; 808 } 809 810 if (IS_ERR(mvchip->clk)) 811 return PTR_ERR(mvchip->clk); 812 813 mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL); 814 if (!mvpwm) 815 return -ENOMEM; 816 mvchip->mvpwm = mvpwm; 817 mvpwm->mvchip = mvchip; 818 mvpwm->offset = offset; 819 820 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { 821 mvpwm->regs = mvchip->regs; 822 823 switch (mvchip->offset) { 824 case AP80X_GPIO0_OFF_A8K: 825 case CP11X_GPIO0_OFF_A8K: 826 /* Blink counter A */ 827 set = 0; 828 break; 829 case CP11X_GPIO1_OFF_A8K: 830 /* Blink counter B */ 831 set = U32_MAX; 832 mvpwm->offset += PWM_BLINK_COUNTER_B_OFF; 833 break; 834 default: 835 return -EINVAL; 836 } 837 } else { 838 base = devm_platform_ioremap_resource_byname(pdev, "pwm"); 839 if (IS_ERR(base)) 840 return PTR_ERR(base); 841 842 mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base, 843 &mvebu_gpio_regmap_config); 844 if (IS_ERR(mvpwm->regs)) 845 return PTR_ERR(mvpwm->regs); 846 847 /* 848 * Use set A for lines of GPIO chip with id 0, B for GPIO chip 849 * with id 1. Don't allow further GPIO chips to be used for PWM. 850 */ 851 if (id == 0) 852 set = 0; 853 else if (id == 1) 854 set = U32_MAX; 855 else 856 return -EINVAL; 857 } 858 859 regmap_write(mvchip->regs, 860 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); 861 862 mvpwm->clk_rate = clk_get_rate(mvchip->clk); 863 if (!mvpwm->clk_rate) { 864 dev_err(dev, "failed to get clock rate\n"); 865 return -EINVAL; 866 } 867 868 mvpwm->chip.dev = dev; 869 mvpwm->chip.ops = &mvebu_pwm_ops; 870 mvpwm->chip.npwm = mvchip->chip.ngpio; 871 872 spin_lock_init(&mvpwm->lock); 873 874 return pwmchip_add(&mvpwm->chip); 875 } 876 877 #ifdef CONFIG_DEBUG_FS 878 #include <linux/seq_file.h> 879 880 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 881 { 882 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 883 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; 884 const char *label; 885 int i; 886 887 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out); 888 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf); 889 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink); 890 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol); 891 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 892 cause = mvebu_gpio_read_edge_cause(mvchip); 893 edg_msk = mvebu_gpio_read_edge_mask(mvchip); 894 lvl_msk = mvebu_gpio_read_level_mask(mvchip); 895 896 for_each_requested_gpio(chip, i, label) { 897 u32 msk; 898 bool is_out; 899 900 msk = BIT(i); 901 is_out = !(io_conf & msk); 902 903 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); 904 905 if (is_out) { 906 seq_printf(s, " out %s %s\n", 907 out & msk ? "hi" : "lo", 908 blink & msk ? "(blink )" : ""); 909 continue; 910 } 911 912 seq_printf(s, " in %s (act %s) - IRQ", 913 (data_in ^ in_pol) & msk ? "hi" : "lo", 914 in_pol & msk ? "lo" : "hi"); 915 if (!((edg_msk | lvl_msk) & msk)) { 916 seq_puts(s, " disabled\n"); 917 continue; 918 } 919 if (edg_msk & msk) 920 seq_puts(s, " edge "); 921 if (lvl_msk & msk) 922 seq_puts(s, " level"); 923 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); 924 } 925 } 926 #else 927 #define mvebu_gpio_dbg_show NULL 928 #endif 929 930 static const struct of_device_id mvebu_gpio_of_match[] = { 931 { 932 .compatible = "marvell,orion-gpio", 933 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 934 }, 935 { 936 .compatible = "marvell,mv78200-gpio", 937 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, 938 }, 939 { 940 .compatible = "marvell,armadaxp-gpio", 941 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, 942 }, 943 { 944 .compatible = "marvell,armada-370-gpio", 945 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 946 }, 947 { 948 .compatible = "marvell,armada-8k-gpio", 949 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K, 950 }, 951 { 952 /* sentinel */ 953 }, 954 }; 955 956 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) 957 { 958 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 959 int i; 960 961 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 962 &mvchip->out_reg); 963 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 964 &mvchip->io_conf_reg); 965 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 966 &mvchip->blink_en_reg); 967 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 968 &mvchip->in_pol_reg); 969 970 switch (mvchip->soc_variant) { 971 case MVEBU_GPIO_SOC_VARIANT_ORION: 972 case MVEBU_GPIO_SOC_VARIANT_A8K: 973 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, 974 &mvchip->edge_mask_regs[0]); 975 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, 976 &mvchip->level_mask_regs[0]); 977 break; 978 case MVEBU_GPIO_SOC_VARIANT_MV78200: 979 for (i = 0; i < 2; i++) { 980 regmap_read(mvchip->regs, 981 GPIO_EDGE_MASK_MV78200_OFF(i), 982 &mvchip->edge_mask_regs[i]); 983 regmap_read(mvchip->regs, 984 GPIO_LEVEL_MASK_MV78200_OFF(i), 985 &mvchip->level_mask_regs[i]); 986 } 987 break; 988 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 989 for (i = 0; i < 4; i++) { 990 regmap_read(mvchip->regs, 991 GPIO_EDGE_MASK_ARMADAXP_OFF(i), 992 &mvchip->edge_mask_regs[i]); 993 regmap_read(mvchip->regs, 994 GPIO_LEVEL_MASK_ARMADAXP_OFF(i), 995 &mvchip->level_mask_regs[i]); 996 } 997 break; 998 default: 999 BUG(); 1000 } 1001 1002 if (IS_ENABLED(CONFIG_PWM)) 1003 mvebu_pwm_suspend(mvchip); 1004 1005 return 0; 1006 } 1007 1008 static int mvebu_gpio_resume(struct platform_device *pdev) 1009 { 1010 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 1011 int i; 1012 1013 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 1014 mvchip->out_reg); 1015 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 1016 mvchip->io_conf_reg); 1017 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 1018 mvchip->blink_en_reg); 1019 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 1020 mvchip->in_pol_reg); 1021 1022 switch (mvchip->soc_variant) { 1023 case MVEBU_GPIO_SOC_VARIANT_ORION: 1024 case MVEBU_GPIO_SOC_VARIANT_A8K: 1025 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, 1026 mvchip->edge_mask_regs[0]); 1027 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, 1028 mvchip->level_mask_regs[0]); 1029 break; 1030 case MVEBU_GPIO_SOC_VARIANT_MV78200: 1031 for (i = 0; i < 2; i++) { 1032 regmap_write(mvchip->regs, 1033 GPIO_EDGE_MASK_MV78200_OFF(i), 1034 mvchip->edge_mask_regs[i]); 1035 regmap_write(mvchip->regs, 1036 GPIO_LEVEL_MASK_MV78200_OFF(i), 1037 mvchip->level_mask_regs[i]); 1038 } 1039 break; 1040 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 1041 for (i = 0; i < 4; i++) { 1042 regmap_write(mvchip->regs, 1043 GPIO_EDGE_MASK_ARMADAXP_OFF(i), 1044 mvchip->edge_mask_regs[i]); 1045 regmap_write(mvchip->regs, 1046 GPIO_LEVEL_MASK_ARMADAXP_OFF(i), 1047 mvchip->level_mask_regs[i]); 1048 } 1049 break; 1050 default: 1051 BUG(); 1052 } 1053 1054 if (IS_ENABLED(CONFIG_PWM)) 1055 mvebu_pwm_resume(mvchip); 1056 1057 return 0; 1058 } 1059 1060 static int mvebu_gpio_probe_raw(struct platform_device *pdev, 1061 struct mvebu_gpio_chip *mvchip) 1062 { 1063 void __iomem *base; 1064 1065 base = devm_platform_ioremap_resource(pdev, 0); 1066 if (IS_ERR(base)) 1067 return PTR_ERR(base); 1068 1069 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, 1070 &mvebu_gpio_regmap_config); 1071 if (IS_ERR(mvchip->regs)) 1072 return PTR_ERR(mvchip->regs); 1073 1074 /* 1075 * For the legacy SoCs, the regmap directly maps to the GPIO 1076 * registers, so no offset is needed. 1077 */ 1078 mvchip->offset = 0; 1079 1080 /* 1081 * The Armada XP has a second range of registers for the 1082 * per-CPU registers 1083 */ 1084 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { 1085 base = devm_platform_ioremap_resource(pdev, 1); 1086 if (IS_ERR(base)) 1087 return PTR_ERR(base); 1088 1089 mvchip->percpu_regs = 1090 devm_regmap_init_mmio(&pdev->dev, base, 1091 &mvebu_gpio_regmap_config); 1092 if (IS_ERR(mvchip->percpu_regs)) 1093 return PTR_ERR(mvchip->percpu_regs); 1094 } 1095 1096 return 0; 1097 } 1098 1099 static int mvebu_gpio_probe_syscon(struct platform_device *pdev, 1100 struct mvebu_gpio_chip *mvchip) 1101 { 1102 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); 1103 if (IS_ERR(mvchip->regs)) 1104 return PTR_ERR(mvchip->regs); 1105 1106 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset)) 1107 return -EINVAL; 1108 1109 return 0; 1110 } 1111 1112 static int mvebu_gpio_probe(struct platform_device *pdev) 1113 { 1114 struct mvebu_gpio_chip *mvchip; 1115 const struct of_device_id *match; 1116 struct device_node *np = pdev->dev.of_node; 1117 struct irq_chip_generic *gc; 1118 struct irq_chip_type *ct; 1119 unsigned int ngpios; 1120 bool have_irqs; 1121 int soc_variant; 1122 int i, cpu, id; 1123 int err; 1124 1125 match = of_match_device(mvebu_gpio_of_match, &pdev->dev); 1126 if (match) 1127 soc_variant = (unsigned long) match->data; 1128 else 1129 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; 1130 1131 /* Some gpio controllers do not provide irq support */ 1132 err = platform_irq_count(pdev); 1133 if (err < 0) 1134 return err; 1135 1136 have_irqs = err != 0; 1137 1138 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), 1139 GFP_KERNEL); 1140 if (!mvchip) 1141 return -ENOMEM; 1142 1143 platform_set_drvdata(pdev, mvchip); 1144 1145 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { 1146 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 1147 return -ENODEV; 1148 } 1149 1150 id = of_alias_get_id(pdev->dev.of_node, "gpio"); 1151 if (id < 0) { 1152 dev_err(&pdev->dev, "Couldn't get OF id\n"); 1153 return id; 1154 } 1155 1156 mvchip->clk = devm_clk_get(&pdev->dev, NULL); 1157 /* Not all SoCs require a clock.*/ 1158 if (!IS_ERR(mvchip->clk)) 1159 clk_prepare_enable(mvchip->clk); 1160 1161 mvchip->soc_variant = soc_variant; 1162 mvchip->chip.label = dev_name(&pdev->dev); 1163 mvchip->chip.parent = &pdev->dev; 1164 mvchip->chip.request = gpiochip_generic_request; 1165 mvchip->chip.free = gpiochip_generic_free; 1166 mvchip->chip.get_direction = mvebu_gpio_get_direction; 1167 mvchip->chip.direction_input = mvebu_gpio_direction_input; 1168 mvchip->chip.get = mvebu_gpio_get; 1169 mvchip->chip.direction_output = mvebu_gpio_direction_output; 1170 mvchip->chip.set = mvebu_gpio_set; 1171 if (have_irqs) 1172 mvchip->chip.to_irq = mvebu_gpio_to_irq; 1173 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; 1174 mvchip->chip.ngpio = ngpios; 1175 mvchip->chip.can_sleep = false; 1176 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; 1177 1178 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) 1179 err = mvebu_gpio_probe_syscon(pdev, mvchip); 1180 else 1181 err = mvebu_gpio_probe_raw(pdev, mvchip); 1182 1183 if (err) 1184 return err; 1185 1186 /* 1187 * Mask and clear GPIO interrupts. 1188 */ 1189 switch (soc_variant) { 1190 case MVEBU_GPIO_SOC_VARIANT_ORION: 1191 case MVEBU_GPIO_SOC_VARIANT_A8K: 1192 regmap_write(mvchip->regs, 1193 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0); 1194 regmap_write(mvchip->regs, 1195 GPIO_EDGE_MASK_OFF + mvchip->offset, 0); 1196 regmap_write(mvchip->regs, 1197 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0); 1198 break; 1199 case MVEBU_GPIO_SOC_VARIANT_MV78200: 1200 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); 1201 for (cpu = 0; cpu < 2; cpu++) { 1202 regmap_write(mvchip->regs, 1203 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0); 1204 regmap_write(mvchip->regs, 1205 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0); 1206 } 1207 break; 1208 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 1209 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); 1210 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); 1211 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); 1212 for (cpu = 0; cpu < 4; cpu++) { 1213 regmap_write(mvchip->percpu_regs, 1214 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0); 1215 regmap_write(mvchip->percpu_regs, 1216 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0); 1217 regmap_write(mvchip->percpu_regs, 1218 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0); 1219 } 1220 break; 1221 default: 1222 BUG(); 1223 } 1224 1225 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); 1226 1227 /* Some MVEBU SoCs have simple PWM support for GPIO lines */ 1228 if (IS_ENABLED(CONFIG_PWM)) { 1229 err = mvebu_pwm_probe(pdev, mvchip, id); 1230 if (err) 1231 return err; 1232 } 1233 1234 /* Some gpio controllers do not provide irq support */ 1235 if (!have_irqs) 1236 return 0; 1237 1238 mvchip->domain = 1239 irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL); 1240 if (!mvchip->domain) { 1241 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", 1242 mvchip->chip.label); 1243 err = -ENODEV; 1244 goto err_pwm; 1245 } 1246 1247 err = irq_alloc_domain_generic_chips( 1248 mvchip->domain, ngpios, 2, np->name, handle_level_irq, 1249 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0); 1250 if (err) { 1251 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", 1252 mvchip->chip.label); 1253 goto err_domain; 1254 } 1255 1256 /* 1257 * NOTE: The common accessors cannot be used because of the percpu 1258 * access to the mask registers 1259 */ 1260 gc = irq_get_domain_generic_chip(mvchip->domain, 0); 1261 gc->private = mvchip; 1262 ct = &gc->chip_types[0]; 1263 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 1264 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; 1265 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; 1266 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1267 ct->chip.name = mvchip->chip.label; 1268 1269 ct = &gc->chip_types[1]; 1270 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 1271 ct->chip.irq_ack = mvebu_gpio_irq_ack; 1272 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; 1273 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; 1274 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1275 ct->handler = handle_edge_irq; 1276 ct->chip.name = mvchip->chip.label; 1277 1278 /* 1279 * Setup the interrupt handlers. Each chip can have up to 4 1280 * interrupt handlers, with each handler dealing with 8 GPIO 1281 * pins. 1282 */ 1283 for (i = 0; i < 4; i++) { 1284 int irq = platform_get_irq_optional(pdev, i); 1285 1286 if (irq < 0) 1287 continue; 1288 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler, 1289 mvchip); 1290 } 1291 1292 return 0; 1293 1294 err_domain: 1295 irq_domain_remove(mvchip->domain); 1296 err_pwm: 1297 pwmchip_remove(&mvchip->mvpwm->chip); 1298 1299 return err; 1300 } 1301 1302 static struct platform_driver mvebu_gpio_driver = { 1303 .driver = { 1304 .name = "mvebu-gpio", 1305 .of_match_table = mvebu_gpio_of_match, 1306 }, 1307 .probe = mvebu_gpio_probe, 1308 .suspend = mvebu_gpio_suspend, 1309 .resume = mvebu_gpio_resume, 1310 }; 1311 builtin_platform_driver(mvebu_gpio_driver); 1312